SG10201905833RA - Semiconductor device and manufacturing method of the semiconductor device - Google Patents
Semiconductor device and manufacturing method of the semiconductor deviceInfo
- Publication number
- SG10201905833RA SG10201905833RA SG10201905833RA SG10201905833RA SG10201905833RA SG 10201905833R A SG10201905833R A SG 10201905833RA SG 10201905833R A SG10201905833R A SG 10201905833RA SG 10201905833R A SG10201905833R A SG 10201905833RA SG 10201905833R A SG10201905833R A SG 10201905833RA
- Authority
- SG
- Singapore
- Prior art keywords
- semiconductor device
- manufacturing
- semiconductor
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title 2
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020180086842A KR102618309B1 (ko) | 2018-07-25 | 2018-07-25 | 반도체 장치 및 그 제조방법 |
Publications (1)
Publication Number | Publication Date |
---|---|
SG10201905833RA true SG10201905833RA (en) | 2020-02-27 |
Family
ID=69177498
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG10201905833RA SG10201905833RA (en) | 2018-07-25 | 2019-06-24 | Semiconductor device and manufacturing method of the semiconductor device |
Country Status (4)
Country | Link |
---|---|
US (2) | US11114454B2 (zh) |
KR (1) | KR102618309B1 (zh) |
CN (1) | CN110767657B (zh) |
SG (1) | SG10201905833RA (zh) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102666113B1 (ko) * | 2018-10-08 | 2024-05-17 | 삼성전자주식회사 | 3차원 반도체 메모리 소자 |
JP2021048304A (ja) * | 2019-09-19 | 2021-03-25 | キオクシア株式会社 | 半導体記憶装置および半導体記憶装置の製造方法 |
KR20210155266A (ko) * | 2020-06-15 | 2021-12-22 | 에스케이하이닉스 주식회사 | 반도체 장치 및 반도체 장치의 제조 방법 |
KR20220036053A (ko) | 2020-09-15 | 2022-03-22 | 삼성전자주식회사 | 반도체 장치 및 이를 포함하는 데이터 저장 시스템 |
US11723196B2 (en) | 2020-10-05 | 2023-08-08 | Micron Technology, Inc. | Microelectronic devices with support pillars spaced along a slit region between pillar array blocks, and related systems |
KR20220157142A (ko) * | 2021-05-20 | 2022-11-29 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 및 그 제조 방법 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05175243A (ja) * | 1991-12-26 | 1993-07-13 | Toshiba Corp | 半導体装置の製造方法 |
TW548832B (en) * | 2001-03-08 | 2003-08-21 | Hitachi Ltd | Method of producing semiconductor integrated circuit device and semiconductor integrated circuit device |
JP4088120B2 (ja) * | 2002-08-12 | 2008-05-21 | 株式会社ルネサステクノロジ | 半導体装置 |
KR100750950B1 (ko) * | 2006-07-18 | 2007-08-22 | 삼성전자주식회사 | 반도체 장치의 배선 구조물 및 그 형성 방법, 비휘발성메모리 장치 및 그 제조 방법 |
KR101147526B1 (ko) | 2010-04-02 | 2012-05-21 | 서울대학교산학협력단 | 전기적 초기화로 층간 구별되는 3차원 낸드 플래시 메모리 어레이 및 그 제조방법 |
KR20150116510A (ko) * | 2014-04-07 | 2015-10-16 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조방법 |
KR20160061174A (ko) * | 2014-11-21 | 2016-05-31 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조방법 |
KR102449571B1 (ko) * | 2015-08-07 | 2022-10-04 | 삼성전자주식회사 | 반도체 장치 |
US9831266B2 (en) * | 2015-11-20 | 2017-11-28 | Sandisk Technologies Llc | Three-dimensional NAND device containing support pedestal structures for a buried source line and method of making the same |
KR102543998B1 (ko) * | 2015-12-03 | 2023-06-16 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조 방법 |
KR102581032B1 (ko) * | 2015-12-08 | 2023-09-22 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조 방법 |
US10038006B2 (en) | 2015-12-22 | 2018-07-31 | Sandisk Technologies Llc | Through-memory-level via structures for a three-dimensional memory device |
KR102607825B1 (ko) * | 2016-01-18 | 2023-11-30 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조 방법 |
US10141327B2 (en) * | 2016-03-18 | 2018-11-27 | Toshiba Memory Corporation | Semiconductor memory device |
KR20180047639A (ko) * | 2016-11-01 | 2018-05-10 | 삼성전자주식회사 | 수직형 메모리 장치 및 그 제조 방법 |
JP2018107230A (ja) * | 2016-12-26 | 2018-07-05 | 猛英 白土 | 半導体装置及びその製造方法 |
JP2018152412A (ja) * | 2017-03-10 | 2018-09-27 | 東芝メモリ株式会社 | 半導体装置及びその製造方法 |
-
2018
- 2018-07-25 KR KR1020180086842A patent/KR102618309B1/ko active IP Right Grant
-
2019
- 2019-03-12 US US16/299,252 patent/US11114454B2/en active Active
- 2019-04-15 CN CN201910299348.8A patent/CN110767657B/zh active Active
- 2019-06-24 SG SG10201905833RA patent/SG10201905833RA/en unknown
-
2021
- 2021-08-05 US US17/395,093 patent/US11871568B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
CN110767657B (zh) | 2023-12-12 |
US11114454B2 (en) | 2021-09-07 |
CN110767657A (zh) | 2020-02-07 |
KR20200011852A (ko) | 2020-02-04 |
KR102618309B1 (ko) | 2023-12-27 |
US11871568B2 (en) | 2024-01-09 |
US20210366929A1 (en) | 2021-11-25 |
US20200035702A1 (en) | 2020-01-30 |
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