MX2010014181A - Interconexion de puente de vias a traves de silicio. - Google Patents
Interconexion de puente de vias a traves de silicio.Info
- Publication number
- MX2010014181A MX2010014181A MX2010014181A MX2010014181A MX2010014181A MX 2010014181 A MX2010014181 A MX 2010014181A MX 2010014181 A MX2010014181 A MX 2010014181A MX 2010014181 A MX2010014181 A MX 2010014181A MX 2010014181 A MX2010014181 A MX 2010014181A
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Abstract
Un sistema de interconexión de puente de circuito integrado incluye una primera matriz y una segunda matriz proporcionadas en una configuración lado a lado y eléctricamente interconectadas entre sí a través de una matriz de puente; la matriz de puente incluye vías a través del silicio (TSV) para conectar líneas de interconexión conductoras en la matriz de puente a la primera matriz y la segunda matriz; circuiteria activa, diferente a las líneas de interconexión, puede ser proporcionada en la matriz de puente; al menos una o más matrices adicionales pueden estar apiladas en la matriz de puente e interconectadas a la matriz de puente.
Description
INTERCONEXION DE PUENTE DE VIAS A TRAVES DE SILI
CAMPO DE LA INVENCION
Esta descripción se refiere a empaquetami itos integrados (IC), y de manera más espec conexiones de puente entre circuitos integrados dentro de un paquete de substrato.
ANTECEDENTES DE LA INVENCION
En el empaquetamiento IC existe la neces rcionar matrices de semiconductor en una confi a-lado dentro de un paquete y su interconex te puede ser, por ejemplo, un paquete de bast ctores .
En una configuración, las matrices de semic mpaquetadas con el lado activo de cada matriz
ado por el tamaño de las interconexiones. Ade tancia de los conductores en la unión con cable riz puede limitar el rendimiento del dis uetado. Además, el cable de oro es una ncional para unión con cable, increi ficativamente el costo neto del paquete.
En otra configuración, el empaquetamie dura de bolita de chip basculante, la región ac sitivo de la matriz está sobre la superficie que rato de montaje de paquete, por ejemplo, hacia a configuración, la densidad de la interconexió ces adyacentes también queda limitada p rimientos de tamaño de la almohadilla de contact
La Patente de los Estados Unidos No. 5 ga la interconexión de dos matrices de semicond
scribe un método para formar los conductores de sición en el puente, de silicio. Además, el m ble de los conductores de has puede ser difici e ocupa espacio entre las dos matrices. Además, el oro es un metal de interconexión preferido, to en el costo del material del paquete ensambla
Por lo tanto, existe la necesidad de un si conexión de empaquetamiento entre matri onductor adyacentes que simplifique el pro ble, reduzca el costo de los materiales de inter mita la interconexión entre chips con un espac ino de lo que convencionalmente se permite con cable e interconexiones de conductores . alentes .
SUMARIO DE LA INVENCION
segundo lado y una segunda matriz que tiene u y un segundo lado. Estas matrices son proporció configuración lado-por-ladó . Una matriz de puen ada en los primeros lados de la primera matr da matriz. La matriz de puente interconecta la z y la segunda matriz.
Un sistema de empaquetamiento de circuito i ye un paquete para contener matrices de semicon ubstrato colocado dentro del paquete para ces de semiconductor. Una primera matriz y una z, ambas con un primer lado y un segundo lado adas sobre el substrato en una configuración l Los segundos lados de la primera y segunda hacia el substrato. Una matriz de puente está os primeros lados de la primera matriz y la
ca debieran apreciar que la concepción y la m ifica descrita se pueden utilizar fácilmente c para modificar o diseñar otras estructuras que los mismos propósitos de la presente invención. tos en la técnica también debieran observar qu rucciones equivalentes no se aparten del esp ce de la invención tal como se establece ndicaciones anexas. Las características novedosa son la característica de la invención, tanto en efiere a su organización como al método de op con objetivos y ventajas adicionales, se en a partir de la siguiente descripción cu deren en conexión con las figuras acompañan nte, se debería entender de forma expresa que s figuras se proporciona con el propósito de ilu
mbrica ejemplar en el cual de manera convenÍ n emplear las modalidades de la invención.
La figura 2 ilustra una vista plana conexión de puente TSV de acuerdo con una moda vención .
La figura 3 es una vista en sección transv s ejemplar de una modalidad de la intercone e entre dos matrices de chip basculante .
La figura 4 es una vista en sección transv s ejemplar de una modalidad de la intercone e entre dos matrices de unión con cable.
La figura 5 es una vista en sección transv s ejemplar de una modalidad de la intercone e entre una matriz de chip basculante y una ma con cable.
zando una matriz de puente de intercone onductor (típicamente silicio) para hacer cont matrices lado-a-lado. La matriz de pue conexión tiene vías a través del silicio para almohadillas de contacto en cada de las matric ficie opuesta de la matriz de puente de interc líneas de interconexión en la matriz de pu conexión se forman para completar las conexion ías a través del silicio.
La figura 1 muestra un sistema de comú mbrica ejemplar 100 en el cual se puede emp a conveniente una modalidad de la invenció sitos de ilustración, la figura 1 muestra tres as 120, 130 y 150 y dos estaciones base ocerá que sistemas de comunicación inalámbrica n tener muchas más unidades remotas estacion
En la figura 1, la unidad remota 120 se un teléfono móvil, la unidad remota 130 se mues omputadora portátil, y la unidad remota 150 se una unidad remota de ubicación fija en un sis local inalámbrico. Por ejemplo, las unidades n ser teléfonos celulares, unidades de sist icación personal manuales (PCS) , unidades d tiles tales como asistentes de datos person des de datos de ubicación fija, tales como e ra de medidores. Aunque la figura 1 ilustra as de acuerdo con las enseñanzas de la invenc ción no queda limitada a estas unidades ej radas . La invención se puede emplear de niente en cualquier dispositivo que incluya un lti-chip que tenga chips en una configuración l
matrices 220 y 230 se muestran colocadas guración lado-por-lado . Una superficie de las 230 se puede conectar al substrato 210, y event conductores del paquete.
Una matriz de interconexión de puente 240 q imer y un segundo lados al menos traslapa parcia omunica eléctricamente- con las matrices 220 y a través del silicio (TSV) 270 rellenadas con ctor, conectan el primer lado (que se muestra fuera de la página) de la matriz de intercon e 240 a la circuiteria activa en las matrices 22 lineas de interconexión 272 en el primer lad z de interconexión de puente 240 entonces compl iones entre las matrices 220 y 230. Para di aciones funcionales, donde las funciones especi
os {es decir, transistores, lógica, memoria, e no se muestra en la figura 2, el primer lad z de interconexión de puente 240 puede iteria activa adicional, no relacionada onalidad de interconexión.
Las lineas de interconexión 272 y/o circui triz de interconexión de puente 240 se pueden f de pastilla, incluyendo la formación de los nados con metal de las TSV 270 utilizando proc ización y semiconductor convencionales, despué la pastilla entonces puede ser separada en mat conexión de puente' individuales 240.
La figura 3 es una vista en sección transv
I
s ejemplar de una modalidad de una configuració interconexión de puente entre dos matrices
'
ran mirando hacia arriba en la figura 2) iteria activa en los segundos lados de las matr .
Las almohadillas de. contacto 371 en el segú matriz de interconexión de puente 240 y los de las matrices 320 y 330 están alineadas, y pu s utilizando métodos tales como, por ejemplo, dura de bolita y la pasta conductora. Las almo ontacto 371 formadas en las matrices 320, 33 itan el contacto conductivo entre
spondientes 270 y 373. En consecuencia, la cir a en las matrices 320 y 330 está c ricamente al primer lado de la matriz de inter ente 240, en donde la interconexión entre la cir a es completada utilizando las lineas de inter Las almohadillas de contacto 371 se
, la figura 3. Es decir, la matriz de intercon e 240 de la figura 4 puede tener las teristicas y arreglo de las TSV 270, almohadi cto 371, lineas de interconexión 272 y opcion ntos de impedancia y/o dispositivos activos, ados sobre el primer lado de la matriz de inter ente 240 de la figura 3.
Las matrices de unión con cable de semic 430 tienen un primer lado y un segundo lado, d dos lados de las matrices 420 y 430 miran y está bstrato 210. La unión con cable conecta las almo ntacto sobre los primeros lados de las matrice las almohadillas de contacto sobre el substrato que en la configuración de chip basculante 30 a 3, las tres matrices 420, 430 y 240 adillas e cont c 371 en ic i n orres o
estra en la figura 4, se puede incluir opcional no ser requerida.
La figura 5 es una vista en sección transv s ejemplar de una modalidad de una configuració interconexión de puente entre la matriz lante 320 y la matriz de unión con cable nsación apropiada se puede obtener para dif ivas en grosores de matriz, altura de unión de para colocar los primeros lados de ambas matric a la misma altura. Una consideración de in iadas entre matrices de chip basculante, puente able son las mismas que se describieron con refe iguras 3 y 4. Por ejemplo, la matriz de chip ba iene circuiteria activa colocada en el segundo , mirando al substrato 210) y puede reque lidad de TSV 373 conectadas a la lm h i
iar de una modalidad de una configuración 600 en enos una o más matrices adicionales 640 (dond sitos ilustrativos, solamente se muestra una mat apiladas en la matriz de interconexión de¦ pue atriz adicional 640 puede incluir una funció logía de material u otra base para formar la ma adamente de otras matrices 320, 430 que c sitivos activos. La matriz de puente de inter uede incluir almohadillas de contacto 371 en e para conectarse en interfaz con las almohadi cto correspondiente 371 que miran en dirección o están ubicadas 'en la matriz 640. La matriz 64 ir las TSV 674 conectadas a las almohadillas de en ambos lados de la matriz 640 para prop conexión entre la matriz de puente de intercone
da) , la disposición de la circuiteria puede uiera del primer o el segundo lado de la matriz
Numerosas ventajas se pueden derivar idades descritas. Al utilizar una matriz de pue s de interconexión se pueden fabricar en can a de pastilla utilizando procesos de semicondu r de la metalización puede ser en el orden as mieras o menos, con anchos de linea convenien de tecnología de avance, tal como 45 nm y m puede ser otro que no sea oro. En comparación de cable de oro entre los substratos, se var ahorros sustanciales de material.
De manera adicional, la unión con cable separación mínima entre almohadillas de entes sobre un substrato, por motivos debido,
Además, en la situación donde una configur chip lado-a-lado ha sido diseñada previamen con cable, una interconexión de puente pu mentada de manera benéfica para reemplazar la u , mientras se hace uso de las almohadillas de entes. Un reemplazo de la interconexión de pue ión con cable reduce el número de pasos del ens-ión a los múltiples pasos de' unión con cable s una colocación de matriz sencilla.
Incluso todavía, la unión con cable por lo ucra un bucle en el arco del cable ent adillas de unión además de una distancia r a entre las almohadillas de unión. Como result tancia del cable puede degradar el rend ialmente en dispositivos de alta velocidad d
es de cable.
Una ventaja adicional todavía es la h ente para incluir en un solo paquete dos o más c rados que requieren diferentes materiales, fl so o nodos de tecnología para optimizar el ren "nivel de sistema" soportado por los be nalizados de cada chip. Esto permite una funci vel superior en un solo paquete.
Una ventaja adicional todavía es la capaci ir la funcionalidad en la matriz de puente, la ser habilitada por la unión con cable solamente.
Muchas de las mismas ventajas aplican cu za la unión de chip basculante para empaquetar rcuito integrado. Al implementar las TSV en las ip basculante, se puede permitir interconexi
manera, a operaciones de escritura. Además, el a presente solicitud no pretende quedar limitad idades particulares del proceso, máquina, fabr sición de materia, medios, métodos y pasos desc specificación. Por ejemplo, aunque TSV es un en la técnica que hace referencia a matrices de ió, las vías pueden ser formadas en otros mater rticular otras matrices de semiconductor tal co GaN, u otros materiales convenientes. El términ aplicar con aplicación a cualquiera de iales. Tal como un experto en la. técnica lo a mente a partir de la descripción de la ción, procesos, máquinas, manufactura, composic ia, medios, métodos o, pasos, que existen en el e se desarrollarán más adelante, los cuales n i lm n
Claims (1)
- NOVEDAD DE LA INVENCION Habiendo descrito el presente inven dera como una novedad y,' por lo tanto, se reci idad lo contenido en las siguientes: REIVINDICACIONES 1.- Un sistema de interconexión de pu ito integrado, que comprende: una primera matriz que tiene un primer la do lado; una segunda matriz, que tiene un primer la do lado, proporcionados en una configuración lad a primera matriz; y una matriz de puente, que tiene un primer l do lado, colocados al menos parcialmente en los de la primera matriz y la segunda matriz, la m e interconecta de forma eléctrica la primera mat tir la interconexión. 3. - El sistema de conformidad con la reivin aracterizado porque la matriz de puente además c iteria activa en el primer lado. 4. - El sistema de conformidad con la reivin racterizado porque una o más almohadillas de con egundo lado de la matriz de puente contactan u adillas de contacto correspondientes en los de la primera y segunda matrices. 5. - El sistema de conformidad con la reivin racterizado porque al menos una de la primera y ces comprende: una matriz de chip basculante que tiene cir ada en el segundo lado; y TSV de chip basculante desde el primer la z de chip basculante al segundo lado de la m triz. 7. - El sistema de conformidad con la reivin e además comprende: una o más almohadillas de contacto en la p da matriz. 8. - El sistema de conformidad con la reivin racterizado porque la matriz de puente además co una o más almohadillas dé contacto en el de la matriz de puente correspondiente a las z de puente y opuestas y correspondientes a un adillas de contacto en los primeros y/o ros lados de la matriz. 9. - El sistema de conformidad con la reivin e además comprende: al menos una matriz adicional apilada en l ente, al menos una matriz adicional además c un paquete, que contiene matrices de semicond un substrato colocado dentro del paque ir matrices de semiconductor; una primera matriz que tiene un primer la do lado, en donde la primera matriz está coloca bstrato con el segundo lado mirando hacia el subs una segunda matriz que tiene un primer la do lado proporcionados en una configuración l con la primera matriz, en donde la segunda mat ada sobre el substrato con el segundo lado miran bstrato; y una matriz de puente, que tiene un primer l do lado, en donde la matriz de puente está col parcialmente sobre los primeros lados de la z y la segunda matriz, la matriz de puente ínte imera matriz y la segunda matriz. 13. - El sistema de empaquetamiento de con a reivindicación 12, caracterizado porque la m e además comprende circuiteria activa en el prime 14. - El sistema de empaquetamiento de con la reivindicación 12, caracterizado porque un adillas de contacto en el segundo lado de la m e contactan una o más almohadillas de spondientes en los primeros lados de la pr da matrices. 15. - El sistema de empaquetamiento, de con a reivindicación 12, caracterizado porque al m primera y segunda matrices comprende: una matriz de chip basculante que tiene cir ada en el segundo lado, en donde el chip bascula ado al substrato mediante unión con bolita, u de soldadura o pasta conductora; primera y segunda matriz comprende circuiteria primer lado de la matriz. 17. - El sistema de empaquetamiento de con a reivindicación 12, que además comprende: la primera y la segunda matriz tienen, ca más almohadillas de contacto. 18. - El sistema de empaquetamiento de con a reivindicación 17, caracterizado porque la m e además comprende: una o más almohadillas de contacto en el de la matriz de puente correspondiente a las z de puente y opuestas y correspondientes a un adillas de contacto en el primer y/o segundo de la matriz. 19. - El sistema de empaquetamiento de con a reivindicación 18, que además comprende:
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US12/164,331 US7969009B2 (en) | 2008-06-30 | 2008-06-30 | Through silicon via bridge interconnect |
PCT/US2009/048372 WO2010002645A1 (en) | 2008-06-30 | 2009-06-24 | Through silicon via bridge interconnect |
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MX2010014181A true MX2010014181A (es) | 2011-02-22 |
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MX2010014181A MX2010014181A (es) | 2008-06-30 | 2009-06-24 | Interconexion de puente de vias a traves de silicio. |
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US (2) | US7969009B2 (es) |
EP (1) | EP2311088B1 (es) |
JP (2) | JP5265768B2 (es) |
KR (1) | KR101209146B1 (es) |
CN (1) | CN102077344B (es) |
BR (1) | BRPI0914112B1 (es) |
CA (1) | CA2727260C (es) |
ES (1) | ES2812556T3 (es) |
HU (1) | HUE051601T2 (es) |
MX (1) | MX2010014181A (es) |
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-
2008
- 2008-06-30 US US12/164,331 patent/US7969009B2/en active Active
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- 2009-06-24 MX MX2010014181A patent/MX2010014181A/es active IP Right Grant
- 2009-06-24 CN CN2009801244053A patent/CN102077344B/zh active Active
- 2009-06-24 JP JP2011516553A patent/JP5265768B2/ja active Active
- 2009-06-24 KR KR1020117002307A patent/KR101209146B1/ko active IP Right Grant
- 2009-06-24 ES ES09774097T patent/ES2812556T3/es active Active
- 2009-06-24 RU RU2011103138/28A patent/RU2461092C1/ru active
- 2009-06-24 HU HUE09774097A patent/HUE051601T2/hu unknown
- 2009-06-24 BR BRPI0914112-0A patent/BRPI0914112B1/pt active IP Right Grant
- 2009-06-24 WO PCT/US2009/048372 patent/WO2010002645A1/en active Application Filing
- 2009-06-24 CA CA2727260A patent/CA2727260C/en active Active
- 2009-06-24 EP EP09774097.1A patent/EP2311088B1/en active Active
- 2009-06-30 TW TW098122074A patent/TWI483369B/zh active
-
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Also Published As
Publication number | Publication date |
---|---|
RU2461092C1 (ru) | 2012-09-10 |
CA2727260C (en) | 2017-08-08 |
US20090321939A1 (en) | 2009-12-31 |
ES2812556T3 (es) | 2021-03-17 |
WO2010002645A1 (en) | 2010-01-07 |
JP2011527113A (ja) | 2011-10-20 |
KR101209146B1 (ko) | 2012-12-06 |
CA2727260A1 (en) | 2010-01-07 |
EP2311088B1 (en) | 2020-05-20 |
TWI483369B (zh) | 2015-05-01 |
EP2311088A1 (en) | 2011-04-20 |
BRPI0914112B1 (pt) | 2020-08-11 |
TW201010038A (en) | 2010-03-01 |
HUE051601T2 (hu) | 2021-03-01 |
US20110215472A1 (en) | 2011-09-08 |
KR20110025699A (ko) | 2011-03-10 |
JP5763121B2 (ja) | 2015-08-12 |
JP5265768B2 (ja) | 2013-08-14 |
CN102077344A (zh) | 2011-05-25 |
JP2013175772A (ja) | 2013-09-05 |
RU2011103138A (ru) | 2012-08-10 |
US7969009B2 (en) | 2011-06-28 |
BRPI0914112A2 (pt) | 2015-10-20 |
CN102077344B (zh) | 2013-04-17 |
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