MX2010014181A - Interconexion de puente de vias a traves de silicio. - Google Patents

Interconexion de puente de vias a traves de silicio.

Info

Publication number
MX2010014181A
MX2010014181A MX2010014181A MX2010014181A MX2010014181A MX 2010014181 A MX2010014181 A MX 2010014181A MX 2010014181 A MX2010014181 A MX 2010014181A MX 2010014181 A MX2010014181 A MX 2010014181A MX 2010014181 A MX2010014181 A MX 2010014181A
Authority
MX
Mexico
Prior art keywords
matrix
bridge
contact
chip
accordance
Prior art date
Application number
MX2010014181A
Other languages
English (en)
Inventor
Arvind Chandrasekaran
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of MX2010014181A publication Critical patent/MX2010014181A/es

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73207—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1027—IV
    • H01L2924/10272—Silicon Carbide [SiC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/1033—Gallium nitride [GaN]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/1579—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

Un sistema de interconexión de puente de circuito integrado incluye una primera matriz y una segunda matriz proporcionadas en una configuración lado a lado y eléctricamente interconectadas entre sí a través de una matriz de puente; la matriz de puente incluye vías a través del silicio (TSV) para conectar líneas de interconexión conductoras en la matriz de puente a la primera matriz y la segunda matriz; circuiteria activa, diferente a las líneas de interconexión, puede ser proporcionada en la matriz de puente; al menos una o más matrices adicionales pueden estar apiladas en la matriz de puente e interconectadas a la matriz de puente.

Description

INTERCONEXION DE PUENTE DE VIAS A TRAVES DE SILI CAMPO DE LA INVENCION Esta descripción se refiere a empaquetami itos integrados (IC), y de manera más espec conexiones de puente entre circuitos integrados dentro de un paquete de substrato.
ANTECEDENTES DE LA INVENCION En el empaquetamiento IC existe la neces rcionar matrices de semiconductor en una confi a-lado dentro de un paquete y su interconex te puede ser, por ejemplo, un paquete de bast ctores .
En una configuración, las matrices de semic mpaquetadas con el lado activo de cada matriz ado por el tamaño de las interconexiones. Ade tancia de los conductores en la unión con cable riz puede limitar el rendimiento del dis uetado. Además, el cable de oro es una ncional para unión con cable, increi ficativamente el costo neto del paquete.
En otra configuración, el empaquetamie dura de bolita de chip basculante, la región ac sitivo de la matriz está sobre la superficie que rato de montaje de paquete, por ejemplo, hacia a configuración, la densidad de la interconexió ces adyacentes también queda limitada p rimientos de tamaño de la almohadilla de contact La Patente de los Estados Unidos No. 5 ga la interconexión de dos matrices de semicond scribe un método para formar los conductores de sición en el puente, de silicio. Además, el m ble de los conductores de has puede ser difici e ocupa espacio entre las dos matrices. Además, el oro es un metal de interconexión preferido, to en el costo del material del paquete ensambla Por lo tanto, existe la necesidad de un si conexión de empaquetamiento entre matri onductor adyacentes que simplifique el pro ble, reduzca el costo de los materiales de inter mita la interconexión entre chips con un espac ino de lo que convencionalmente se permite con cable e interconexiones de conductores . alentes .
SUMARIO DE LA INVENCION segundo lado y una segunda matriz que tiene u y un segundo lado. Estas matrices son proporció configuración lado-por-ladó . Una matriz de puen ada en los primeros lados de la primera matr da matriz. La matriz de puente interconecta la z y la segunda matriz.
Un sistema de empaquetamiento de circuito i ye un paquete para contener matrices de semicon ubstrato colocado dentro del paquete para ces de semiconductor. Una primera matriz y una z, ambas con un primer lado y un segundo lado adas sobre el substrato en una configuración l Los segundos lados de la primera y segunda hacia el substrato. Una matriz de puente está os primeros lados de la primera matriz y la ca debieran apreciar que la concepción y la m ifica descrita se pueden utilizar fácilmente c para modificar o diseñar otras estructuras que los mismos propósitos de la presente invención. tos en la técnica también debieran observar qu rucciones equivalentes no se aparten del esp ce de la invención tal como se establece ndicaciones anexas. Las características novedosa son la característica de la invención, tanto en efiere a su organización como al método de op con objetivos y ventajas adicionales, se en a partir de la siguiente descripción cu deren en conexión con las figuras acompañan nte, se debería entender de forma expresa que s figuras se proporciona con el propósito de ilu mbrica ejemplar en el cual de manera convenÍ n emplear las modalidades de la invención.
La figura 2 ilustra una vista plana conexión de puente TSV de acuerdo con una moda vención .
La figura 3 es una vista en sección transv s ejemplar de una modalidad de la intercone e entre dos matrices de chip basculante .
La figura 4 es una vista en sección transv s ejemplar de una modalidad de la intercone e entre dos matrices de unión con cable.
La figura 5 es una vista en sección transv s ejemplar de una modalidad de la intercone e entre una matriz de chip basculante y una ma con cable. zando una matriz de puente de intercone onductor (típicamente silicio) para hacer cont matrices lado-a-lado. La matriz de pue conexión tiene vías a través del silicio para almohadillas de contacto en cada de las matric ficie opuesta de la matriz de puente de interc líneas de interconexión en la matriz de pu conexión se forman para completar las conexion ías a través del silicio.
La figura 1 muestra un sistema de comú mbrica ejemplar 100 en el cual se puede emp a conveniente una modalidad de la invenció sitos de ilustración, la figura 1 muestra tres as 120, 130 y 150 y dos estaciones base ocerá que sistemas de comunicación inalámbrica n tener muchas más unidades remotas estacion En la figura 1, la unidad remota 120 se un teléfono móvil, la unidad remota 130 se mues omputadora portátil, y la unidad remota 150 se una unidad remota de ubicación fija en un sis local inalámbrico. Por ejemplo, las unidades n ser teléfonos celulares, unidades de sist icación personal manuales (PCS) , unidades d tiles tales como asistentes de datos person des de datos de ubicación fija, tales como e ra de medidores. Aunque la figura 1 ilustra as de acuerdo con las enseñanzas de la invenc ción no queda limitada a estas unidades ej radas . La invención se puede emplear de niente en cualquier dispositivo que incluya un lti-chip que tenga chips en una configuración l matrices 220 y 230 se muestran colocadas guración lado-por-lado . Una superficie de las 230 se puede conectar al substrato 210, y event conductores del paquete.
Una matriz de interconexión de puente 240 q imer y un segundo lados al menos traslapa parcia omunica eléctricamente- con las matrices 220 y a través del silicio (TSV) 270 rellenadas con ctor, conectan el primer lado (que se muestra fuera de la página) de la matriz de intercon e 240 a la circuiteria activa en las matrices 22 lineas de interconexión 272 en el primer lad z de interconexión de puente 240 entonces compl iones entre las matrices 220 y 230. Para di aciones funcionales, donde las funciones especi os {es decir, transistores, lógica, memoria, e no se muestra en la figura 2, el primer lad z de interconexión de puente 240 puede iteria activa adicional, no relacionada onalidad de interconexión.
Las lineas de interconexión 272 y/o circui triz de interconexión de puente 240 se pueden f de pastilla, incluyendo la formación de los nados con metal de las TSV 270 utilizando proc ización y semiconductor convencionales, despué la pastilla entonces puede ser separada en mat conexión de puente' individuales 240.
La figura 3 es una vista en sección transv I s ejemplar de una modalidad de una configuració interconexión de puente entre dos matrices ' ran mirando hacia arriba en la figura 2) iteria activa en los segundos lados de las matr .
Las almohadillas de. contacto 371 en el segú matriz de interconexión de puente 240 y los de las matrices 320 y 330 están alineadas, y pu s utilizando métodos tales como, por ejemplo, dura de bolita y la pasta conductora. Las almo ontacto 371 formadas en las matrices 320, 33 itan el contacto conductivo entre spondientes 270 y 373. En consecuencia, la cir a en las matrices 320 y 330 está c ricamente al primer lado de la matriz de inter ente 240, en donde la interconexión entre la cir a es completada utilizando las lineas de inter Las almohadillas de contacto 371 se , la figura 3. Es decir, la matriz de intercon e 240 de la figura 4 puede tener las teristicas y arreglo de las TSV 270, almohadi cto 371, lineas de interconexión 272 y opcion ntos de impedancia y/o dispositivos activos, ados sobre el primer lado de la matriz de inter ente 240 de la figura 3.
Las matrices de unión con cable de semic 430 tienen un primer lado y un segundo lado, d dos lados de las matrices 420 y 430 miran y está bstrato 210. La unión con cable conecta las almo ntacto sobre los primeros lados de las matrice las almohadillas de contacto sobre el substrato que en la configuración de chip basculante 30 a 3, las tres matrices 420, 430 y 240 adillas e cont c 371 en ic i n orres o estra en la figura 4, se puede incluir opcional no ser requerida.
La figura 5 es una vista en sección transv s ejemplar de una modalidad de una configuració interconexión de puente entre la matriz lante 320 y la matriz de unión con cable nsación apropiada se puede obtener para dif ivas en grosores de matriz, altura de unión de para colocar los primeros lados de ambas matric a la misma altura. Una consideración de in iadas entre matrices de chip basculante, puente able son las mismas que se describieron con refe iguras 3 y 4. Por ejemplo, la matriz de chip ba iene circuiteria activa colocada en el segundo , mirando al substrato 210) y puede reque lidad de TSV 373 conectadas a la lm h i iar de una modalidad de una configuración 600 en enos una o más matrices adicionales 640 (dond sitos ilustrativos, solamente se muestra una mat apiladas en la matriz de interconexión de¦ pue atriz adicional 640 puede incluir una funció logía de material u otra base para formar la ma adamente de otras matrices 320, 430 que c sitivos activos. La matriz de puente de inter uede incluir almohadillas de contacto 371 en e para conectarse en interfaz con las almohadi cto correspondiente 371 que miran en dirección o están ubicadas 'en la matriz 640. La matriz 64 ir las TSV 674 conectadas a las almohadillas de en ambos lados de la matriz 640 para prop conexión entre la matriz de puente de intercone da) , la disposición de la circuiteria puede uiera del primer o el segundo lado de la matriz Numerosas ventajas se pueden derivar idades descritas. Al utilizar una matriz de pue s de interconexión se pueden fabricar en can a de pastilla utilizando procesos de semicondu r de la metalización puede ser en el orden as mieras o menos, con anchos de linea convenien de tecnología de avance, tal como 45 nm y m puede ser otro que no sea oro. En comparación de cable de oro entre los substratos, se var ahorros sustanciales de material.
De manera adicional, la unión con cable separación mínima entre almohadillas de entes sobre un substrato, por motivos debido, Además, en la situación donde una configur chip lado-a-lado ha sido diseñada previamen con cable, una interconexión de puente pu mentada de manera benéfica para reemplazar la u , mientras se hace uso de las almohadillas de entes. Un reemplazo de la interconexión de pue ión con cable reduce el número de pasos del ens-ión a los múltiples pasos de' unión con cable s una colocación de matriz sencilla.
Incluso todavía, la unión con cable por lo ucra un bucle en el arco del cable ent adillas de unión además de una distancia r a entre las almohadillas de unión. Como result tancia del cable puede degradar el rend ialmente en dispositivos de alta velocidad d es de cable.
Una ventaja adicional todavía es la h ente para incluir en un solo paquete dos o más c rados que requieren diferentes materiales, fl so o nodos de tecnología para optimizar el ren "nivel de sistema" soportado por los be nalizados de cada chip. Esto permite una funci vel superior en un solo paquete.
Una ventaja adicional todavía es la capaci ir la funcionalidad en la matriz de puente, la ser habilitada por la unión con cable solamente.
Muchas de las mismas ventajas aplican cu za la unión de chip basculante para empaquetar rcuito integrado. Al implementar las TSV en las ip basculante, se puede permitir interconexi manera, a operaciones de escritura. Además, el a presente solicitud no pretende quedar limitad idades particulares del proceso, máquina, fabr sición de materia, medios, métodos y pasos desc specificación. Por ejemplo, aunque TSV es un en la técnica que hace referencia a matrices de ió, las vías pueden ser formadas en otros mater rticular otras matrices de semiconductor tal co GaN, u otros materiales convenientes. El términ aplicar con aplicación a cualquiera de iales. Tal como un experto en la. técnica lo a mente a partir de la descripción de la ción, procesos, máquinas, manufactura, composic ia, medios, métodos o, pasos, que existen en el e se desarrollarán más adelante, los cuales n i lm n

Claims (1)

  1. NOVEDAD DE LA INVENCION Habiendo descrito el presente inven dera como una novedad y,' por lo tanto, se reci idad lo contenido en las siguientes: REIVINDICACIONES 1.- Un sistema de interconexión de pu ito integrado, que comprende: una primera matriz que tiene un primer la do lado; una segunda matriz, que tiene un primer la do lado, proporcionados en una configuración lad a primera matriz; y una matriz de puente, que tiene un primer l do lado, colocados al menos parcialmente en los de la primera matriz y la segunda matriz, la m e interconecta de forma eléctrica la primera mat tir la interconexión. 3. - El sistema de conformidad con la reivin aracterizado porque la matriz de puente además c iteria activa en el primer lado. 4. - El sistema de conformidad con la reivin racterizado porque una o más almohadillas de con egundo lado de la matriz de puente contactan u adillas de contacto correspondientes en los de la primera y segunda matrices. 5. - El sistema de conformidad con la reivin racterizado porque al menos una de la primera y ces comprende: una matriz de chip basculante que tiene cir ada en el segundo lado; y TSV de chip basculante desde el primer la z de chip basculante al segundo lado de la m triz. 7. - El sistema de conformidad con la reivin e además comprende: una o más almohadillas de contacto en la p da matriz. 8. - El sistema de conformidad con la reivin racterizado porque la matriz de puente además co una o más almohadillas dé contacto en el de la matriz de puente correspondiente a las z de puente y opuestas y correspondientes a un adillas de contacto en los primeros y/o ros lados de la matriz. 9. - El sistema de conformidad con la reivin e además comprende: al menos una matriz adicional apilada en l ente, al menos una matriz adicional además c un paquete, que contiene matrices de semicond un substrato colocado dentro del paque ir matrices de semiconductor; una primera matriz que tiene un primer la do lado, en donde la primera matriz está coloca bstrato con el segundo lado mirando hacia el subs una segunda matriz que tiene un primer la do lado proporcionados en una configuración l con la primera matriz, en donde la segunda mat ada sobre el substrato con el segundo lado miran bstrato; y una matriz de puente, que tiene un primer l do lado, en donde la matriz de puente está col parcialmente sobre los primeros lados de la z y la segunda matriz, la matriz de puente ínte imera matriz y la segunda matriz. 13. - El sistema de empaquetamiento de con a reivindicación 12, caracterizado porque la m e además comprende circuiteria activa en el prime 14. - El sistema de empaquetamiento de con la reivindicación 12, caracterizado porque un adillas de contacto en el segundo lado de la m e contactan una o más almohadillas de spondientes en los primeros lados de la pr da matrices. 15. - El sistema de empaquetamiento, de con a reivindicación 12, caracterizado porque al m primera y segunda matrices comprende: una matriz de chip basculante que tiene cir ada en el segundo lado, en donde el chip bascula ado al substrato mediante unión con bolita, u de soldadura o pasta conductora; primera y segunda matriz comprende circuiteria primer lado de la matriz. 17. - El sistema de empaquetamiento de con a reivindicación 12, que además comprende: la primera y la segunda matriz tienen, ca más almohadillas de contacto. 18. - El sistema de empaquetamiento de con a reivindicación 17, caracterizado porque la m e además comprende: una o más almohadillas de contacto en el de la matriz de puente correspondiente a las z de puente y opuestas y correspondientes a un adillas de contacto en el primer y/o segundo de la matriz. 19. - El sistema de empaquetamiento de con a reivindicación 18, que además comprende:
MX2010014181A 2008-06-30 2009-06-24 Interconexion de puente de vias a traves de silicio. MX2010014181A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/164,331 US7969009B2 (en) 2008-06-30 2008-06-30 Through silicon via bridge interconnect
PCT/US2009/048372 WO2010002645A1 (en) 2008-06-30 2009-06-24 Through silicon via bridge interconnect

Publications (1)

Publication Number Publication Date
MX2010014181A true MX2010014181A (es) 2011-02-22

Family

ID=41228442

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2010014181A MX2010014181A (es) 2008-06-30 2009-06-24 Interconexion de puente de vias a traves de silicio.

Country Status (13)

Country Link
US (2) US7969009B2 (es)
EP (1) EP2311088B1 (es)
JP (2) JP5265768B2 (es)
KR (1) KR101209146B1 (es)
CN (1) CN102077344B (es)
BR (1) BRPI0914112B1 (es)
CA (1) CA2727260C (es)
ES (1) ES2812556T3 (es)
HU (1) HUE051601T2 (es)
MX (1) MX2010014181A (es)
RU (1) RU2461092C1 (es)
TW (1) TWI483369B (es)
WO (1) WO2010002645A1 (es)

Families Citing this family (150)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
US8873585B2 (en) 2006-12-19 2014-10-28 Corning Optical Communications Wireless Ltd Distributed antenna system for MIMO technologies
US9276656B2 (en) 2007-02-19 2016-03-01 Corning Optical Communications Wireless Ltd Method and system for improving uplink performance
US20100054746A1 (en) 2007-07-24 2010-03-04 Eric Raymond Logan Multi-port accumulator for radio-over-fiber (RoF) wireless picocellular systems
US8175459B2 (en) 2007-10-12 2012-05-08 Corning Cable Systems Llc Hybrid wireless/wired RoF transponder and hybrid RoF communication system using same
US8594133B2 (en) 2007-10-22 2013-11-26 Corning Mobileaccess Ltd. Communication system using low bandwidth wires
US8175649B2 (en) 2008-06-20 2012-05-08 Corning Mobileaccess Ltd Method and system for real time control of an active antenna over a distributed antenna system
US8644844B2 (en) 2007-12-20 2014-02-04 Corning Mobileaccess Ltd. Extending outdoor location based services and applications into enclosed areas
US7969009B2 (en) * 2008-06-30 2011-06-28 Qualcomm Incorporated Through silicon via bridge interconnect
JP2012517190A (ja) 2009-02-03 2012-07-26 コーニング ケーブル システムズ リミテッド ライアビリティ カンパニー 光ファイバベースの分散型アンテナシステム、構成要素、及びそのモニタリング及び構成のための関連の方法
AU2010210771B2 (en) 2009-02-03 2015-09-17 Corning Cable Systems Llc Optical fiber-based distributed antenna systems, components, and related methods for calibration thereof
US9673904B2 (en) 2009-02-03 2017-06-06 Corning Optical Communications LLC Optical fiber-based distributed antenna systems, components, and related methods for calibration thereof
CN102232191B (zh) 2009-02-08 2015-07-08 康宁移动接入有限公司 采用携带以太网信号的电缆的通信***
US9590733B2 (en) 2009-07-24 2017-03-07 Corning Optical Communications LLC Location tracking using fiber optic array cables and related systems and methods
US8548330B2 (en) 2009-07-31 2013-10-01 Corning Cable Systems Llc Sectorization in distributed antenna systems, and related components and methods
JP5635247B2 (ja) * 2009-08-20 2014-12-03 富士通株式会社 マルチチップモジュール
US8280259B2 (en) 2009-11-13 2012-10-02 Corning Cable Systems Llc Radio-over-fiber (RoF) system for protocol-independent wired and/or wireless communication
CN102130098B (zh) * 2010-01-20 2015-11-25 飞思卡尔半导体公司 双管芯半导体封装
US8275265B2 (en) 2010-02-15 2012-09-25 Corning Cable Systems Llc Dynamic cell bonding (DCB) for radio-over-fiber (RoF)-based networks and communication systems and related methods
AU2011232897B2 (en) 2010-03-31 2015-11-05 Corning Optical Communications LLC Localization services in optical fiber-based distributed communications components and systems, and related methods
US8525342B2 (en) * 2010-04-12 2013-09-03 Qualcomm Incorporated Dual-side interconnected CMOS for stacked integrated circuits
US20110268446A1 (en) 2010-05-02 2011-11-03 Cune William P Providing digital data services in optical fiber-based distributed radio frequency (rf) communications systems, and related components and methods
US9525488B2 (en) 2010-05-02 2016-12-20 Corning Optical Communications LLC Digital data services and/or power distribution in optical fiber-based distributed communications systems providing digital data and radio frequency (RF) communications services, and related components and methods
WO2011140082A1 (en) * 2010-05-03 2011-11-10 Georgia Tech Research Corporation Cmut devices and fabrication methods
TWI513301B (zh) * 2010-06-02 2015-12-11 Sony Corp 半導體裝置，固態成像裝置及相機系統
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US8570914B2 (en) 2010-08-09 2013-10-29 Corning Cable Systems Llc Apparatuses, systems, and methods for determining location of a mobile device(s) in a distributed antenna system(s)
EP2606707A1 (en) 2010-08-16 2013-06-26 Corning Cable Systems LLC Remote antenna clusters and related systems, components, and methods supporting digital data signal propagation between remote antenna units
US8786066B2 (en) 2010-09-24 2014-07-22 Intel Corporation Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming same
US9160449B2 (en) 2010-10-13 2015-10-13 Ccs Technology, Inc. Local power management for remote antenna units in distributed antenna systems
US9252874B2 (en) 2010-10-13 2016-02-02 Ccs Technology, Inc Power management for remote antenna units in distributed antenna systems
WO2012071367A1 (en) 2010-11-24 2012-05-31 Corning Cable Systems Llc Power distribution module(s) capable of hot connection and/or disconnection for distributed antenna systems, and related power units, components, and methods
US11296504B2 (en) 2010-11-24 2022-04-05 Corning Optical Communications LLC Power distribution module(s) capable of hot connection and/or disconnection for wireless communication systems, and related power units, components, and methods
US9190371B2 (en) 2010-12-21 2015-11-17 Moon J. Kim Self-organizing network with chip package having multiple interconnection configurations
WO2012115843A1 (en) 2011-02-21 2012-08-30 Corning Cable Systems Llc Providing digital data services as electrical signals and radio-frequency (rf) communications over optical fiber in distributed communications systems, and related components and methods
US8823133B2 (en) 2011-03-29 2014-09-02 Xilinx, Inc. Interposer having an inductor
EP2702780A4 (en) 2011-04-29 2014-11-12 Corning Cable Sys Llc SYSTEMS, METHODS AND DEVICES FOR INCREASING HIGH-FREQUENCY (HF) PERFORMANCE IN DISTRIBUTED ANTENNA SYSTEMS
CN103548290B (zh) 2011-04-29 2016-08-31 康宁光缆***有限责任公司 判定分布式天线***中的通信传播延迟及相关组件、***与方法
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US9406738B2 (en) 2011-07-20 2016-08-02 Xilinx, Inc. Inductive structure formed using through silicon vias
US8404520B1 (en) 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
US9330823B1 (en) 2011-12-19 2016-05-03 Xilinx, Inc. Integrated circuit structure with inductor in silicon interposer
US9059179B2 (en) * 2011-12-28 2015-06-16 Broadcom Corporation Semiconductor package with a bridge interposer
US9337138B1 (en) 2012-03-09 2016-05-10 Xilinx, Inc. Capacitors within an interposer coupled to supply and ground planes of a substrate
EP2829152A2 (en) 2012-03-23 2015-01-28 Corning Optical Communications Wireless Ltd. Radio-frequency integrated circuit (rfic) chip(s) for providing distributed antenna system functionalities, and related components, systems, and methods
US9613917B2 (en) 2012-03-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) device with integrated passive device in a via
EP2832012A1 (en) 2012-03-30 2015-02-04 Corning Optical Communications LLC Reducing location-dependent interference in distributed antenna systems operating in multiple-input, multiple-output (mimo) configuration, and related components, systems, and methods
US9781553B2 (en) 2012-04-24 2017-10-03 Corning Optical Communications LLC Location based services in a distributed communication system, and related components and methods
EP2842245A1 (en) 2012-04-25 2015-03-04 Corning Optical Communications LLC Distributed antenna system architectures
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
WO2013181247A1 (en) 2012-05-29 2013-12-05 Corning Cable Systems Llc Ultrasound-based localization of client devices with inertial navigation supplement in distributed communication systems and related devices and methods
US9154222B2 (en) 2012-07-31 2015-10-06 Corning Optical Communications LLC Cooling system control in distributed antenna systems
US9391008B2 (en) * 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
EP2883416A1 (en) 2012-08-07 2015-06-17 Corning Optical Communications Wireless Ltd. Distribution of time-division multiplexed (tdm) management services in a distributed antenna system, and related components, systems, and methods
US9165887B2 (en) 2012-09-10 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with discrete blocks
US9391041B2 (en) 2012-10-19 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out wafer level package structure
US9455784B2 (en) 2012-10-31 2016-09-27 Corning Optical Communications Wireless Ltd Deployable wireless infrastructures and methods of deploying wireless infrastructures
US10257056B2 (en) 2012-11-28 2019-04-09 Corning Optical Communications LLC Power management for distributed communication systems, and related components, systems, and methods
EP2926466A1 (en) 2012-11-29 2015-10-07 Corning Optical Communications LLC HYBRID INTRA-CELL / INTER-CELL REMOTE UNIT ANTENNA BONDING IN MULTIPLE-INPUT, MULTIPLE-OUTPUT (MIMO) DISTRIBUTED ANTENNA SYSTEMS (DASs)
US9647758B2 (en) 2012-11-30 2017-05-09 Corning Optical Communications Wireless Ltd Cabling connectivity monitoring and verification
US8866308B2 (en) * 2012-12-20 2014-10-21 Intel Corporation High density interconnect device and method
US9158864B2 (en) 2012-12-21 2015-10-13 Corning Optical Communications Wireless Ltd Systems, methods, and devices for documenting a location of installed equipment
KR102021077B1 (ko) 2013-01-24 2019-09-11 삼성전자주식회사 적층된 다이 패키지, 이를 포함하는 시스템 및 이의 제조 방법
US9497706B2 (en) 2013-02-20 2016-11-15 Corning Optical Communications Wireless Ltd Power management in distributed antenna systems (DASs), and related components, systems, and methods
US8901748B2 (en) * 2013-03-14 2014-12-02 Intel Corporation Direct external interconnect for embedded interconnect bridge package
JP2014222728A (ja) * 2013-05-14 2014-11-27 凸版印刷株式会社 半導体パッケージ
EP3008828B1 (en) 2013-06-12 2017-08-09 Corning Optical Communications Wireless Ltd. Time-division duplexing (tdd) in distributed communications systems, including distributed antenna systems (dass)
WO2014199384A1 (en) 2013-06-12 2014-12-18 Corning Optical Communications Wireless, Ltd. Voltage controlled optical directional coupler
US9041205B2 (en) 2013-06-28 2015-05-26 Intel Corporation Reliable microstrip routing for electronics components
US9247543B2 (en) 2013-07-23 2016-01-26 Corning Optical Communications Wireless Ltd Monitoring non-supported wireless spectrum within coverage areas of distributed antenna systems (DASs)
US9661781B2 (en) 2013-07-31 2017-05-23 Corning Optical Communications Wireless Ltd Remote units for distributed communication systems and related installation methods and apparatuses
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
WO2015029028A1 (en) 2013-08-28 2015-03-05 Corning Optical Communications Wireless Ltd. Power management for distributed communication systems, and related components, systems, and methods
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
KR20160036666A (ko) 2013-09-27 2016-04-04 인텔 코포레이션 수동 부품용 중첩체 기판을 구비한 다이 패키지
US9385810B2 (en) 2013-09-30 2016-07-05 Corning Optical Communications Wireless Ltd Connection mapping in distributed communication systems
JP2016533646A (ja) 2013-10-16 2016-10-27 インテル・コーポレーション 集積回路パッケージ基板
EP3064032A1 (en) 2013-10-28 2016-09-07 Corning Optical Communications Wireless Ltd Unified optical fiber-based distributed antenna systems (dass) for supporting small cell communications deployment from multiple small cell service providers, and related devices and methods
US9679839B2 (en) 2013-10-30 2017-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US9373527B2 (en) 2013-10-30 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
WO2015079435A1 (en) 2013-11-26 2015-06-04 Corning Optical Communications Wireless Ltd. Selective activation of communications services on power-up of a remote unit(s) in a distributed antenna system (das) based on power consumption
US9275955B2 (en) 2013-12-18 2016-03-01 Intel Corporation Integrated circuit package with embedded bridge
US9178635B2 (en) 2014-01-03 2015-11-03 Corning Optical Communications Wireless Ltd Separation of communication signal sub-bands in distributed antenna systems (DASs) to reduce interference
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
JP2014078760A (ja) * 2014-02-03 2014-05-01 Fujitsu Ltd マルチチップモジュール
US9583460B2 (en) * 2014-02-14 2017-02-28 Qualcomm Incorporated Integrated device comprising stacked dies on redistribution layers
US9775123B2 (en) 2014-03-28 2017-09-26 Corning Optical Communications Wireless Ltd. Individualized gain control of uplink paths in remote units in a distributed antenna system (DAS) based on individual remote unit contribution to combined uplink power
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9357551B2 (en) 2014-05-30 2016-05-31 Corning Optical Communications Wireless Ltd Systems and methods for simultaneous sampling of serial digital data streams from multiple analog-to-digital converters (ADCS), including in distributed antenna systems
US9509133B2 (en) 2014-06-27 2016-11-29 Corning Optical Communications Wireless Ltd Protection of distributed antenna systems
US10056352B2 (en) 2014-07-11 2018-08-21 Intel IP Corporation High density chip-to-chip connection
US9525472B2 (en) 2014-07-30 2016-12-20 Corning Incorporated Reducing location-dependent destructive interference in distributed antenna systems (DASS) operating in multiple-input, multiple-output (MIMO) configuration, and related components, systems, and methods
US9730228B2 (en) 2014-08-29 2017-08-08 Corning Optical Communications Wireless Ltd Individualized gain control of remote uplink band paths in a remote unit in a distributed antenna system (DAS), based on combined uplink power level in the remote unit
US9653861B2 (en) 2014-09-17 2017-05-16 Corning Optical Communications Wireless Ltd Interconnection of hardware components
CN107004661B (zh) 2014-09-19 2019-06-14 英特尔公司 具有嵌入式桥接互连件的半导体封装
US9602210B2 (en) 2014-09-24 2017-03-21 Corning Optical Communications Wireless Ltd Flexible head-end chassis supporting automatic identification and interconnection of radio interface modules and optical interface modules in an optical fiber-based distributed antenna system (DAS)
US9420542B2 (en) 2014-09-25 2016-08-16 Corning Optical Communications Wireless Ltd System-wide uplink band gain control in a distributed antenna system (DAS), based on per band gain control of remote uplink paths in remote units
US9184960B1 (en) 2014-09-25 2015-11-10 Corning Optical Communications Wireless Ltd Frequency shifting a communications signal(s) in a multi-frequency distributed antenna system (DAS) to avoid or reduce frequency interference
US10659163B2 (en) 2014-09-25 2020-05-19 Corning Optical Communications LLC Supporting analog remote antenna units (RAUs) in digital distributed antenna systems (DASs) using analog RAU digital adaptors
EP3198644A4 (en) 2014-09-26 2018-05-23 Intel Corporation Integrated circuit package having wire-bonded multi-die stack
WO2016071902A1 (en) 2014-11-03 2016-05-12 Corning Optical Communications Wireless Ltd. Multi-band monopole planar antennas configured to facilitate improved radio frequency (rf) isolation in multiple-input multiple-output (mimo) antenna arrangement
WO2016075696A1 (en) 2014-11-13 2016-05-19 Corning Optical Communications Wireless Ltd. Analog distributed antenna systems (dass) supporting distribution of digital communications signals interfaced from a digital signal source and analog radio frequency (rf) communications signals
US11069734B2 (en) 2014-12-11 2021-07-20 Invensas Corporation Image sensor device
US9729267B2 (en) 2014-12-11 2017-08-08 Corning Optical Communications Wireless Ltd Multiplexing two separate optical links with the same wavelength using asymmetric combining and splitting
WO2016098111A1 (en) 2014-12-18 2016-06-23 Corning Optical Communications Wireless Ltd. Digital- analog interface modules (da!ms) for flexibly.distributing digital and/or analog communications signals in wide-area analog distributed antenna systems (dass)
WO2016098109A1 (en) 2014-12-18 2016-06-23 Corning Optical Communications Wireless Ltd. Digital interface modules (dims) for flexibly distributing digital and/or analog communications signals in wide-area analog distributed antenna systems (dass)
US20160249365A1 (en) 2015-02-19 2016-08-25 Corning Optical Communications Wireless Ltd. Offsetting unwanted downlink interference signals in an uplink path in a distributed antenna system (das)
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9785175B2 (en) 2015-03-27 2017-10-10 Corning Optical Communications Wireless, Ltd. Combining power from electrically isolated power paths for powering remote units in a distributed antenna system(s) (DASs)
US9681313B2 (en) 2015-04-15 2017-06-13 Corning Optical Communications Wireless Ltd Optimizing remote antenna unit performance using an alternative data channel
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9948349B2 (en) 2015-07-17 2018-04-17 Corning Optical Communications Wireless Ltd IOT automation and data collection system
US9368450B1 (en) 2015-08-21 2016-06-14 Qualcomm Incorporated Integrated device package comprising bridge in litho-etchable layer
US10560214B2 (en) 2015-09-28 2020-02-11 Corning Optical Communications LLC Downlink and uplink communication path switching in a time-division duplex (TDD) distributed antenna system (DAS)
US9935076B1 (en) * 2015-09-30 2018-04-03 Apple Inc. Structure and method for fabricating a computing system with an integrated voltage regulator module
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
WO2017111790A1 (en) 2015-12-23 2017-06-29 Manusharow Mathew J Improving size and efficiency of dies
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US10002100B2 (en) 2016-02-02 2018-06-19 Xilinx, Inc. Active-by-active programmable device
US10042806B2 (en) 2016-02-02 2018-08-07 Xilinx, Inc. System-level interconnect ring for a programmable integrated circuit
CN109075787B (zh) * 2016-02-02 2022-04-29 赛灵思公司 有源接有源可编程器件
US9648580B1 (en) 2016-03-23 2017-05-09 Corning Optical Communications Wireless Ltd Identifying remote units in a wireless distribution system (WDS) based on assigned unique temporal delay patterns
US10236924B2 (en) 2016-03-31 2019-03-19 Corning Optical Communications Wireless Ltd Reducing out-of-channel noise in a wireless distribution system (WDS)
WO2018004692A1 (en) * 2016-07-01 2018-01-04 Pietambaram Srinivas V Molded embedded bridge for enhanced emib applications
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
US10651126B2 (en) 2017-12-08 2020-05-12 Applied Materials, Inc. Methods and apparatus for wafer-level die bridge
US11508663B2 (en) 2018-02-02 2022-11-22 Marvell Israel (M.I.S.L) Ltd. PCB module on package
US11735570B2 (en) * 2018-04-04 2023-08-22 Intel Corporation Fan out packaging pop mechanical attach method
US10438894B1 (en) 2018-05-30 2019-10-08 Globalfoundries Inc. Chip-to-chip and chip-to-substrate interconnections in multi-chip semiconductor devices
US11462419B2 (en) 2018-07-06 2022-10-04 Invensas Bonding Technologies, Inc. Microelectronic assemblies
US20200098692A1 (en) * 2018-09-26 2020-03-26 Intel Corporation Microelectronic assemblies having non-rectilinear arrangements
US11581292B2 (en) 2019-06-10 2023-02-14 Marvell Israel (M.I.S.L) Ltd. IC package with top-side memory module
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US10957650B2 (en) 2019-08-21 2021-03-23 International Business Machines Corporation Bridge support structure
TW202111907A (zh) 2019-09-05 2021-03-16 力成科技股份有限公司 以矽中介層作為互連橋的封裝晶片結構
US11430764B2 (en) * 2019-12-20 2022-08-30 Intel Corporation Overhang bridge interconnect
WO2021202075A1 (en) * 2020-04-03 2021-10-07 Cree, Inc. Rf amplifier package
WO2021202199A1 (en) 2020-04-03 2021-10-07 Cree, Inc. Group iii nitride-based radio frequency amplifiers having back side source, gate and/or drain terminals
CN115699326A (zh) 2020-04-03 2023-02-03 沃孚半导体公司 具有源极、栅极和/或漏极导电通孔的基于iii族氮化物的射频晶体管放大器
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11830817B2 (en) * 2020-08-12 2023-11-28 Advanced Micro Devices, Inc. Creating interconnects between dies using a cross-over die and through-die vias
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6013737U (ja) * 1983-07-08 1985-01-30 日本電気株式会社 半導体集積回路装置
US5399898A (en) * 1992-07-17 1995-03-21 Lsi Logic Corporation Multi-chip semiconductor arrangements using flip chip dies
US5321277A (en) * 1990-12-31 1994-06-14 Texas Instruments Incorporated Multi-chip module testing
US5225633A (en) 1991-10-04 1993-07-06 The United States Of America As Represented By The Secretary Of The Air Force Bridge chip interconnect system
US5198963A (en) * 1991-11-21 1993-03-30 Motorola, Inc. Multiple integrated circuit module which simplifies handling and testing
US6728113B1 (en) * 1993-06-24 2004-04-27 Polychip, Inc. Method and apparatus for non-conductively interconnecting integrated circuits
JPH07283364A (ja) * 1994-04-13 1995-10-27 Seiko Instr Inc 電子装置及びその製造方法
JPH09293824A (ja) * 1996-04-26 1997-11-11 Shinko Electric Ind Co Ltd マルチチップモジュール
DE10019483A1 (de) 2000-04-19 2001-10-31 Infineon Technologies Ag Halbleiterbauelement mit mehreren Halbleiterchips
JP4616985B2 (ja) * 2000-11-29 2011-01-19 富士通セミコンダクター株式会社 半導体装置
TW588446B (en) * 2003-03-21 2004-05-21 Advanced Semiconductor Eng Multi-chips stacked package
TWI225291B (en) * 2003-03-25 2004-12-11 Advanced Semiconductor Eng Multi-chips module and manufacturing method thereof
KR100621992B1 (ko) * 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
JP4587676B2 (ja) * 2004-01-29 2010-11-24 ルネサスエレクトロニクス株式会社 チップ積層構成の３次元半導体装置
US7067910B2 (en) * 2004-04-13 2006-06-27 Sun Microsystems, Inc. Method and apparatus for using capacitively coupled communication within stacks of laminated chips
JP4441328B2 (ja) * 2004-05-25 2010-03-31 株式会社ルネサステクノロジ 半導体装置及びその製造方法
JP2006073651A (ja) * 2004-08-31 2006-03-16 Fujitsu Ltd 半導体装置
US20060095639A1 (en) 2004-11-02 2006-05-04 Guenin Bruce M Structures and methods for proximity communication using bridge chips
US20060096639A1 (en) * 2004-11-05 2006-05-11 Gregory Coogle Condensate drain tray connector
JP4581768B2 (ja) * 2005-03-16 2010-11-17 ソニー株式会社 半導体装置の製造方法
JP2007036104A (ja) * 2005-07-29 2007-02-08 Nec Electronics Corp 半導体装置およびその製造方法
JP2007180529A (ja) * 2005-12-02 2007-07-12 Nec Electronics Corp 半導体装置およびその製造方法
US7554195B2 (en) * 2006-01-03 2009-06-30 Sun Microsystems, Inc. Engine with cable direct to outboard memory
US7514289B2 (en) * 2006-03-20 2009-04-07 Sun Microsystems, Inc. Methods and structures for facilitating proximity communication
US7390700B2 (en) * 2006-04-07 2008-06-24 Texas Instruments Incorporated Packaged system of semiconductor chips having a semiconductor interposer
RU2312425C1 (ru) * 2006-04-21 2007-12-10 Юрий Дмитриевич Сасов Трехмерный электронный модуль с шариковыми выводами
US7477535B2 (en) * 2006-10-05 2009-01-13 Nokia Corporation 3D chip arrangement including memory manager
JP2008124072A (ja) * 2006-11-08 2008-05-29 Toshiba Corp 半導体装置
JP2008192853A (ja) * 2007-02-05 2008-08-21 Sharp Corp 複数の半導体素子を備える半導体装置、および半導体装置の製造方法
US7553752B2 (en) * 2007-06-20 2009-06-30 Stats Chippac, Ltd. Method of making a wafer level integration package
TWI344694B (en) * 2007-08-06 2011-07-01 Siliconware Precision Industries Co Ltd Sensor-type package and method for fabricating the same
US8350382B2 (en) * 2007-09-21 2013-01-08 Infineon Technologies Ag Semiconductor device including electronic component coupled to a backside of a chip
US8008764B2 (en) * 2008-04-28 2011-08-30 International Business Machines Corporation Bridges for interconnecting interposers in multi-chip integrated circuits
US7969009B2 (en) * 2008-06-30 2011-06-28 Qualcomm Incorporated Through silicon via bridge interconnect
US8282766B2 (en) * 2008-11-19 2012-10-09 Austriamicrosystems Ag Etch apparatus and method of etching silicon nitride
US8274149B2 (en) * 2010-03-29 2012-09-25 Advanced Semiconductor Engineering, Inc. Semiconductor device package having a buffer structure and method of fabricating the same
US9082869B2 (en) * 2010-09-14 2015-07-14 Terapede Systems, Inc. Apparatus and methods for high-density chip connectivity
US9147672B1 (en) * 2014-05-08 2015-09-29 Macronix International Co., Ltd. Three-dimensional multiple chip packages including multiple chip stacks

Also Published As

Publication number Publication date
RU2461092C1 (ru) 2012-09-10
CA2727260C (en) 2017-08-08
US20090321939A1 (en) 2009-12-31
ES2812556T3 (es) 2021-03-17
WO2010002645A1 (en) 2010-01-07
JP2011527113A (ja) 2011-10-20
KR101209146B1 (ko) 2012-12-06
CA2727260A1 (en) 2010-01-07
EP2311088B1 (en) 2020-05-20
TWI483369B (zh) 2015-05-01
EP2311088A1 (en) 2011-04-20
BRPI0914112B1 (pt) 2020-08-11
TW201010038A (en) 2010-03-01
HUE051601T2 (hu) 2021-03-01
US20110215472A1 (en) 2011-09-08
KR20110025699A (ko) 2011-03-10
JP5763121B2 (ja) 2015-08-12
JP5265768B2 (ja) 2013-08-14
CN102077344A (zh) 2011-05-25
JP2013175772A (ja) 2013-09-05
RU2011103138A (ru) 2012-08-10
US7969009B2 (en) 2011-06-28
BRPI0914112A2 (pt) 2015-10-20
CN102077344B (zh) 2013-04-17

Similar Documents

Publication Publication Date Title
MX2010014181A (es) Interconexion de puente de vias a traves de silicio.
CN103700633B (zh) 半导体封装件
CN108155174B (zh) 包括堆叠芯片的半导体存储器件及具有其的存储模块
CN105826307B (zh) 包含内插器的半导体封装
CN104253115B (zh) 用于半导体封装中减小的管芯到管芯间隔的底部填充材料流控制
JP4587676B2 (ja) チップ積層構成の３次元半導体装置
CN101252115B (zh) 半导体封装及其制造方法和电子***及其制造方法
CN108074912B (zh) 包括互连器的半导体封装
CN108206178A (zh) 包括传热块的半导体封装及其制造方法
CN106910736A (zh) 半导体封装及其制造方法
KR20200092566A (ko) 브리지 다이를 포함한 반도체 패키지
US20090196086A1 (en) High bandwidth cache-to-processing unit communication in a multiple processor/cache system
CN106057788A (zh) 具有中介层的半导体封装及其制造方法
CN102290404A (zh) 半导体芯片封装及其制造方法
CN103620774A (zh) 倒装芯片、正面和背面线键合相组合的封装
US20110244634A1 (en) Semiconductor package and methods of manufacturing the same
CN103219325A (zh) 多维集成电路结构及其形成方法
KR20120001340A (ko) 임베디이드 칩 온 칩 패키지 및 이를 포함하는 패키지 온 패키지
CN107180816A (zh) 一种具有倾斜贯穿硅通道的晶片封装及其制备方法
CN110379798A (zh) 芯片层叠封装
CN107731667A (zh) 具备金属连线的混合键合方法及混合键合结构
CN106684066A (zh) 一种封装芯片及基于封装芯片的信号传输方法
TWI785666B (zh) 連接至處理單元之半導體記憶體堆疊以及相關系統及方法
TW201347120A (zh) 半導體晶片，具有該半導體晶片之半導體包裝，以及使用該半導體包裝之疊層半導體封裝
CN114400219A (zh) 半导体器件及其制造方法、封装器件和电子装置

Legal Events

Date Code Title Description
FG Grant or registration