MX173460B - Arbitraje dinamico de barra colectora, con transferencia que comparte cada ciclo - Google Patents

Arbitraje dinamico de barra colectora, con transferencia que comparte cada ciclo

Info

Publication number
MX173460B
MX173460B MX9101149A MX9101149A MX173460B MX 173460 B MX173460 B MX 173460B MX 9101149 A MX9101149 A MX 9101149A MX 9101149 A MX9101149 A MX 9101149A MX 173460 B MX173460 B MX 173460B
Authority
MX
Mexico
Prior art keywords
collector
arbitration
cycle
external device
priority
Prior art date
Application number
MX9101149A
Other languages
English (en)
Inventor
George Bohoslaw Marenin
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of MX173460B publication Critical patent/MX173460B/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/30—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal with priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

La presente invención se refiere a aparato para optimizar el arbitraje de colectores durante las transferencias de datos de acceso directo de memoria, a través de un colector no dedicado, entre una memoria y/o una pluralidad de dispositivos externos, cada uno con una prioridad de arbitraje, el aparato comprende: un elemento para suministrar cuando menos dos relojes no sobrepuestos por ciclo de transferencia y cuando menos un ciclo de transferencia por ciclo de arbitraje; un elemento para transmitir solicitudes de prioridad de arbitraje desde cada dispositivo externo a un colector de arbitraje, solamente en el ascenso del primero de los relojes; un elemento operativo en el final del último de los relojes, para determinar la clave de prioridad del dispositivo externo que tiene la prioridad más alta, para designar el dispositivo externo, el cual llega a ser el colector maestro, y elementos para transferir direcciones y datos entre el colector maestro designado y la memoria u otro dispositivo externo por vía del colector no dedicado, durante el siguiente ciclo, después de un control que abandona el colector maestro, entonces activo.
MX9101149A 1990-09-21 1991-09-19 Arbitraje dinamico de barra colectora, con transferencia que comparte cada ciclo MX173460B (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US58634990A 1990-09-21 1990-09-21

Publications (1)

Publication Number Publication Date
MX173460B true MX173460B (es) 1994-03-04

Family

ID=24345380

Family Applications (1)

Application Number Title Priority Date Filing Date
MX9101149A MX173460B (es) 1990-09-21 1991-09-19 Arbitraje dinamico de barra colectora, con transferencia que comparte cada ciclo

Country Status (18)

Country Link
US (1) US5195185A (es)
EP (1) EP0476990B1 (es)
JP (1) JPH0810445B2 (es)
KR (1) KR950014505B1 (es)
CN (1) CN1037553C (es)
AU (1) AU639589B2 (es)
BR (1) BR9103929A (es)
CA (1) CA2050129C (es)
CZ (1) CZ282214B6 (es)
DE (1) DE69132344T2 (es)
FI (1) FI914429A (es)
HU (1) HU215867B (es)
MX (1) MX173460B (es)
NO (1) NO913707L (es)
PL (1) PL167608B1 (es)
PT (1) PT99006A (es)
RU (1) RU2110838C1 (es)
SG (1) SG42853A1 (es)

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Also Published As

Publication number Publication date
CN1060166A (zh) 1992-04-08
PL291778A1 (en) 1992-06-01
AU639589B2 (en) 1993-07-29
NO913707L (no) 1992-03-23
FI914429A0 (fi) 1991-09-20
EP0476990B1 (en) 2000-08-02
CA2050129A1 (en) 1992-03-22
CA2050129C (en) 1996-05-14
US5195185A (en) 1993-03-16
HU913024D0 (en) 1992-01-28
KR920006858A (ko) 1992-04-28
PT99006A (pt) 1993-10-29
DE69132344T2 (de) 2001-02-15
RU2110838C1 (ru) 1998-05-10
KR950014505B1 (ko) 1995-12-02
PL167608B1 (pl) 1995-09-30
AU8261291A (en) 1992-03-26
HUT58931A (en) 1992-03-30
NO913707D0 (no) 1991-09-20
EP0476990A3 (en) 1993-08-04
CS287491A3 (en) 1992-04-15
CZ282214B6 (cs) 1997-06-11
CN1037553C (zh) 1998-02-25
FI914429A (fi) 1992-03-22
SG42853A1 (en) 1997-10-17
JPH04246758A (ja) 1992-09-02
BR9103929A (pt) 1992-05-26
JPH0810445B2 (ja) 1996-01-31
HU215867B (hu) 1999-03-29
DE69132344D1 (de) 2000-09-07
EP0476990A2 (en) 1992-03-25

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