KR970063686A - 유기 기판을 구비한 전자 요소의 제조 방법 - Google Patents
유기 기판을 구비한 전자 요소의 제조 방법 Download PDFInfo
- Publication number
- KR970063686A KR970063686A KR1019960076645A KR19960076645A KR970063686A KR 970063686 A KR970063686 A KR 970063686A KR 1019960076645 A KR1019960076645 A KR 1019960076645A KR 19960076645 A KR19960076645 A KR 19960076645A KR 970063686 A KR970063686 A KR 970063686A
- Authority
- KR
- South Korea
- Prior art keywords
- slot
- inner edge
- final package
- organic substrate
- package body
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15182—Fan-in arrangement of the internal vias
- H01L2924/15183—Fan-in arrangement of the internal vias in a single layer of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Perforating, Stamping-Out Or Severing By Means Other Than Cutting (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Manufacturing Of Electrical Connectors (AREA)
- Electroluminescent Light Sources (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structure Of Printed Boards (AREA)
Abstract
집적 회로를 패키지하는 방법은 하나 이상의 디바이스 사이트(312)를 구비한 유기 기판(310)을 제공함으로써 시작된다. 각 디바이스 내에서, 하나 이상의 전자 디바이스(532)가 설치된다. 디바이스 사이트 주위에는 슬롯(316) 및 코너 구멍(318)이 형성된다. 한 실시예에 있어서, 노치(326)와 같은, 네거티브 형태는 슬롯의 내부 에지(315)를 따라 기판에서 형성된다. 전자 디바이스가 설치되어 플라스틱 패키지 몸체(320)에서 개별화된 후, 디바이스는 최종 패키지 경계선(317)의 코너 영역을 펀칭함으로써 기판으로부터 절단된다. 슬롯, 코너 구멍, 및 노치의 배치는 버르가 없는 펀치 주위에 귀착되어, 최대 실제 접속 영역을 제공하고 펀칭 동작 동안 표면 또는 에지의 손상을 최소화한다. 노치를 대신하여, 돌출부(426)와 같은, 포지티브 형태를 펀칭 도구 세그먼트로 합체하여도 동일한 장점을 제공할 수 있다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제7도는 본 발명의 한 실시예에 따라 노치를 포함하는 새로운 유기 기판 구조 및 단일 디바이스 사이트를 도시한 평면 투시도.
Claims (4)
- 전자 요소의 제조 방법에 있어서, 다수의 전도 트레이스(536)와 4측부의 각각을 따라 형성된 슬롯(316)를 갖는 디바이스 사이트(312)를 구비하며, 각 슬롯의 내부 에지는 최종 패키지 몸체(320)의 외형 크기를 한정하고, 각 슬롯은 두 단부를 구비하며, 형태(326)는 유기 기판에 형성되어 각 슬롯의 각 두 단부 부근의 내부 에지를 따라 배치되는 구성의 유기 기판(310)을 제공하는 단계와, 디바이스 사이트 내에 전자 디아비스(532)를 설치하는 단계와, 전자 디바이스를 다수의 전도 트레이스에 전기적으로 접속하는 단계와, 형태가 절단 동작중에 최종 패키지의 외부 에지의 손상을 방지하도록, 유기 기판으로부터 최종 패키지 몸체를 절단하는 단계를 포함하는 것을 특징으로 하는 전자 요소의 제조 방법.
- 전자 요소의 제조 방법에 있어서, 다수의 슬롯(316)에 의해 한정된 디바이스 사이트와 다수의 전도 트레이스(536)를 구비하고, 각 슬롯은 최종 패키지 몸체(320)의 외부 에지를 한정하는 내부 에지를 가지며 또한 두 대향하는 단부를 구비한 구성의 유기 기판(310)을 제공하는 단계와, 각 슬롯의 내부 에지를 따라서 두 대향하는 각 단부 부근에서 네거티브 형태(326)를 제공하는 단계와, 전자 디바이스(532)를 디바이스 사이트 내에 설치하는 단계와, 전자 디바이스를 다수의 전도 트레이스에 전기적으로 접속하는 단계와, 형태가 절단 동작중에 최종 패키지의 외부 에지의 손상을 방지하도록, 유기 기판으로부터 최종 패키지 몸체를 절단하는 단계를 포함하는 것을 특징으로 하는 전자 요소의 제조 방법.
- 반도체 디바이스의 제조 방법에 있어서, 다수의 전도 트레이스(536)와, 4측부와, 4측부의 각각을 따라 형성된 슬롯(316)를 갖는 디바이스 사이트를 구비하며, 각 슬롯의 내부 에지는 최종 패키지 몸체(320)의 외형 크기를 한정하고, 각 슬롯은 두 단부를 구비하며, 노치(326)는 각 슬롯의 각 두 단부 부근에서 내부 에지를 따라 형성된 구성의 유기 기판(310)을 제공하는 단계와, 디바이스 사이트 내에 반도체 다이(532)를 설치하는 단계와, 반도체 다이를 다수의 전도 트레이스에 전기적으로 접속하는 단계와, 각 노치와 일치하는 종단부를 구비한 펀치를 사용함으로써 디바이스 사이트의 코너에서 펀칭작업이 실행되도록, 유기 기판으로부터 최종 패키지 몸체를 펀칭하는 단계를 포함하는 것을 특징으로 하는 반도체 디바이스의 제조 방법.
- 반도체 디바이스의 제조 방법에 있어서, 다수의 전도 트레이스(536)와, 4측부와, 4측부의 각각을 따라 형성된 슬롯(316)를 갖는 디바이스 사이트를 구비하며, 각 슬롯의 내부 에지는 최종 패키지 몸체(320)의 외형 크기를 한정하고, 각 슬롯은 두 단부를 구비하며, 드릴된 구멍(326)은 각 슬롯의 두 단부의 각각의 부근에서 내부 에지를 따라 형성되고, 바이어(538)가 안쪽에 형성된 구성의 유기 기판(320)을 제공하는 단계를 포함하며, 상기 바이어는 제1직경을 구비하고, 드릴된 구멍은 제1직경과 실제로 동일한 제2직경을 구비하는 것을 특징으로 하는 반도체 디바이스의 제조 방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/606,981 US5691242A (en) | 1996-02-26 | 1996-02-26 | Method for making an electronic component having an organic substrate |
US606,981 | 1996-02-26 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970063686A true KR970063686A (ko) | 1997-09-12 |
KR100429319B1 KR100429319B1 (ko) | 2004-07-19 |
Family
ID=24430314
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019960076645A KR100429319B1 (ko) | 1996-02-26 | 1996-12-30 | 유기기판을가진전자부품을제조하기위한방법 |
Country Status (7)
Country | Link |
---|---|
US (1) | US5691242A (ko) |
JP (1) | JP4010591B2 (ko) |
KR (1) | KR100429319B1 (ko) |
CN (1) | CN1110076C (ko) |
MX (1) | MX9700608A (ko) |
MY (1) | MY113012A (ko) |
TW (1) | TW356588B (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101147929B1 (ko) * | 2005-02-05 | 2012-05-22 | 하이맥스 테크놀로지스, 인코포레이션 | 슬롯을 구비한 기판 |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4161399B2 (ja) * | 1998-03-12 | 2008-10-08 | 沖電気工業株式会社 | 半導体装置用樹脂基板及び半導体装置 |
JPH11354689A (ja) * | 1998-06-04 | 1999-12-24 | Oki Electric Ind Co Ltd | フレーム状基板とその製造方法及び半導体装置の製造方法 |
JP2001102486A (ja) * | 1999-07-28 | 2001-04-13 | Seiko Epson Corp | 半導体装置用基板、半導体チップ搭載基板、半導体装置及びその製造方法、回路基板並びに電子機器 |
JP2001319567A (ja) * | 2000-02-28 | 2001-11-16 | Ricoh Co Ltd | 電子源基板および該電子源基板を用いた画像表示装置 |
US6319750B1 (en) * | 2000-11-14 | 2001-11-20 | Siliconware Precision Industries Co., Ltd. | Layout method for thin and fine ball grid array package substrate with plating bus |
US7148561B2 (en) | 2001-03-29 | 2006-12-12 | Siliconware Precision Industries Co., Ltd. | Ball grid array substrate strip with warpage-preventive linkage structure |
CN101241894A (zh) * | 2007-09-20 | 2008-08-13 | 三星电子株式会社 | 智能卡金属载带及其制造方法和包括该载带的封装模块 |
JP2010004011A (ja) * | 2008-05-19 | 2010-01-07 | Panasonic Corp | 半導体装置及び半導体装置の製造方法 |
CN102097317B (zh) * | 2010-12-01 | 2015-04-29 | 佛山市南海区宏乾电子有限公司 | 一种全包封装开关电源三极管的生产方法 |
KR101935553B1 (ko) * | 2012-02-01 | 2019-01-07 | 삼성디스플레이 주식회사 | 플렉시블 디스플레이 장치 및 그 제조방법 |
EP3210396A1 (en) | 2014-10-20 | 2017-08-30 | Axon Enterprise, Inc. | Systems and methods for distributed control |
TWI638410B (zh) * | 2017-11-14 | 2018-10-11 | 蔡宜興 | 降低封裝基板翹曲的方法及半成品結構 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0286138A (ja) * | 1988-09-22 | 1990-03-27 | Hitachi Ltd | 半導体装置 |
JPH0744405Y2 (ja) * | 1989-03-07 | 1995-10-11 | ローム株式会社 | プリント基板の切断装置 |
JPH0821658B2 (ja) * | 1990-01-18 | 1996-03-04 | 株式会社三井ハイテック | リードフレームの製造方法 |
US5403785A (en) * | 1991-03-03 | 1995-04-04 | Matsushita Electric Works, Ltd. | Process of fabrication IC chip package from an IC chip carrier substrate and a leadframe and the IC chip package fabricated thereby |
US5429992A (en) * | 1994-05-25 | 1995-07-04 | Texas Instruments Incorporated | Lead frame structure for IC devices with strengthened encapsulation adhesion |
JP3257904B2 (ja) * | 1994-08-11 | 2002-02-18 | 新光電気工業株式会社 | リードフレームとその製造方法 |
-
1996
- 1996-02-26 US US08/606,981 patent/US5691242A/en not_active Expired - Lifetime
- 1996-03-27 TW TW085103677A patent/TW356588B/zh not_active IP Right Cessation
- 1996-12-30 KR KR1019960076645A patent/KR100429319B1/ko not_active IP Right Cessation
-
1997
- 1997-01-21 CN CN97100387A patent/CN1110076C/zh not_active Expired - Lifetime
- 1997-01-23 MX MX9700608A patent/MX9700608A/es unknown
- 1997-02-20 JP JP05247797A patent/JP4010591B2/ja not_active Expired - Lifetime
- 1997-02-26 MY MYPI97000732A patent/MY113012A/en unknown
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101147929B1 (ko) * | 2005-02-05 | 2012-05-22 | 하이맥스 테크놀로지스, 인코포레이션 | 슬롯을 구비한 기판 |
Also Published As
Publication number | Publication date |
---|---|
MX9700608A (es) | 1997-08-30 |
US5691242A (en) | 1997-11-25 |
TW356588B (en) | 1999-04-21 |
MY113012A (en) | 2001-10-31 |
CN1162194A (zh) | 1997-10-15 |
JPH1027861A (ja) | 1998-01-27 |
CN1110076C (zh) | 2003-05-28 |
JP4010591B2 (ja) | 2007-11-21 |
KR100429319B1 (ko) | 2004-07-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR970063686A (ko) | 유기 기판을 구비한 전자 요소의 제조 방법 | |
US6222270B1 (en) | Integrated circuit bonding pads including closed vias and closed conductive patterns | |
KR101077416B1 (ko) | 회로 기판 및 그 제조 방법, 회로 장치 및 그 제조 방법, 및 기판 | |
TW344109B (en) | Methods of making semiconductor devices | |
KR920005304A (ko) | 반도체집적회로장치의 배선접속구조 및 그 제조방법 | |
EP1455392A4 (en) | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME | |
KR840005921A (ko) | 전자 장치 | |
FI20050767A (fi) | Monikerroksinen langoituslevy ja menetelmä sen valmistamiseksi | |
KR950027962A (ko) | 반도체장치 및 그 제조방법 | |
KR960039290A (ko) | 반도체 장치 | |
KR20040032873A (ko) | 카드 제조 기법 및 이에 의한 카드 | |
KR930001361A (ko) | 플립 칩 실장 및 결선 패키지 및 그 방법 | |
KR890018026A (ko) | Ic유니트 및 그 접합방법 | |
KR950004532A (ko) | 고집적 반도체 배선구조 및 그 제조방법 | |
ATE533229T1 (de) | Elektronische vorrichtung | |
KR960039426A (ko) | 전계효과에 의해 제어가능한 반도체소자 | |
MXPA97000608A (en) | Method for making an electronic component having an organic substrate | |
US20040031588A1 (en) | Heat sink and method of removing heat from power electronics components | |
KR900001005A (ko) | 마스터 슬라이스(Master slice)방법을 사용하여 반도체 집적회로를 형성하는 방법 | |
KR960039417A (ko) | 반도체장치 및 그 제조방법 및 전자장치 | |
KR920015464A (ko) | 반도체 장치의 전극배선층 및 그 제조방법 | |
KR950012613A (ko) | 반도체 장치 및 그 제조 방법 | |
KR920018941A (ko) | 게이트 어레이(Gate array)및 그것을 사용한 반도체 집적회로 장치의 제조방법 | |
KR960015794A (ko) | 반도체소자 제조방법 | |
CN108615686B (zh) | 芯片封装结构的制作方法与基板结构 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20130408 Year of fee payment: 10 |
|
FPAY | Annual fee payment |
Payment date: 20140407 Year of fee payment: 11 |
|
LAPS | Lapse due to unpaid annual fee |