KR970060530A - 유전체 분리형 박막 반도체 장치 - Google Patents

유전체 분리형 박막 반도체 장치 Download PDF

Info

Publication number
KR970060530A
KR970060530A KR1019960052196A KR19960052196A KR970060530A KR 970060530 A KR970060530 A KR 970060530A KR 1019960052196 A KR1019960052196 A KR 1019960052196A KR 19960052196 A KR19960052196 A KR 19960052196A KR 970060530 A KR970060530 A KR 970060530A
Authority
KR
South Korea
Prior art keywords
region
thin film
oxide film
semiconductor device
silicon film
Prior art date
Application number
KR1019960052196A
Other languages
English (en)
Other versions
KR100249290B1 (ko
Inventor
유지 스즈키
히도미찌 타카노
마사히코 수주무라
요시이키 하야사키
다카시 기시다
요시후미 시라이
Original Assignee
이마이 기요스케
마쓰시타 덴코 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP01217396A external-priority patent/JP3210853B2/ja
Priority claimed from JP8012172A external-priority patent/JPH09205210A/ja
Application filed by 이마이 기요스케, 마쓰시타 덴코 가부시키가이샤 filed Critical 이마이 기요스케
Publication of KR970060530A publication Critical patent/KR970060530A/ko
Application granted granted Critical
Publication of KR100249290B1 publication Critical patent/KR100249290B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L29/78624—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

유전체 분리형 (SIO형) 박막 트랜지스터는 반도체 기판 상에 형성된 매설 산화막과 매설 산화막 상에 형성된 제1전도성 타입의 실리콘 막과, 실리콘 막 상에 형성된 상부 산화막을 구비한다. 실리콘 막은 제2전도성 타입의 보디 영역과 제1전도성 타입의 소스 영역과, 제1전도형 타입의 드레인 영역과, 제1전도성 드리프트 영역을 가진다. 실리콘 막은 도핑 영역에 형성된 T1 두께의 제1부분 및 보디 영역이 매설 산화막에 도달하도록 형성된 보디 영역에 T2 두께의 제2부분을 형성한다.
두께(T1 및 T2)는 다음 관계를 만족하도록 결정된다.
0.4㎛＜T1, 0.4㎛≤T2≤1.5㎛, T2＜T1.
트랜지스터는 개선된 동력 소산과 높은 내전압 및 낮은 저항성을 나타내고, 트랜지스터 제조 공정에 이점을 제공한다.

Description

유전체 분리형 박막 반도체 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제5a도는 본 발명에 따른 제2실시예의 박막 트랜지스터의 단면도이다.
제5b도는 제5a도의 필드 플레이트와 선형 도핑 영역 사이의 측면 거리(L)과 파손 전압 (V) 간의 관계를 나타낸 도면.

Claims (7)

  1. 유전체 분리형(SOI형) 박막 반도체 장치에 있어서, 반도체 기판 상에 형성된 매설 산화막과; 상기 매설 산화막 상에 형성된 제1전도형의 실리콘 막과; 상기 실리콘 막상에 형성된 상부 산화막과; 상기 보디 영역 및 소스 영역 모두에 접촉되는 소스 전극과; 상기 드레인 영역에 접촉되는 드레인 전극과; 박막 산화막에 의해 상기 실리콘 막으로부터 이격되며 상기 소스 및 드레인 전극 사이에 배치된 게이트 전극을 구비하며 상기 실리콘 막이 제2전도형의 보디 영역과, 상기 제1전도형의 소스 영역과, 상기 제1전도형의 드레인 영역과, 상기 소스와 드레인 영역 사이에 형성된 상기 제1전도형의 드리프트 영역을 가지며, 상기 소스 영역은 상기 매설 산화막으로부터 이격되는 상기 보디 영역에 형성되며, 상기 실리콘 막은 상기 드리프트 영역이 형성되는 제1부분의 두께(T1)와, 상기 보디 영역이 형성되어 상기 매설 산화막에 도달하는 제2부분의 두께(T2)로 형성되며, 상기 두께(T1 및 T2)가 다음의 관계식
    0.4㎛＜T1, 0.4㎛≤T2≤1.5㎛, T2＜T1을 만족시키는 것을 특징으로 하는 유전체 분리형(SOI형) 박막 반도체 장치.
  2. 제1항에 있어서, 상기 제1 및 제2전도형은 각각 n형 및 p형인 것을 특징으로 하는 박막 반도체 장치.
  3. 제1항에 있어서, 상기 드리프트 영역은 측면 선형 도핑 영역을 형성하는 것을 특징으로 하는 박막 반도체 장치.
  4. 제3항에 있어서, 상기 게이트 전극은 게이트 전극에 단락되는 필드 플레이트를 가지며, 상기 게이트 전극과 필드 플레이트는 상기 실리콘 막으로부터 이격관계로 상기 선형 도핑 영역 상에 놓이지 않고 측면으로 연장되는 것을 특징으로 하는 박막 반도체 장치.
  5. 제1항에 있어서, 상기 두께(T1)는 1㎛ 이상인 것을 특징으로 하는 박막 반도체 장치.
  6. 제1항에 있어서, 상기 실리콘 막은 상부 면상에 상기 제2부분으로부터 상기 제1부분으로 연장되는 기울기로 형성되고, 상기 보디 영역은 상기 제2부분으로부터 상기 제1부분을 향하여 상기 기울기를 따라 연장되며, 상기 게이트 전극은 상기 기울기와 평행하고, 상기 박막 산화막에서 상기 기울기로부터 이격된 관계로 연장되는 필드 플레이트를 가지는 것을 특징으로 하는 박막 반도체 장치.
  7. 제1항에 있어서, 상기 드레인 영역은 상기 매설 산화막으로부터 이격되도록 실리콘 막에 형성되는 것을 특징으로 하는 박막 반도체 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960052196A 1996-01-26 1996-10-31 절연체상 실리콘(soi)형 박막트랜지스터 KR100249290B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP96-012172 1996-01-26
JP96-012173 1996-01-26
JP01217396A JP3210853B2 (ja) 1996-01-26 1996-01-26 半導体装置
JP8012172A JPH09205210A (ja) 1996-01-26 1996-01-26 誘電体分離型半導体装置

Publications (2)

Publication Number Publication Date
KR970060530A true KR970060530A (ko) 1997-08-12
KR100249290B1 KR100249290B1 (ko) 2000-03-15

Family

ID=26347747

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960052196A KR100249290B1 (ko) 1996-01-26 1996-10-31 절연체상 실리콘(soi)형 박막트랜지스터

Country Status (7)

Country Link
US (1) US5780900A (ko)
EP (1) EP0786818B1 (ko)
KR (1) KR100249290B1 (ko)
CN (1) CN1081833C (ko)
DE (1) DE69634745T2 (ko)
HK (1) HK1000853A1 (ko)
TW (1) TW360982B (ko)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3527034B2 (ja) * 1996-09-20 2004-05-17 株式会社半導体エネルギー研究所 半導体装置
US6211551B1 (en) * 1997-06-30 2001-04-03 Matsushita Electric Works, Ltd. Solid-state relay
US6310378B1 (en) 1997-12-24 2001-10-30 Philips Electronics North American Corporation High voltage thin film transistor with improved on-state characteristics and method for making same
US6346451B1 (en) 1997-12-24 2002-02-12 Philips Electronics North America Corporation Laterial thin-film silicon-on-insulator (SOI) device having a gate electrode and a field plate electrode
KR100257765B1 (ko) * 1997-12-30 2000-06-01 김영환 기억소자 및 그 제조 방법
JPH11297941A (ja) * 1998-04-09 1999-10-29 Nec Corp 半導体装置
US5969387A (en) * 1998-06-19 1999-10-19 Philips Electronics North America Corporation Lateral thin-film SOI devices with graded top oxide and graded drift region
US6232636B1 (en) 1998-11-25 2001-05-15 Philips Electronics North America Corporation Lateral thin-film silicon-on-insulator (SOI) device having multiple doping profile slopes in the drift region
US6127703A (en) * 1999-08-31 2000-10-03 Philips Electronics North America Corporation Lateral thin-film silicon-on-insulator (SOI) PMOS device having a drain extension region
US6221737B1 (en) * 1999-09-30 2001-04-24 Philips Electronics North America Corporation Method of making semiconductor devices with graded top oxide and graded drift region
US6369408B1 (en) * 1999-10-06 2002-04-09 Agere Systems Guardian Corp. GaAs MOSFET having low capacitance and on-resistance and method of manufacturing the same
US6166411A (en) * 1999-10-25 2000-12-26 Advanced Micro Devices, Inc. Heat removal from SOI devices by using metal substrates
US6483147B1 (en) 1999-10-25 2002-11-19 Advanced Micro Devices, Inc. Through wafer backside contact to improve SOI heat dissipation
US6191453B1 (en) * 1999-12-13 2001-02-20 Philips Electronics North America Corporation Lateral insulated-gate bipolar transistor (LIGBT) device in silicon-on-insulator (SOI) technology
TW564557B (en) * 1999-12-22 2003-12-01 Matsushita Electric Works Ltd Semiconductor device and process for producing the same
US6552395B1 (en) 2000-01-03 2003-04-22 Advanced Micro Devices, Inc. Higher thermal conductivity glass for SOI heat removal
US6613643B1 (en) 2000-01-28 2003-09-02 Advanced Micro Devices, Inc. Structure, and a method of realizing, for efficient heat removal on SOI
US6847081B2 (en) * 2001-12-10 2005-01-25 Koninklijke Philips Electronics N.V. Dual gate oxide high-voltage semiconductor device
KR100489802B1 (ko) * 2002-12-18 2005-05-16 한국전자통신연구원 고전압 및 저전압 소자의 구조와 그 제조 방법
US7501669B2 (en) 2003-09-09 2009-03-10 Cree, Inc. Wide bandgap transistor devices with field plates
DE102004005948B4 (de) 2004-02-02 2009-04-02 Atmel Germany Gmbh MOS-Transistor und Verfahren zur Herstellung einer MOS-Transistorstruktur
CN100421255C (zh) * 2004-04-28 2008-09-24 台湾积体电路制造股份有限公司 完全耗尽型soi多临界电压应用
US7550783B2 (en) * 2004-05-11 2009-06-23 Cree, Inc. Wide bandgap HEMTs with source connected field plates
US7573078B2 (en) * 2004-05-11 2009-08-11 Cree, Inc. Wide bandgap transistors with multiple field plates
US9773877B2 (en) * 2004-05-13 2017-09-26 Cree, Inc. Wide bandgap field effect transistors with source connected field plates
KR100865365B1 (ko) * 2005-01-12 2008-10-24 샤프 가부시키가이샤 반도체 장치의 제조방법 및 반도체 장치
US7217604B2 (en) * 2005-01-31 2007-05-15 International Business Machines Corporation Structure and method for thin box SOI device
US11791385B2 (en) * 2005-03-11 2023-10-17 Wolfspeed, Inc. Wide bandgap transistors with gate-source field plates
US20060255377A1 (en) * 2005-05-12 2006-11-16 Der-Wei Tu Field effect transistor with novel field-plate structure
EP1921669B1 (en) 2006-11-13 2015-09-02 Cree, Inc. GaN based HEMTs with buried field plates
US7598128B2 (en) * 2007-05-22 2009-10-06 Sharp Laboratories Of America, Inc. Thin silicon-on-insulator double-diffused metal oxide semiconductor transistor
JP5479671B2 (ja) 2007-09-10 2014-04-23 ローム株式会社 半導体装置
US9847411B2 (en) 2013-06-09 2017-12-19 Cree, Inc. Recessed field plate transistor structures
US9679981B2 (en) 2013-06-09 2017-06-13 Cree, Inc. Cascode structures for GaN HEMTs
US10026830B2 (en) 2015-04-29 2018-07-17 Stmicroelectronics, Inc. Tunneling field effect transistor (TFET) having a semiconductor fin structure
US11195915B2 (en) * 2019-04-15 2021-12-07 Texas Instruments Incorporated Semiconductor devices with a sloped surface

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4922327A (en) * 1987-12-24 1990-05-01 University Of Toronto Innovations Foundation Semiconductor LDMOS device with upper and lower passages
US5246870A (en) 1991-02-01 1993-09-21 North American Philips Corporation Method for making an improved high voltage thin film transistor having a linear doping profile
US5362979A (en) * 1991-02-01 1994-11-08 Philips Electronics North America Corporation SOI transistor with improved source-high performance
DE69209678T2 (de) 1991-02-01 1996-10-10 Philips Electronics Nv Halbleiteranordnung für Hochspannungsverwendung und Verfahren zur Herstellung
JP2731056B2 (ja) * 1991-10-09 1998-03-25 シャープ株式会社 薄膜トランジスタの製造方法
EP0562271B1 (en) * 1992-03-26 1998-01-14 Texas Instruments Incorporated High voltage structure with oxide isolated source and resurf drift region in bulk silicon
JP3217554B2 (ja) * 1993-09-17 2001-10-09 株式会社東芝 高耐圧半導体装置
US5548150A (en) * 1993-03-10 1996-08-20 Kabushiki Kaisha Toshiba Field effect transistor
US5378912A (en) * 1993-11-10 1995-01-03 Philips Electronics North America Corporation Lateral semiconductor-on-insulator (SOI) semiconductor device having a lateral drift region
US5510275A (en) * 1993-11-29 1996-04-23 Texas Instruments Incorporated Method of making a semiconductor device with a composite drift region composed of a substrate and a second semiconductor material
US5382818A (en) * 1993-12-08 1995-01-17 Philips Electronics North America Corporation Lateral semiconductor-on-insulator (SOI) semiconductor device having a buried diode

Also Published As

Publication number Publication date
EP0786818A2 (en) 1997-07-30
TW360982B (en) 1999-06-11
US5780900A (en) 1998-07-14
CN1158009A (zh) 1997-08-27
EP0786818B1 (en) 2005-05-18
CN1081833C (zh) 2002-03-27
DE69634745T2 (de) 2006-02-23
EP0786818A3 (en) 1998-03-25
HK1000853A1 (en) 2002-08-23
DE69634745D1 (de) 2005-06-23
KR100249290B1 (ko) 2000-03-15

Similar Documents

Publication Publication Date Title
KR970060530A (ko) 유전체 분리형 박막 반도체 장치
KR100675990B1 (ko) 드레인 확장 영역을 갖는 측면 박막 실리콘 온 절연체(ｓｏｉ) ｐｍｏｓ 디바이스
KR100652449B1 (ko) 횡형 박막 실리콘-온-절연체 ｊｆｅｔ 디바이스
US5382818A (en) Lateral semiconductor-on-insulator (SOI) semiconductor device having a buried diode
JP3393148B2 (ja) 高電圧パワートランジスタ
JP3871352B2 (ja) 薄膜ｓｏｉ装置及びその製造方法
KR970072205A (ko) 에스. 오. 아이(soi)형 트랜지스터 및 그 제조방법
KR950034767A (ko) Mis형 반도체장치
US5648671A (en) Lateral thin-film SOI devices with linearly-graded field oxide and linear doping profile
US5710451A (en) High-voltage lateral MOSFET SOI device having a semiconductor linkup region
SE513283C2 (sv) MOS-transistorstruktur med utsträckt driftregion
KR940019013A (ko) 고전압 트랜지스터
KR960019497A (ko) Soi 구조를 가지는 반도체장치 및 그의 제조방법
US10170542B2 (en) Semiconductor device
KR900013652A (ko) 감소된 온 저항을 가진 soi구조의 고전압 반도체 장치
KR100701712B1 (ko) 수평 박막 ｓｏｉ 디바이스
KR930020738A (ko) 고전압 전력 트랜지스터 및 그 제조 방법
KR100320894B1 (ko) 반도체장치
KR960002880A (ko) 실리콘 온 인슐레이터(soi) 트랜지스터
KR950012769A (ko) 반도체 소자
KR960019766A (ko) 에스오아이(soi) 기판상의 모스페트(mosfet)
KR930022601A (ko) 반도체 장치의 제조방법
KR19980084367A (ko) 실리콘-온-인슐레이터 기판을 사용한 저감 표면 전계형 횡형 이중-확산 모스 트랜지스터에 대한 모델링 방법
KR950010138A (ko) 엠엔오에스(mnos)형 반도체장치
KR970063782A (ko) 고전압 트랜지스터

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20121203

Year of fee payment: 14

LAPS Lapse due to unpaid annual fee