KR970060510A - 반도체 장치 및 그 제조 방법 - Google Patents
반도체 장치 및 그 제조 방법 Download PDFInfo
- Publication number
- KR970060510A KR970060510A KR1019960041881A KR19960041881A KR970060510A KR 970060510 A KR970060510 A KR 970060510A KR 1019960041881 A KR1019960041881 A KR 1019960041881A KR 19960041881 A KR19960041881 A KR 19960041881A KR 970060510 A KR970060510 A KR 970060510A
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- gate electrode
- soi
- channel region
- insulating film
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 4
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000011810 insulating material Substances 0.000 claims abstract 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 2
- 229910052710 silicon Inorganic materials 0.000 claims 2
- 239000010703 silicon Substances 0.000 claims 2
- 239000012212 insulator Substances 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78636—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with supplementary region or layer for improving the flatness of the device
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
Abstract
종래의 기술에서는 메사 분리된 SOI층의 측단면에 절연 물질로 이루어진 측벽을 형성할 때, SOI층 상면에 에칭 손상을 받는다는 문제가 있고, 또한 SOI층상단부와 게이트 전극과의 거리가 짧았기 때문에 절연성에 문제가 있었다.
SOI층상에 게이트 절연막, 게이트 전극의 일부로서 작용하는 도전층을 순차 적층한 후, SOI층의 측단면 뿐만 아니라 게이트 절연막 및 도전층의 측단면에도 측벽을 형성하여 도전층상에 게이트 전극을 형성함으로써 SOI층 상면에 에칭 손상을 주지 않고 게이트 전극과 SOI층의 상단부와의 거리를 일정 이상의 크기로 하는 구조의 반도체 장치를 형성한다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예에 따른 반도체 장치의 단면도.
Claims (3)
- 절연막상에 형성된 메사 분리형 실리콘층 〔이하, SOI(Silicon On Insulator)층이라 함〕; 내부에 채널 영역 및 소오스/드레인 영역이 형성된 상기 SOI층의 상면에 게이트 절연막을 사이에 두고 형성된 도전층; 상기 채널영역의 단부이고, 상기 SOI층, 게이트 절연막, 도전층의 측잔면인 면에 부착하여 형성된 절연 물질로 이루어진측벽; 및 상기 도전층상에 형성된 게이트 전극을 구비하는 것을 특징으로 하는 반도체 장치.
- 절연막상에 형성되고, 내부에 채널 영역 및 소오스/드레인 영역이 형성된 SOI층; 상기 채널 영역상에 게이트 절연막을 사이에 두고 형성된 게이트 전극; 및 상기 SOI층, 게이트 절연막 및 게이트 전극의 측단면의 일부에 부착하열 형성된 절연 물질로 이루어진 측벽을 구비하는 것을 특징으로 하는 반도체 장치.
- 제2항에 있어서, 상기 채널 영역상에 형성되는 게이트 전극은 채널 영역 이외의 영역에 형성되는 게이트전극보다도 두껍게 형성되는 것을 특징으로 하는 반도체 장치.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP96-005712 | 1996-01-17 | ||
JP00571296A JP3472401B2 (ja) | 1996-01-17 | 1996-01-17 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970060510A true KR970060510A (ko) | 1997-08-12 |
KR100255575B1 KR100255575B1 (ko) | 2000-05-01 |
Family
ID=11618740
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019960041881A KR100255575B1 (ko) | 1996-01-17 | 1996-09-24 | 반도체 장치 및 그 제조 방법 |
Country Status (3)
Country | Link |
---|---|
US (2) | US6064090A (ko) |
JP (1) | JP3472401B2 (ko) |
KR (1) | KR100255575B1 (ko) |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4032443B2 (ja) * | 1996-10-09 | 2008-01-16 | セイコーエプソン株式会社 | 薄膜トランジスタ、回路、アクティブマトリクス基板、液晶表示装置 |
US6424010B2 (en) | 1996-11-15 | 2002-07-23 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a semiconductor device having reduced power consumption without a reduction in the source/drain breakdown voltage |
JP2000031489A (ja) * | 1998-07-08 | 2000-01-28 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
KR100316709B1 (ko) * | 1998-07-13 | 2001-12-12 | 윤종용 | 불휘발성 메모리 장치 제조 방법 |
JP2000208771A (ja) * | 1999-01-11 | 2000-07-28 | Hitachi Ltd | 半導体装置、液晶表示装置およびこれらの製造方法 |
KR100349366B1 (ko) * | 1999-06-28 | 2002-08-21 | 주식회사 하이닉스반도체 | 에스오아이 소자 및 그의 제조방법 |
JP3504212B2 (ja) * | 2000-04-04 | 2004-03-08 | シャープ株式会社 | Soi構造の半導体装置 |
TWI286338B (en) * | 2000-05-12 | 2007-09-01 | Semiconductor Energy Lab | Semiconductor device and manufacturing method thereof |
TW480576B (en) * | 2000-05-12 | 2002-03-21 | Semiconductor Energy Lab | Semiconductor device and method for manufacturing same |
TW501282B (en) * | 2000-06-07 | 2002-09-01 | Semiconductor Energy Lab | Method of manufacturing semiconductor device |
US6586809B2 (en) | 2001-03-15 | 2003-07-01 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
US6649457B2 (en) * | 2001-09-24 | 2003-11-18 | Sharp Laboratories Of America, Inc. | Method for SOI device isolation |
US6664582B2 (en) | 2002-04-12 | 2003-12-16 | International Business Machines Corporation | Fin memory cell and method of fabrication |
US6960810B2 (en) * | 2002-05-30 | 2005-11-01 | Honeywell International Inc. | Self-aligned body tie for a partially depleted SOI device structure |
US6991973B2 (en) | 2002-09-26 | 2006-01-31 | National Chiao Tung University | Manufacturing method of thin film transistor |
US20040063311A1 (en) * | 2002-09-26 | 2004-04-01 | National Chiao Tung University | Structure of thin film transistor and manufacturing method thereof |
US6794718B2 (en) * | 2002-12-19 | 2004-09-21 | International Business Machines Corporation | High mobility crystalline planes in double-gate CMOS technology |
JP2006222101A (ja) | 2003-01-10 | 2006-08-24 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
US7157774B2 (en) * | 2003-01-31 | 2007-01-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Strained silicon-on-insulator transistors with mesa isolation |
US7374981B2 (en) * | 2003-04-11 | 2008-05-20 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor, electronic device having the same, and method for manufacturing the same |
US6913959B2 (en) * | 2003-06-23 | 2005-07-05 | Advanced Micro Devices, Inc. | Method of manufacturing a semiconductor device having a MESA structure |
JP4470398B2 (ja) * | 2003-06-23 | 2010-06-02 | Tdk株式会社 | 電界効果トランジスタ |
US6955955B2 (en) * | 2003-12-29 | 2005-10-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | STI liner for SOI structure |
TWI240950B (en) * | 2004-03-26 | 2005-10-01 | Chi Mei Optoelectronics Corp | Thin film transistor, thin film transistor substrate, and methods for manufacturing the same |
US7358571B2 (en) * | 2004-10-20 | 2008-04-15 | Taiwan Semiconductor Manufacturing Company | Isolation spacer for thin SOI devices |
US10263013B2 (en) * | 2017-02-24 | 2019-04-16 | Globalfoundries Inc. | Method of forming an integrated circuit (IC) with hallow trench isolation (STI) regions and the resulting IC structure |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60258957A (ja) * | 1984-06-05 | 1985-12-20 | Nec Corp | Soi型半導体装置の製造方法 |
US4648173A (en) * | 1985-05-28 | 1987-03-10 | International Business Machines Corporation | Fabrication of stud-defined integrated circuit structure |
JP2537936B2 (ja) * | 1986-04-23 | 1996-09-25 | エイ・ティ・アンド・ティ・コーポレーション | 半導体デバイスの製作プロセス |
US4753986A (en) * | 1986-12-22 | 1988-06-28 | General Electric Company | Polyester compositions having high impact strength |
JPH0760901B2 (ja) * | 1989-06-27 | 1995-06-28 | 三菱電機株式会社 | 半導体装置 |
US5102809A (en) * | 1990-10-11 | 1992-04-07 | Texas Instruments Incorporated | SOI BICMOS process |
JP2700955B2 (ja) * | 1991-01-11 | 1998-01-21 | 三菱電機株式会社 | 電界効果型トランジスタを備えた半導体装置 |
JPH04239117A (ja) | 1991-01-14 | 1992-08-27 | Fujitsu Ltd | 熱処理装置 |
JP2717237B2 (ja) * | 1991-05-16 | 1998-02-18 | 株式会社 半導体エネルギー研究所 | 絶縁ゲイト型半導体装置およびその作製方法 |
JP2868168B2 (ja) * | 1991-08-23 | 1999-03-10 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
JPH05114735A (ja) * | 1991-09-04 | 1993-05-07 | Fujitsu Ltd | Mos型半導体装置 |
US5572040A (en) * | 1993-07-12 | 1996-11-05 | Peregrine Semiconductor Corporation | High-frequency wireless communication system on a single ultrathin silicon on sapphire chip |
US5477073A (en) * | 1993-08-20 | 1995-12-19 | Casio Computer Co., Ltd. | Thin film semiconductor device including a driver and a matrix circuit |
US5482871A (en) * | 1994-04-15 | 1996-01-09 | Texas Instruments Incorporated | Method for forming a mesa-isolated SOI transistor having a split-process polysilicon gate |
KR0151195B1 (ko) * | 1994-09-13 | 1998-10-01 | 문정환 | 박막 트랜지스터의 구조 및 제조방법 |
US5763904A (en) * | 1995-09-14 | 1998-06-09 | Kabushiki Kaisha Toshiba | Non-single crystal semiconductor apparatus thin film transistor and liquid crystal display apparatus |
US5702986A (en) * | 1995-12-05 | 1997-12-30 | Micron Technology, Inc. | Low-stress method of fabricating field-effect transistors having silicon nitride spacers on gate electrode edges |
-
1996
- 1996-01-17 JP JP00571296A patent/JP3472401B2/ja not_active Expired - Fee Related
- 1996-06-27 US US08/671,542 patent/US6064090A/en not_active Expired - Lifetime
- 1996-09-24 KR KR1019960041881A patent/KR100255575B1/ko not_active IP Right Cessation
-
2000
- 2000-01-31 US US09/494,352 patent/US6271065B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH09199730A (ja) | 1997-07-31 |
JP3472401B2 (ja) | 2003-12-02 |
US6271065B1 (en) | 2001-08-07 |
KR100255575B1 (ko) | 2000-05-01 |
US6064090A (en) | 2000-05-16 |
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