KR890003038A - 페데스탈 구조를 가지는 반도체 제조 공정 - Google Patents

페데스탈 구조를 가지는 반도체 제조 공정 Download PDF

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KR890003038A
KR890003038A KR1019880009592A KR880009592A KR890003038A KR 890003038 A KR890003038 A KR 890003038A KR 1019880009592 A KR1019880009592 A KR 1019880009592A KR 880009592 A KR880009592 A KR 880009592A KR 890003038 A KR890003038 A KR 890003038A
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forming
dielectric layer
substrate
over
layer
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엔. 쿠리 2세 다니엘
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빈센트 죠셉로너
모토로라 인코포레이티드
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Publication of KR890003038A publication Critical patent/KR890003038A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66265—Thin film bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/7317—Bipolar thin film transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/011—Bipolar transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/026—Deposition thru hole in mask
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/05—Etch and refill
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/053—Field effect transistors fets
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/135—Removal of substrate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)

Abstract

내용없음

Description

페데스탈 구조를 가지는 반도체 제조 공정
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도 내지 15, 17, 19 및 20도는 공정의 여러 단계 동안 페데스탈 구조를 가지는 반전된 실리콘중 절연 반도체 소자의 확대된 단면도

Claims (3)

  1. 페데스탈 구조를 가지는 반도체 제조 공정에 있어서, 제 1 기판을 제공하는 단계와, 상기 제 1 기판위에 제공하는 단계와, 상기 제 1 기판위에 제 1 유전층을 형성하는 단계와, 상기 제 1 유전층 위에 제 1 폴리실리콘층을 형성하는 단계와, 상기 제 1 폴리실리콘층 위에 제 2 유전층을 형성하는 단계와, 상기 제 2 유전층 위에 제 2 폴리실리콘층을 형성하는 단계와, 상기 제 2 폴리실리콘층 위에 제 3 유전층을 형성하는 단계와, 상기 제 1 기판까지 연장된 개구를 에피텍셜 영역을 형성하는 단계와, 상기 에피텍셜 영역 및 상기 제 3 유전층 위에 최종 유전층을 형성하는 단계오, 상기 최종 유전층에 제 2기판을 결합하는 단계오, 상기 반도체 소자르 반전하는 단계와, 상기 제 1 기판을 제거하는 단계와, 상기 반도체 소자에서다수의접촉 개구를 엣칭하는 단계와, 상기 접촉 개구에서 전기적인 접촉부를 형서하는 단계를 구비하는 것을 특징으로 하는 페데스탈 구조를 가지는 반도체 제조공정
  2. 페데스탈 구조를 가지는 반도체 제조 공정에 있어서, 제 1 기판을 제공하는 단계와 , 상기 제 1 기판 위에 제 1 유전층을 형성하는 단계와, 상기 제 1 유전층 위에 제 1 폴리실리콘층을 형성하는 단계와, 상기 제 1 폴리실리콘층을 도핑하는 단계와, 상기 도핑된 제 1 폴리실리콘층을 패턴 및 엣칭하는 단계와, 상기 제 1 폴리실리코층 위에 제 2 유전층을 형성하는 단계와, 상기 제 2 유전층 위에 제 2 폴리실리콘층을 형성하는 단계와, 상기 제 2 폴리실리콘층을 도핑하는 단계와, 상기 도핑된 제 2 폴리실리콘층을 패턴 및 엣칭하는 단계와, 상기 제 2 폴리실리콘층 위에 제 3 유전층을 형성하는 단계와, 상기 제 1, 제 2 및 제 3 유전층 뿐만아니라 상기 제 1및 제 2 폴리실리콘층을 통하여 상기 제 1 기판에 연장된 개구를 패턴 및 엣칭하는 단계와, 상기 개구에 상기 제 1 기판 위에 에피텍셜영역을 형성하는 단계와, 상기 에피텍셜 영역 및 상기 제 3 유전층 위에 제 4 유전층을 형성하는 단계와, 상기 제 4 유전층 위에 질화물층을 형성하는 단계와, 제 2 기판을 제공하는 단계와, 상기 질화물층에 상기 제 2 기판을 결합하는 단계와, 상기 반도체 소자로부터 상기 제 1 기판을 제거하는 단계와, 상기 반도체 소자를 반전하는 단계와, 상기 반도체 소자에 다수의 접촉 개구 패턴 및 엣칭하는 단계와, 상기 접촉 개구에 금속 결합을 형성하는 단계를 구비하는 것ㅇ르 특징으로 하는 페테스탈 구조를 가지는 반도체 제조 공정
  3. 페데스탈 구조를 가지는 반도체 제조 공정에 있어서, 제 1 기판을 제공하는 단계와, 제 1 기판 위에 제 1 유전층을 형성하는 단계와, 제 1 유전층 위에 제 1 전도형으로 도핑된 상기 제 1 폴리실리콘층을 형성하는 단계와, 상기 제 1 폴리실리콘층 위에 제 2 유전층을 형성하는 단계와, 상기 제 2 유전층 위에 제 2 전도형으로 도핑된 상기 제 2 폴리실리콘층을 형성하는 단계와, 상기 폴리실리콘층 위에 제 3 유전층을 형성하는 단계와, 상기 유전층 및 상기 폴리실리콘층을 통하여 상기 제 1 기판에 연장하는 개구를 엣칭하는 단계와, 상기 제 1 폴리실리콘층 위에 상기 개구를 산화물 모서리부를 형성하는 단계와, 상기 개구로 상기 제 1 기판 위에 에피텍셜영역을 형성하는 단계와, 상기 에피텍셜 드레인을 형성하는 단계와, 상기 제 1 폴리실리콘층에 게이트를 형성하는 단계와, 상기 에피텍셜 영역에 소오스를 형성하는 단계와, 상기 에피텍셜 영역 및 상기 제 3 유전층 위에 최종 유전층을 형성하는 단계와, 상기 최종 유전층에 제 2 기판을 결합하는 단계와, 상기 반도체 소자를 반전하는 단계와, 상기 제 1 기판을 제거하는 단계를 구비하는 것을 특징으로 하는 페데스탈 구조를 가지는 반도체 제조공정
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임
KR1019880009592A 1987-07-31 1988-07-29 페데스탈 구조를 가지는 반도체 제조 공정 KR890003038A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/079,984 US4902641A (en) 1987-07-31 1987-07-31 Process for making an inverted silicon-on-insulator semiconductor device having a pedestal structure
US79,984 1987-07-31

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KR890003038A true KR890003038A (ko) 1989-04-12

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US (1) US4902641A (ko)
EP (1) EP0301223B1 (ko)
JP (1) JP2549892B2 (ko)
KR (1) KR890003038A (ko)
DE (1) DE3886291D1 (ko)

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US4902641A (en) 1990-02-20
JP2549892B2 (ja) 1996-10-30
EP0301223B1 (en) 1993-12-15
EP0301223A3 (en) 1990-07-04
EP0301223A2 (en) 1989-02-01
JPS6444065A (en) 1989-02-16
DE3886291D1 (de) 1994-01-27

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