KR940012583A - 반도체 집적회로 장치 및 그 제조방법 - Google Patents

반도체 집적회로 장치 및 그 제조방법 Download PDF

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Publication number
KR940012583A
KR940012583A KR1019930024131A KR930024131A KR940012583A KR 940012583 A KR940012583 A KR 940012583A KR 1019930024131 A KR1019930024131 A KR 1019930024131A KR 930024131 A KR930024131 A KR 930024131A KR 940012583 A KR940012583 A KR 940012583A
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South Korea
Prior art keywords
semiconductor substrate
main surface
integrated circuit
semiconductor
substrate
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KR1019930024131A
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English (en)
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KR970007178B1 (ko
Inventor
요이찌 히루따
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사또 후미오
가부시끼가이샤 도시바
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Publication of KR940012583A publication Critical patent/KR940012583A/ko
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Publication of KR970007178B1 publication Critical patent/KR970007178B1/ko

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

고밀도 장착의 소형화, 박형화에 대한 내습성이 좋은 고신뢰성의 팩키지를 갖춘 반도체 집적 회로 장치 및 그 제조 방법을 제공한다.
팩키지로서 집적 회로가 형성된 실리콘 기판 (1)의 비활성 영역 (12) 및 실리콘 반도체 기판 (10)으로 이루어진 상부 기판을 사용한다. 그리고, 내부 회로의 예를 들면, 트랜지스터의 드레인을 외부의 회로에 접속하기 위해 활성 영역 (11)과 비활성 영역 (12)에 걸쳐 고농도 불순물 확산 영역 (3)을 형성하고, 이 영역 (3)은 비활성 영역 (12) 부분에서 외부 인출 리드 (4)와 접속시킨다. 이 리드가 활성 영역까지 들어가 있지 않기 때문에, 내습성이 좋아지고, 반도체 기판을 팩키지로서 이용하기 때문에, 얇은 형태 및 소형화가 가능하게 된다.

Description

반도체 집적회로 장치 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예의 반도체 집적 회로 장치의 단면도.
제2도는 제1도의 반도체 집적 회로 장치의 제조 공정의 단면도.
제3도는 제1도의 반도체 집적 회로 장치의 제조 공정의 단면도.
제4도는 제1도의 반도체 집적 회로 장치의 제조 공정의 단면도.
제5도는 제1도의 반도체 집적 회로 장치의 제조 공정의 단면도.

Claims (4)

  1. 반도체 기판 (1), 상기 반도체 기판의 주면 (主面)에 반도체 집적 회로가 형성되어 있는 활성영역 (11), 상기 반도체 기판 주면의 주변부의 반도체 집적 회로가 형성되지 않은 비활성영역 (12), 상기 반도체 기판 주면의 상기 비활성 영역에 형성된 접속 전극 (5), 한 단부는 상기 접속 전극에 접속되고, 다른 단부는 상기 반도체 기판의 주면 외부로 뻗어 있는 리드 (4), 상기 접속 전극과 상기 활성 영역에 형성된 집적 회로를 전기적으로 접속하는 접속 수단 (3, 23) 및 상기 반도체 기판의 주면 상에 형성되고, 적어도 상기 활성 영역, 상기 전기 접속 전극, 상기리드의 상기 반도체 기판의 주면 상에 배치되어 있는 부분 및 상기 접속 수단을 피복하는 밀봉 기판 (10)을 구비하고 있는 것을 특징으로 하는 반도체 집적 회로 장치.
  2. 제1항에 있어서, 상기 접속 수단이 상기 반도체 기판의 상기 활성 영역과 상기 비활성 영역의 경계에 걸쳐서 형성되어 있는 불순물 확산 영역 (3), 또는 상기 반도체 기판 상의 다결정실리콘막 (23)인 것을 특징으로 하는 반도체 집적회로 장치.
  3. 제1반도체 기판 (1), 상기 제1반도체 기판의 주면에 반도체 집적 회로가 형성되어 있는 활성 영역 (11), 상기 제1반도체 기판 주면의 주변부의 반도체 집적 회로가 형성되지 않는 비활성 영역 (12), 상기 제1반도체 기판 주면의 주변부의 비활성 영역에 형성된 접속 전극 (5), 한 단부는 상기 제1반도체 기판 주면의 외부로 뻗어 있는 리드 (4), 상기 제1반도체 기판 주면의 접속 전극과 상기 제1반도체 기판 주면의 활성 영역에 형성되어 있는 상기 반도체 집적 회로를 전기적으로 접속하는 접속 수단 (3), 상기 제1반도체 기판 주면에 주면과 마주보도록 배치되는 제2반도체 기판 (10), 상기 제2반도체 기판 주면에 반도체 집적 회로가 형성되어 있는 활성 영역 (110), 상기 제2반도체 기판 주면의 주변부의 반도체 집적회로가 형성되지 않은 비활성 영역 (120), 상기 제2반도체 기판 주면의 주변부의 비활성 영역에 형성된 접속 전극 (50), 한단부는 상기 제2반도체 기판 주면의 접속 전극에 접속되고, 다른 단부는 상기 제2반도체 기판 주면의 외부로 뻗어 있는 리드 (40) 및 상기 제2반도체 기판 주면의 접속 전극과 상기 제2반도체 기판 주면의 활성 영역에 형성된 집적 회로를 전기적으로 접속하는 접속 수단 (30)을 구비하고 있는 것을 특징으로 하는 반도체 집적 회로 장치.
  4. 보호 밴드를 반도체 기판의 주면 위와 밀봉 기판 위에 또는 제1반도체 기판의 주면 위와 제2반도체 기판의 주면 위에 각각 형성하는 공정, 상기 반도체 기판의 주면 위와 상기 밀봉 기판 위의 상기 보호 밴드, 또는 제1반도체 기판의 주면 위와 제2반도체 기판의 주면 위의 상기 보호 밴드를 정합시키는 공정 및 상기 정합된 보호 밴드에 초음파 진동을 가하여 이를 보호 밴드를 서로 결합시키는 공정을 포함하는 것을 특징으로 하는 반도체 집적 회로 장치의 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930024131A 1992-11-14 1993-11-13 반도체 집적 회로 장치 및 그 제조 방법 KR970007178B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP4328892A JPH06151616A (ja) 1992-11-14 1992-11-14 半導体集積回路装置及びその製造方法
JP92-328892 1992-11-14

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KR940012583A true KR940012583A (ko) 1994-06-23
KR970007178B1 KR970007178B1 (ko) 1997-05-03

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JP3296400B2 (ja) * 1995-02-01 2002-06-24 東芝マイクロエレクトロニクス株式会社 半導体装置、その製造方法およびＣｕ製リード
JPH0943628A (ja) * 1995-08-01 1997-02-14 Toshiba Corp 液晶表示装置
TW332336B (en) * 1997-09-15 1998-05-21 Winbond Electruction Company Anti-peeling bonding pad structure
KR100787678B1 (ko) * 2000-03-10 2007-12-21 스태츠 칩팩, 엘티디. 플립칩 내장형 리드프레임 패키지 및 그 처리과정
JP5135815B2 (ja) * 2006-02-14 2013-02-06 ミツミ電機株式会社 半導体集積回路装置

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US4862322A (en) * 1988-05-02 1989-08-29 Bickford Harry R Double electronic device structure having beam leads solderlessly bonded between contact locations on each device and projecting outwardly from therebetween
US5136354A (en) * 1989-04-13 1992-08-04 Seiko Epson Corporation Semiconductor device wafer with interlayer insulating film covering the scribe lines
US5317194A (en) * 1989-10-17 1994-05-31 Kabushiki Kaisha Toshiba Resin-sealed semiconductor device having intermediate silicon thermal dissipation means and embedded heat sink
JP3144817B2 (ja) * 1990-03-23 2001-03-12 株式会社東芝 半導体装置
JPH0590452A (ja) * 1991-09-25 1993-04-09 Sony Corp 樹脂封止型半導体装置

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KR970007178B1 (ko) 1997-05-03
US5463245A (en) 1995-10-31

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