KR920006860A - Multi-Process System Arbiter Delay Circuit - Google Patents

Multi-Process System Arbiter Delay Circuit Download PDF

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Publication number
KR920006860A
KR920006860A KR1019900015361A KR900015361A KR920006860A KR 920006860 A KR920006860 A KR 920006860A KR 1019900015361 A KR1019900015361 A KR 1019900015361A KR 900015361 A KR900015361 A KR 900015361A KR 920006860 A KR920006860 A KR 920006860A
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South Korea
Prior art keywords
bus
signal
output
master
collision
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KR1019900015361A
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Korean (ko)
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KR950008393B1 (en
Inventor
이승희
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안시환
삼성항공산업 주식회사
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Priority to KR1019900015361A priority Critical patent/KR950008393B1/en
Publication of KR920006860A publication Critical patent/KR920006860A/en
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Publication of KR950008393B1 publication Critical patent/KR950008393B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)

Abstract

내용 없음.No content.

Description

멀티프로세스 시스템 아비터지연회로Multi-Process System Arbiter Delay Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 통상적인 멀티프로세스 시스템의 구성도.1 is a block diagram of a conventional multiprocess system.

Claims (2)

시스템 프로세서(10)를 이용하여 테이터통신을 하기 위한 멀티프로세스 시스템에 있어서, 상기 시스템프로세서(10)내의 기억장소를 나타내기 위하여 지정된 번지를 선택하는 어드레스 디코더(20)와; 상기 시스템 프로세서(10)와 버퍼(90)를 연결하는 데이터라인을 통해서 전송되는 데이터를 상기 어드레스 디코더(20)에서 전송되는 신호로 선택함에 따른 레벨신호를 출력하는 상태레지스터(30)와; 상기 어드레스 디코더(20)에서 출력되는 신호를 받아서 버스제어신호들을 각 점퍼블록으로 출력하는 버스제어부(40)와; 상기 상태레지스터(30)의 레벨신호와 상기 버스제어부(40)의 버스요구신호를 조합하여 그 조합신호를 출력하는 마스터 세트모듈(50)과; 상기 마스터세트모듈(50)의 출력신호와 데이지체인을 이루는 백플레인(140)에서 전송되는 버스양도신호를 조합하여 그 조합신호를 버스제어부(40)에 전송하는 충돌방지모듈(60)과; 상기 시스템 프로세서(10)에서 출력되는 신호에 따라 시스템 제어신호들을 출력하는 마스터제어부(70)와; 상기 마스터제어부(70)에서 출력되는 시스템 제어신호들을 상태레지스터(30)의 출력신호에 따라서 선택하여 데이지체인을 이루는 백플레인(140)으로 전송하는 마스터선택버퍼(80)를 포함함을 특징으로 하는 멀티프로세스 시스템의 아비터지연회로.1. A multiprocess system for data communication using a system processor (10), comprising: an address decoder (20) for selecting a designated address to indicate a storage location in the system processor (10); A state register (30) for outputting a level signal according to the data transmitted through the data line connecting the system processor (10) and the buffer (90) as a signal transmitted from the address decoder (20); A bus controller 40 which receives a signal output from the address decoder 20 and outputs bus control signals to each jumper block; A master set module 50 for combining the level signal of the state register 30 with the bus request signal of the bus control unit 40 and outputting the combined signal; An anti-collision module 60 for combining the output signal of the master set module 50 with the bus transfer signal transmitted from the backplane 140 forming a daisy chain and transmitting the combined signal to the bus controller 40; A master controller (70) for outputting system control signals in accordance with the signal output from the system processor (10); And a master selection buffer (80) for selecting the system control signals output from the master controller (70) according to the output signal of the state register (30) and transmitting them to the backplane (140) forming a daisy chain. Arbiter delay circuit of the process system. 제1항에 있어서, 상기 충돌방지모듈(60)은 데이지체인의 백플레인(140)에서 전송되는 버스양도신호와 마스터세트모듈(50)에서 전송되는 신호를 오아게이트로 연결시켜 버스충돌이 일어나는 경우 "로우"액티브신호가 출력되어 버스제어부(40)를 제어함으로써 버스충돌을 막아주는 것을 특징으로 하는 멀티프로세스 시스템의 아비터지연회로.The method of claim 1, wherein the collision avoidance module 60 connects the bus transfer signal transmitted from the backplane 140 of the daisy chain and the signal transmitted from the master set module 50 to an oragate so that a bus collision occurs. A low delay active circuit is output to control the bus control unit 40 to prevent the bus collision, Arbiter delay circuit of the multi-process system. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900015361A 1990-09-27 1990-09-27 Arbeiter delay circuit for multiprocessor system KR950008393B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900015361A KR950008393B1 (en) 1990-09-27 1990-09-27 Arbeiter delay circuit for multiprocessor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900015361A KR950008393B1 (en) 1990-09-27 1990-09-27 Arbeiter delay circuit for multiprocessor system

Publications (2)

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KR920006860A true KR920006860A (en) 1992-04-28
KR950008393B1 KR950008393B1 (en) 1995-07-28

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KR1019900015361A KR950008393B1 (en) 1990-09-27 1990-09-27 Arbeiter delay circuit for multiprocessor system

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100242690B1 (en) * 1996-12-31 2000-02-01 강병호 Control device of subsystem using address line

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100242690B1 (en) * 1996-12-31 2000-02-01 강병호 Control device of subsystem using address line

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Publication number Publication date
KR950008393B1 (en) 1995-07-28

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