KR920013683A - Semiconductor leadframe - Google Patents

Semiconductor leadframe Download PDF

Info

Publication number
KR920013683A
KR920013683A KR1019900022666A KR900022666A KR920013683A KR 920013683 A KR920013683 A KR 920013683A KR 1019900022666 A KR1019900022666 A KR 1019900022666A KR 900022666 A KR900022666 A KR 900022666A KR 920013683 A KR920013683 A KR 920013683A
Authority
KR
South Korea
Prior art keywords
lead frame
semiconductor
split pads
chip
semiconductor leadframe
Prior art date
Application number
KR1019900022666A
Other languages
Korean (ko)
Other versions
KR940003588B1 (en
Inventor
송영재
권오식
권영신
이충우
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019900022666A priority Critical patent/KR940003588B1/en
Publication of KR920013683A publication Critical patent/KR920013683A/en
Application granted granted Critical
Publication of KR940003588B1 publication Critical patent/KR940003588B1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

내용 없음No content

Description

반도체 리드 프레임Semiconductor leadframe

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제5도는 이 발명에따른 리드프레임의 평면도, 제7도는 제5도의 리드프레임을 이용한 패키지의 단면.5 is a plan view of a lead frame according to the present invention, and FIG. 7 is a cross section of a package using the lead frame of FIG.

Claims (4)

칩을 본딩시켜 고정시키기 위한 리드프레임 패드와, 이 리드프레임 패드를 물리적으로 지지하는 지지대와, 칩과 금선등으로 연결되는 리드들을 구비한 반도체 리드프레임에 있어서, 상기 리드프레임 패드가 다수개의 분할패드들로 형성됨을 특징으로 하는 반도체 리드프레임.In a semiconductor lead frame having a lead frame pad for bonding and fixing a chip, a support for physically supporting the lead frame pad, and leads connected to the chip and a gold wire, the lead frame pad includes a plurality of split pads. A semiconductor lead frame, characterized in that formed with. 제1항에 있어서, 상기 분할 패드들은 서로 지지대로 연결됨을 특징으로 하는 반도체 리드 프레임.The semiconductor lead frame of claim 1, wherein the split pads are connected to each other by a support. 제1항에 있어서, 상기 분할패드들은 상부의 모서리가 스템핑 가공됨을 특징으로 하는 반도체 리드프레임.The semiconductor leadframe of claim 1, wherein the split pads are stamped at an upper edge thereof. 제1항에 있어서, 상기 분할 패드들에 다수의 딤풀이 형성됨을 특징으로 하는 반도체 리드 프레임.The semiconductor lead frame of claim 1, wherein a plurality of dimples are formed in the split pads. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: This is to be disclosed by the original application.
KR1019900022666A 1990-12-31 1990-12-31 Lead-frame of semiconductor device KR940003588B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900022666A KR940003588B1 (en) 1990-12-31 1990-12-31 Lead-frame of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900022666A KR940003588B1 (en) 1990-12-31 1990-12-31 Lead-frame of semiconductor device

Publications (2)

Publication Number Publication Date
KR920013683A true KR920013683A (en) 1992-07-29
KR940003588B1 KR940003588B1 (en) 1994-04-25

Family

ID=19309133

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900022666A KR940003588B1 (en) 1990-12-31 1990-12-31 Lead-frame of semiconductor device

Country Status (1)

Country Link
KR (1) KR940003588B1 (en)

Also Published As

Publication number Publication date
KR940003588B1 (en) 1994-04-25

Similar Documents

Publication Publication Date Title
KR890007410A (en) Semiconductor devices
KR920702549A (en) Semiconductor device and manufacturing method thereof
KR920015525A (en) Semiconductor device
KR920013683A (en) Semiconductor leadframe
KR920010803A (en) Wire Bonding Semiconductor Device
KR910020875A (en) Leadframe for IC
KR910001949A (en) Flagless Leadframes, Packages and Methods
KR910017608A (en) Resin Sealed Semiconductor Device
KR940016716A (en) Leadframe Structure for Mounting Rectangular Dies
KR930011190A (en) Semiconductor leadframe
KR920013684A (en) Semiconductor leadframe
KR920005377A (en) SOJ / ZIP Package with Jumper Pads
KR920001686A (en) Package structure using two-step bonding
KR920013689A (en) Lead frame of semiconductor device
KR920020690A (en) Semiconductor lead frame
KR930014851A (en) Semiconductor Package with Lead Frame
JPS62119933A (en) Integrated circuit device
KR970003871A (en) Semiconductor package
KR940018957A (en) Resin-sealed semiconductor device and grid flame
KR920010878A (en) Plastic Multichip Package
KR970067797A (en) Package with adhesive resin spill preventing dam on top of die pad
KR970024101A (en) Lead frame with internal leads installed in the slit of the die pad
KR890001185A (en) Leadframes for Semiconductor Devices
KR970024106A (en) Upset Adjusted Lead Frame and Semiconductor Chip Packages Using the Same
KR950015733A (en) Package for Semiconductor Devices

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20010308

Year of fee payment: 8

LAPS Lapse due to unpaid annual fee