KR920005377A - SOJ / ZIP Package with Jumper Pads - Google Patents

SOJ / ZIP Package with Jumper Pads Download PDF

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Publication number
KR920005377A
KR920005377A KR1019900012443A KR900012443A KR920005377A KR 920005377 A KR920005377 A KR 920005377A KR 1019900012443 A KR1019900012443 A KR 1019900012443A KR 900012443 A KR900012443 A KR 900012443A KR 920005377 A KR920005377 A KR 920005377A
Authority
KR
South Korea
Prior art keywords
soj
jumper
pad
zip
package
Prior art date
Application number
KR1019900012443A
Other languages
Korean (ko)
Other versions
KR930007187B1 (en
Inventor
김진성
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019900012443A priority Critical patent/KR930007187B1/en
Publication of KR920005377A publication Critical patent/KR920005377A/en
Application granted granted Critical
Publication of KR930007187B1 publication Critical patent/KR930007187B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

내용 없음No content

Description

제목 점퍼 패드를 이용한 SOJ/ZIP패캐지SOJ / ZIP Package with Title Jumper Pads

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도 (A)(B)는 본 발명에 따른 패캐지 구조를 보인 평면도로서 (A)도는 점퍼패드 SOJ패캐지 구조도, (B)도는 점퍼패드 ZIP 패캐지 구조도.2 is a plan view showing a package structure according to the present invention, (A) is a jumper pad SOJ package structure diagram, (B) is a jumper pad ZIP package structure diagram.

Claims (3)

패들(3)에 장착된 메모리 소자의 패드(2)와 리드프레임 내부도선(1)을 와이어 본딩하여 패캐지화 함에 있어서, 양측에 패드(2)가 형성된 SOP형의 칩 상하에 점퍼패드(5)를 형성한후 상기 점퍼 패드(5)와 패드(2)를 전송선(4)으로 연결하여 SOJ 패캐지 및 ZIP에 사용 가능토록 구성한 것을 특징으로 하는 점퍼 패드를 이용한 SOJ/ZIP패캐지.In the case where the pad 2 of the memory element mounted on the paddle 3 and the lead frame inner conductor 1 are wire-bonded and packaged, jumper pads 5 are disposed above and below the SOP chip having pads 2 formed on both sides thereof. SOJ / ZIP package using a jumper pad, characterized in that the jumper pad (5) and the pad (2) is connected to the transmission line (4) to be used in the SOJ package and ZIP. 제1항에 있어서, 패드(2)와 리드프레임 내부도선(1)을 와이어 본딩하여 SOJ패캐지에 사용 가능토록 구성한 것을 특징으로 하는 점퍼 패드를 이용한 SOJ/ZIP패캐지.The SOJ / ZIP package using jumper pads according to claim 1, wherein the pad (2) and the lead frame inner conductor (1) are wire-bonded to be used in the SOJ package. 제1항에 있어서, 점퍼 패드(5)와 리드프레임 내부도선(1)을 와이어 본딩하여 ZIP에 사용가능토록 구성한 것을 특징으로 하는 점퍼 패드를 이용한 SOJ/ZIP패캐지.The SOJ / ZIP package using a jumper pad according to claim 1, wherein the jumper pad (5) and the lead frame inner lead (1) are wire-bonded to be usable for ZIP. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900012443A 1990-08-13 1990-08-13 Structure of chip for using soj/zip package KR930007187B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900012443A KR930007187B1 (en) 1990-08-13 1990-08-13 Structure of chip for using soj/zip package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900012443A KR930007187B1 (en) 1990-08-13 1990-08-13 Structure of chip for using soj/zip package

Publications (2)

Publication Number Publication Date
KR920005377A true KR920005377A (en) 1992-03-28
KR930007187B1 KR930007187B1 (en) 1993-07-31

Family

ID=19302297

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900012443A KR930007187B1 (en) 1990-08-13 1990-08-13 Structure of chip for using soj/zip package

Country Status (1)

Country Link
KR (1) KR930007187B1 (en)

Also Published As

Publication number Publication date
KR930007187B1 (en) 1993-07-31

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