KR920007104A - 반도체소자의 제조방법 - Google Patents

반도체소자의 제조방법 Download PDF

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Publication number
KR920007104A
KR920007104A KR1019910014294A KR910014294A KR920007104A KR 920007104 A KR920007104 A KR 920007104A KR 1019910014294 A KR1019910014294 A KR 1019910014294A KR 910014294 A KR910014294 A KR 910014294A KR 920007104 A KR920007104 A KR 920007104A
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KR
South Korea
Prior art keywords
back surface
grinding
manufacturing
semiconductor device
gaas substrate
Prior art date
Application number
KR1019910014294A
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English (en)
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KR940002915B1 (ko
Inventor
마사노리 니시구찌
Original Assignee
나까하라 쯔네오
스미도모덴기고오교오 가부시기가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 나까하라 쯔네오, 스미도모덴기고오교오 가부시기가이샤 filed Critical 나까하라 쯔네오
Publication of KR920007104A publication Critical patent/KR920007104A/ko
Application granted granted Critical
Publication of KR940002915B1 publication Critical patent/KR940002915B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/135—Removal of substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Weting (AREA)

Abstract

내용 없음.

Description

반도체 소자의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 의한 반도체 소자의 제조방법의 1실시예의 특징 부분의 개략공정도
제2도는 숫돌입자직경과 마무리면 조도와의 관계를 표시한 도면
제3도는 에칭량과 이면의 표면상태계수와의 관계를 표시한 도면
* 도면의 주요부분에 대한 부호의 설명
1: 반도체 소자 형성공정 2: 기판의 이면연삭공정
3: 화학적에칭공정

Claims (1)

  1. GaAs 기판의 일평면상에 반도체 소자를 형성하는 소자형성공정과, 상기 GaAs 기판의 이면을 평균입자 직경이 6㎛ 이상의 숫돌을 사용해서 연삭하고, GaAs 기판을 소정의 두께로 하는 연삭공정과, 상기 연삭공정후, 상기 이면에 하등의 연삭처리를 실시하는 일없이, 그 이면을 화학적 에칭법에 의해 0.6㎛ 이상 에칭하는 공정을 포함하는 반도체 소자의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910014294A 1990-09-05 1991-08-20 반도체 소자의 제조방법 KR940002915B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2235152A JP2610703B2 (ja) 1990-09-05 1990-09-05 半導体素子の製造方法
JP2-235152 1990-09-05
JP90-235152 1990-09-05

Publications (2)

Publication Number Publication Date
KR920007104A true KR920007104A (ko) 1992-04-28
KR940002915B1 KR940002915B1 (ko) 1994-04-07

Family

ID=16981823

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910014294A KR940002915B1 (ko) 1990-09-05 1991-08-20 반도체 소자의 제조방법

Country Status (8)

Country Link
US (1) US5122481A (ko)
EP (1) EP0475259B1 (ko)
JP (1) JP2610703B2 (ko)
KR (1) KR940002915B1 (ko)
AU (1) AU649063B2 (ko)
CA (1) CA2050675A1 (ko)
DE (1) DE69112545T2 (ko)
DK (1) DK0475259T3 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023132518A1 (ko) * 2022-01-10 2023-07-13 도레이첨단소재 주식회사 고강도 메타 아라미드 섬유 및 그의 제조방법

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US5279704A (en) * 1991-04-23 1994-01-18 Honda Giken Kogyo Kabushiki Kaisha Method of fabricating semiconductor device
US5245794A (en) * 1992-04-09 1993-09-21 Advanced Micro Devices, Inc. Audio end point detector for chemical-mechanical polishing and method therefor
US5268065A (en) * 1992-12-21 1993-12-07 Motorola, Inc. Method for thinning a semiconductor wafer
US5480842A (en) * 1994-04-11 1996-01-02 At&T Corp. Method for fabricating thin, strong, and flexible die for smart cards
JPH0817777A (ja) * 1994-07-01 1996-01-19 Mitsubishi Materials Shilicon Corp シリコンウェーハの洗浄方法
US5691248A (en) * 1995-07-26 1997-11-25 International Business Machines Corporation Methods for precise definition of integrated circuit chip edges
US5648684A (en) * 1995-07-26 1997-07-15 International Business Machines Corporation Endcap chip with conductive, monolithic L-connect for multichip stack
US6059637A (en) * 1997-12-15 2000-05-09 Lsi Logic Corporation Process for abrasive removal of copper from the back surface of a silicon substrate
DE19921230B4 (de) * 1999-05-07 2009-04-02 Giesecke & Devrient Gmbh Verfahren zum Handhaben von gedünnten Chips zum Einbringen in Chipkarten
US6560871B1 (en) * 2000-03-21 2003-05-13 Hewlett-Packard Development Company, L.P. Semiconductor substrate having increased facture strength and method of forming the same
US6520844B2 (en) * 2000-08-04 2003-02-18 Sharp Kabushiki Kaisha Method of thinning semiconductor wafer capable of preventing its front from being contaminated and back grinding device for semiconductor wafers
EP3252806B1 (en) 2002-03-12 2019-10-09 Hamamatsu Photonics K.K. Substrate dividing method
JP4544876B2 (ja) * 2003-02-25 2010-09-15 三洋電機株式会社 半導体装置の製造方法
JP2005005380A (ja) * 2003-06-10 2005-01-06 Sanyo Electric Co Ltd 半導体装置の製造方法
JP2005026314A (ja) * 2003-06-30 2005-01-27 Sanyo Electric Co Ltd 固体撮像素子の製造方法
JP2005303218A (ja) * 2004-04-16 2005-10-27 Renesas Technology Corp 半導体装置およびその製造方法
JP4872208B2 (ja) * 2004-11-18 2012-02-08 富士電機株式会社 半導体装置の製造方法
JP5149020B2 (ja) * 2008-01-23 2013-02-20 株式会社ディスコ ウエーハの研削方法
GB2459301B (en) * 2008-04-18 2011-09-14 Xsil Technology Ltd A method of dicing wafers to give high die strength

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SU393073A1 (ru) * 1970-12-04 1973-08-10 Способ повышения долговечности алмазных, например выглаживающих инструментов
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FR2505713A1 (fr) * 1981-05-18 1982-11-19 Procedes Equip Sciences Ind Sa Porte-plaquette pour machines a polir des plaquettes minces, fragiles et deformables
DE3148957A1 (de) * 1981-12-10 1983-06-23 Wacker-Chemitronic Gesellschaft für Elektronik-Grundstoffe mbH, 8263 Burghausen "verfahren zur rueckseitengetternden oberflaechenbehandlung von halbleiterscheiben"
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023132518A1 (ko) * 2022-01-10 2023-07-13 도레이첨단소재 주식회사 고강도 메타 아라미드 섬유 및 그의 제조방법

Also Published As

Publication number Publication date
JPH04115528A (ja) 1992-04-16
EP0475259B1 (en) 1995-08-30
CA2050675A1 (en) 1992-03-06
US5122481A (en) 1992-06-16
KR940002915B1 (ko) 1994-04-07
AU8353891A (en) 1992-03-12
DE69112545D1 (de) 1995-10-05
EP0475259A2 (en) 1992-03-18
DK0475259T3 (da) 1996-01-15
JP2610703B2 (ja) 1997-05-14
AU649063B2 (en) 1994-05-12
EP0475259A3 (en) 1992-12-16
DE69112545T2 (de) 1996-05-02

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