KR920001685A - 반도체장치 및 그의 제조방법 - Google Patents

반도체장치 및 그의 제조방법 Download PDF

Info

Publication number
KR920001685A
KR920001685A KR1019910006314A KR910006314A KR920001685A KR 920001685 A KR920001685 A KR 920001685A KR 1019910006314 A KR1019910006314 A KR 1019910006314A KR 910006314 A KR910006314 A KR 910006314A KR 920001685 A KR920001685 A KR 920001685A
Authority
KR
South Korea
Prior art keywords
layer
insulating film
metal wiring
conductive
silicon
Prior art date
Application number
KR1019910006314A
Other languages
English (en)
Other versions
KR950000866B1 (ko
Inventor
고지 에구찌
Original Assignee
시기 모리야
미쓰비시 뎅끼 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 시기 모리야, 미쓰비시 뎅끼 가부시끼가이샤 filed Critical 시기 모리야
Publication of KR920001685A publication Critical patent/KR920001685A/ko
Application granted granted Critical
Publication of KR950000866B1 publication Critical patent/KR950000866B1/ko

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226Via connections in a multilevel interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/927Electromigration resistant metallization

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음

Description

반도체장치 및 그의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1의 실시예의 콘택트 구멍 근방의 구조를 표시하는 단면도.
제2도는 본 발명의 제2의 실시예의 콘택트 구멍 근방의 구조를 표시하는 단면도.
제3A도 내지 제3F도는 제1도에 표시한 제1의 실시예의 구조를 형성하는 제조공정의 1예를 순차표시하는 단면도.

Claims (2)

  1. 도전층과, 이 도전층 표면에 형성된 절연막과, 이 절연막상에 형성되어 또한 이 절연막의 소정위치에 형성된 콘택트 구멍에 있어서, 상기 도전층과 전기적으로 접속되는 도전성 금속배선층을 구비한 반도체장치에 있어서, 상기도전성 금속배선층과 상기 도전층의 표면과는 직접 접합되어 있고, 상기 도전성 금속배선층과 상기 절연막과의 사이에는 단결정체로 되는 또는 립경이 적어도 약 10㎛이상으로 대립경화한 다결정체로 되는 결정체 실리콘층을 개재하게 한 것을 특징으로 하는 반도체 장치
  2. 도전층 표면상에 절연막을 퇴적하게 하는 공정과, 이 절연막 표면상에 다결정 실리콘 또는 비결정질 실리콘으로되는 실리콘층을 형성하는 공정과, 상기 실리콘층 및 상기 절연층의 소정위치에 상기 도전층 표면이 노출하도록 콘택트 구멍을 형성하는 공정과, 상기 콘택트 구멍의 내부표면을 포함하고 상기 실리콘층 표면상에 도전성 금속배선층을 형성하는 공정과, 상기 도전성 금속배선층 및 상기 실리콘층을 필요에 따라 패터닝하는 공정과를 구비한 반도체장치의 제조 방법에 있어서, 상기 실리콘층을 형성하는 공정의 후 상기 도전성 금속 배선층을 형성하는 공정전의 소정의 시점에 있어 상기 실리콘층을 단결정화 또는 적어도 약 10㎛이사이의 립경을 가지도록 다결정화 하게 하기 위해서의 열처리 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910006314A 1990-06-26 1991-04-19 반도체장치 및 그의 제조방법 KR950000866B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2-167282 1990-06-26
JP2167282A JPH0456325A (ja) 1990-06-26 1990-06-26 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
KR920001685A true KR920001685A (ko) 1992-01-30
KR950000866B1 KR950000866B1 (ko) 1995-02-02

Family

ID=15846863

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910006314A KR950000866B1 (ko) 1990-06-26 1991-04-19 반도체장치 및 그의 제조방법

Country Status (4)

Country Link
US (2) US5373192A (ko)
JP (1) JPH0456325A (ko)
KR (1) KR950000866B1 (ko)
DE (1) DE4119920C2 (ko)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3396286B2 (ja) * 1994-02-28 2003-04-14 三菱電機株式会社 半導体集積回路装置およびその製造方法
US5661081A (en) * 1994-09-30 1997-08-26 United Microelectronics Corporation Method of bonding an aluminum wire to an intergrated circuit bond pad
JP3421882B2 (ja) * 1994-10-19 2003-06-30 ソニー株式会社 多結晶半導体薄膜の作成方法
US5614764A (en) * 1995-01-13 1997-03-25 Intel Corporation Endcap reservoir to reduce electromigration
US5672913A (en) * 1995-02-23 1997-09-30 Lucent Technologies Inc. Semiconductor device having a layer of gallium amalgam on bump leads
KR0172851B1 (ko) * 1995-12-19 1999-03-30 문정환 반도체 장치의 배선방법
JP3234762B2 (ja) * 1996-02-26 2001-12-04 シャープ株式会社 半導体装置の製造方法
US6825132B1 (en) 1996-02-29 2004-11-30 Sanyo Electric Co., Ltd. Manufacturing method of semiconductor device including an insulation film on a conductive layer
JP3015752B2 (ja) * 1996-02-29 2000-03-06 三洋電機株式会社 半導体装置の製造方法
KR100383498B1 (ko) 1996-08-30 2003-08-19 산요 덴키 가부시키가이샤 반도체 장치 제조방법
US6310300B1 (en) * 1996-11-08 2001-10-30 International Business Machines Corporation Fluorine-free barrier layer between conductor and insulator for degradation prevention
US5943601A (en) * 1997-04-30 1999-08-24 International Business Machines Corporation Process for fabricating a metallization structure
US5891802A (en) * 1997-07-23 1999-04-06 Advanced Micro Devices, Inc. Method for fabricating a metallization stack structure to improve electromigration resistance and keep low resistivity of ULSI interconnects
US6690084B1 (en) 1997-09-26 2004-02-10 Sanyo Electric Co., Ltd. Semiconductor device including insulation film and fabrication method thereof
US6794283B2 (en) 1998-05-29 2004-09-21 Sanyo Electric Co., Ltd. Semiconductor device and fabrication method thereof
EP0991115A1 (en) 1998-09-28 2000-04-05 STMicroelectronics S.r.l. Process for the definition of openings in a dielectric layer
US20020076917A1 (en) * 1999-12-20 2002-06-20 Edward P Barth Dual damascene interconnect structure using low stress flourosilicate insulator with copper conductors
US6917110B2 (en) * 2001-12-07 2005-07-12 Sanyo Electric Co., Ltd. Semiconductor device comprising an interconnect structure with a modified low dielectric insulation layer
US6943105B2 (en) * 2002-01-18 2005-09-13 International Business Machines Corporation Soft metal conductor and method of making
ES2247219T3 (es) * 2002-05-10 2006-03-01 Siemens Aktiengesellschaft Procedimiento para la determinacion in situ del espesor de una capa.
US6682992B2 (en) * 2002-05-15 2004-01-27 International Business Machines Corporation Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicon structures
US7322543B2 (en) * 2005-08-10 2008-01-29 Philip Moores Party streamer dispenser
WO2011011764A2 (en) * 2009-07-23 2011-01-27 Gigasi Solar, Inc. Systems, methods and materials involving crystallization of substrates using a seed layer, as well as products produced by such processes
US8361890B2 (en) 2009-07-28 2013-01-29 Gigasi Solar, Inc. Systems, methods and materials including crystallization of substrates via sub-melt laser anneal, as well as products produced by such processes
WO2011020124A2 (en) * 2009-08-14 2011-02-17 Gigasi Solar, Inc. Backside only contact thin-film solar cells and devices, systems and methods of fabricating same, and products produced by processes thereof

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58202552A (ja) * 1982-05-21 1983-11-25 Toshiba Corp 単結晶Si−Al配線構造を有する半導体装置及びその製造法
US4639277A (en) * 1984-07-02 1987-01-27 Eastman Kodak Company Semiconductor material on a substrate, said substrate comprising, in order, a layer of organic polymer, a layer of metal or metal alloy and a layer of dielectric material
CA1239706A (en) * 1984-11-26 1988-07-26 Hisao Hayashi Method of forming a thin semiconductor film
US4744858A (en) * 1985-03-11 1988-05-17 Texas Instruments Incorporated Integrated circuit metallization with reduced electromigration
US4922320A (en) * 1985-03-11 1990-05-01 Texas Instruments Incorporated Integrated circuit metallization with reduced electromigration
JPS61208869A (ja) * 1985-03-14 1986-09-17 Nec Corp 半導体装置及びその製造方法
JPS6215819A (ja) * 1985-07-12 1987-01-24 Matsushita Electronics Corp 半導体装置
JPS6273711A (ja) * 1985-09-27 1987-04-04 Nec Corp 半導体装置
JPS62123716A (ja) * 1985-11-22 1987-06-05 Nec Corp 半導体装置の製造方法
JPS6437050A (en) * 1987-07-31 1989-02-07 Nec Corp Semiconductor device
JPS6437051A (en) * 1987-07-31 1989-02-07 Nec Corp Manufacture of semiconductor device
US4904611A (en) * 1987-09-18 1990-02-27 Xerox Corporation Formation of large grain polycrystalline films
JPH01238013A (ja) * 1988-03-18 1989-09-22 Citizen Watch Co Ltd 半導体集積回路の製造方法
JPH01268150A (ja) * 1988-04-20 1989-10-25 Yamaha Corp 半導体装置
US4837183A (en) * 1988-05-02 1989-06-06 Motorola Inc. Semiconductor device metallization process
JPH02186625A (ja) * 1989-01-13 1990-07-20 Fujitsu Ltd 半導体装置の製造方法
US4945070A (en) * 1989-01-24 1990-07-31 Harris Corporation Method of making cmos with shallow source and drain junctions
JPH0817180B2 (ja) * 1989-06-27 1996-02-21 株式会社東芝 半導体装置の製造方法
JPH0682631B2 (ja) * 1990-03-16 1994-10-19 株式会社東芝 半導体装置の製造方法

Also Published As

Publication number Publication date
KR950000866B1 (ko) 1995-02-02
DE4119920A1 (de) 1992-01-09
US5373192A (en) 1994-12-13
DE4119920C2 (de) 1996-04-25
JPH0456325A (ja) 1992-02-24
US5466638A (en) 1995-11-14

Similar Documents

Publication Publication Date Title
KR920001685A (ko) 반도체장치 및 그의 제조방법
KR880014657A (ko) 반도체장치의 제조방법
KR910005383A (ko) 반도체장치 및 그 제조방법
KR920005304A (ko) 반도체집적회로장치의 배선접속구조 및 그 제조방법
KR880013239A (ko) 반도체소자의 접속구멍형성 방법
KR980003732A (ko) 액정표시소자의 제조방법
KR840002162A (ko) 반도체 장치(半導體裝置)
KR900005602A (ko) 반도체장치 및 그 제조방법
KR900008658A (ko) 반도체 장치
KR920018849A (ko) 반도체장치 및 그의 제조방법
KR960005789A (ko) 반도체소자의 콘택홀 제조방법
KR920013728A (ko) 반도체 기억장치 및 그 제조방법
SE9504150D0 (sv) Förfarande vid tillverkning av en halvledaranordning
JPS57145340A (en) Manufacture of semiconductor device
KR970003479A (ko) 반도체 장치의 매복접촉 형성방법
KR870001655A (ko) 반도체장치의 제조방법
KR970053475A (ko) 반도체소자의 소자분리막 제조방법
KR920013629A (ko) 반도체장치
KR960043152A (ko) 반도체 소자의 캐패시터 및 그 제조방법
KR970052255A (ko) 반도체 소자의 콘택홀 매립 방법
KR970052836A (ko) 더미 배선을 갖춘 반도체 장치 및 그 제조 방법
KR930017090A (ko) 배선막구조 및 그 제조방법
JPS57160156A (en) Semiconductor device
KR940016735A (ko) 반도체 소자의 금속 배선 제조 방법
KR970003495A (ko) 반도체 소자 제조시 비아 콘택 방법

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 19980130

Year of fee payment: 4

LAPS Lapse due to unpaid annual fee