KR910019137A - 다결정 실리콘 접촉 구조 - Google Patents
다결정 실리콘 접촉 구조 Download PDFInfo
- Publication number
- KR910019137A KR910019137A KR1019910006936A KR910006936A KR910019137A KR 910019137 A KR910019137 A KR 910019137A KR 1019910006936 A KR1019910006936 A KR 1019910006936A KR 910006936 A KR910006936 A KR 910006936A KR 910019137 A KR910019137 A KR 910019137A
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- polycrystalline silicon
- contact
- conductivity type
- forming
- Prior art date
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims 15
- 229910021332 silicide Inorganic materials 0.000 claims 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims 7
- 239000004065 semiconductor Substances 0.000 claims 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/019—Contacts of silicides
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
- Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
- Y10T428/24926—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including ceramic, glass, porcelain or quartz layer
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 제3도는 본 발명에 따른 접촉을 형성하기 위한 바람직한 방법을 나타낸 도면.
Claims (10)
- 집적 회로 장치의 접촉 구조에 있어서, 제1전도 형태를 갖는 제1 다결정 실리콘 상호 접속 층과; 상기 제1다결정 실리콘 층 상의 규화물 층과; 상기 규화물 층의 상부 표면의 일부를 노출시키는 접촉구를 갖고, 상기 제1다결정 실리콘 층과 상기 규화물 층을 덮는 절연 층과; 제2전도 형태를 가지고, 상기 절연 층의 일부를 덮으며, 오옴 접촉이 형성되는 접촉구에서 상기 규화물 층을 접촉시키는 제2다결정 실리콘 상호 접속층으로 구성됨을 특징으로 하는 집적 회로 장치의 접촉 구조.
- 제1항에 있어서, 제1전도 형태는 N-형이고, 제2전도 형태는 P-형임을 특징으로 하는 집적 회로 장치의 접촉 구조.
- 제1항에 있어서, 제1전도 형태는 P-형이고, 제2전도 형태는 N-형임을 특징으로 하는 집적 회로 장치의 접촉 구조.
- 제1항에 있어서, 상기 제1 및 제2 전도 형태는 동일한 형태이고, 상기 제2 다결정 실리콘 층은 상기 제1 다결정 실리콘 층에 비해 약간 도핑됨을 특징으로 하는 집적 회로 장치의 접촉 구조.
- 제1항에 있어서, 상기 제2 다결정 실리콘 상호 접속 층은 접촉구에서 약간 도핑됨을 특징으로 하는 집적 회로 장치의 접촉 구조.
- 제5항에 있어서, 상기 제1 및 제2 전도 형태는 서로 상반되게 도핑되고, 접촉구로부터 분리된 제2 다결정 실리콘 층의 일부는 상기 제1전도 형태로 도핑되며, P-N 접합은 상기 제2 다결정 실리콘 층 내에서 형성됨을 특징으로 하는 집적 회로 장치의 접촉 구조.
- 반도체 집적 회로 장치의 접촉을 형성하는 방법에 있어서, 제1 전도 형태를 갖는 제1 다결정 실리콘 상호 접속 층을 형성하는 단계와; 상기 제1 다결정 실리콘 상호 접속 층 상에 규화물 층을 형성하는 단계와; 전체 장치에 걸져 절연 층을 형성하는 단계와; 규화물 층의 상부 표면상의 접촉 영역이 노출되며 접촉구를 절연 층에 형성하는 단계와; 접촉구를 통하여 규화물 층과 오움 접촉을 하며, 상기 절연 층에 걸쳐 제2 전도 형태를 갖는 제2 다결정 실리콘 상호 접속 층을 형성하는 단계로 구성됨을 특징으로 하는 반도체 집적 회로 장치의 접촉을 형성하는 방법.
- 제7항에 있어서, 상기 제1 및 제2 전도 형태들은 동일한 형태이고, 상기 제2 다결정 실리콘 상호 접속 층은 상기 제1 다결정 실리콘 상호 접속 층에 비해 약간 도핑됨을 특징으로 하는 반도체 집적 회로 장치의 접촉을 형성하는 방법
- 제7항에 있어서, 제1 및 제2 전도 형태는 서로 상반된 형태임을 특징으로 하는 반도체 집적 회로 장치의 접촉을 형성하는 방법
- 제9항에 있어서, 상기 방법은 상기 접촉구로부터 떨어져 있는 위치에 있으며 P-N 접합이 그안에 형성되는 상기 제2 다결정 실리콘 상호 접속층내에 상기 제1 전도 형태를 가지는 영역을 형성하는 단계를 또한 구성함을 특징으로 하는 반도체 집적 회로 장치의 접촉을 형성하는 방법※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US516,272 | 1990-04-30 | ||
US07/516,272 US5151387A (en) | 1990-04-30 | 1990-04-30 | Polycrystalline silicon contact structure |
Publications (1)
Publication Number | Publication Date |
---|---|
KR910019137A true KR910019137A (ko) | 1991-11-30 |
Family
ID=24054859
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019910006936A KR910019137A (ko) | 1990-04-30 | 1991-04-30 | 다결정 실리콘 접촉 구조 |
Country Status (5)
Country | Link |
---|---|
US (3) | US5151387A (ko) |
EP (1) | EP0455339B1 (ko) |
JP (1) | JP3064472B2 (ko) |
KR (1) | KR910019137A (ko) |
DE (1) | DE69130622T2 (ko) |
Families Citing this family (10)
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US5204279A (en) * | 1991-06-03 | 1993-04-20 | Sgs-Thomson Microelectronics, Inc. | Method of making SRAM cell and structure with polycrystalline p-channel load devices |
JPH06275724A (ja) * | 1993-01-22 | 1994-09-30 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
TW230266B (ko) * | 1993-01-26 | 1994-09-11 | American Telephone & Telegraph | |
US5432129A (en) * | 1993-04-29 | 1995-07-11 | Sgs-Thomson Microelectronics, Inc. | Method of forming low resistance contacts at the junction between regions having different conductivity types |
KR100477034B1 (ko) * | 1995-01-31 | 2005-03-21 | 가부시끼가이샤 히다치 세이사꾸쇼 | 반도체 메모리 장치 |
US5627103A (en) * | 1995-03-02 | 1997-05-06 | Sony Corporation | Method of thin film transistor formation with split polysilicon deposition |
US6406984B1 (en) | 1997-10-06 | 2002-06-18 | The United States Of America As Represented By The Secretary Of The Navy | Method of making improved electrical contact to porous silicon using intercalated conductive materials |
KR100379136B1 (ko) * | 1998-10-02 | 2003-04-08 | 인터내셔널 비지네스 머신즈 코포레이션 | 반도체 소자 형성 방법과 반도체 소자 |
US6214694B1 (en) * | 1998-11-17 | 2001-04-10 | International Business Machines Corporation | Process of making densely patterned silicon-on-insulator (SOI) region on a wafer |
US6429101B1 (en) | 1999-01-29 | 2002-08-06 | International Business Machines Corporation | Method of forming thermally stable polycrystal to single crystal electrical contact structure |
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-
1990
- 1990-04-30 US US07/516,272 patent/US5151387A/en not_active Ceased
-
1991
- 1991-03-25 EP EP91302575A patent/EP0455339B1/en not_active Expired - Lifetime
- 1991-03-25 DE DE69130622T patent/DE69130622T2/de not_active Expired - Fee Related
- 1991-04-25 JP JP3095055A patent/JP3064472B2/ja not_active Expired - Fee Related
- 1991-04-30 KR KR1019910006936A patent/KR910019137A/ko not_active Application Discontinuation
-
1992
- 1992-02-28 US US07/843,818 patent/US5279887A/en not_active Expired - Lifetime
-
1994
- 1994-09-29 US US08/316,035 patent/USRE37769E1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE69130622D1 (de) | 1999-01-28 |
DE69130622T2 (de) | 1999-05-06 |
EP0455339B1 (en) | 1998-12-16 |
USRE37769E1 (en) | 2002-06-25 |
JPH0737885A (ja) | 1995-02-07 |
EP0455339A3 (en) | 1992-06-03 |
JP3064472B2 (ja) | 2000-07-12 |
US5151387A (en) | 1992-09-29 |
US5279887A (en) | 1994-01-18 |
EP0455339A2 (en) | 1991-11-06 |
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