KR910017598A - 반도체 장치의 실장 구조 - Google Patents
반도체 장치의 실장 구조 Download PDFInfo
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- KR910017598A KR910017598A KR1019910004443A KR910004443A KR910017598A KR 910017598 A KR910017598 A KR 910017598A KR 1019910004443 A KR1019910004443 A KR 1019910004443A KR 910004443 A KR910004443 A KR 910004443A KR 910017598 A KR910017598 A KR 910017598A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/183—Connection portion, e.g. seal
- H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1도는 본 발명의 제 1 실시예를 도시하는 단면도, 제 2도는 동 실시예의 수지 봉지전의 평면도, 제 3도는 본 발명의 제 2 실시예를 도시하는 단면도.
Claims (8)
- 외부 회로 기판의 도전 패턴으로 감싸여진 비도전면에 칩 면적보다 큰부를 형성하여, 이부의 저면에 반도체 칩을 접착제로 접착하여, 이 반도체 칩의상 전극과 외부 회로 기판의 도전 패턴을 와이어로 접속하여, 상기한부내의 반도체 칩 및 그 주변의 도전 패턴의 일부를 봉지용수지로 봉지하여 형성되는 것을 특징으로 하는 반도체 장치의 실장구조.
- 제 1항에 있어서, 상기한부가 개미홈형상인 것을 특징으로 하는 반도체 장치의 실장구조.
- 외부 회로 기판의 비도전면의 칩 접착 영역 이외의 영역에부를 형성하여, 상기 칩 접착 영역에 반도체 칩을 접착제로 접착하여, 이 반도체 칩의상 전극과 외부 회로 기판의 도전 패턴을 와이어로 접속하여, 상기한 반도체 칩, 상기한부 및 그들의 주변의 도전 패턴의 일부를 봉지용수지로 봉지하여 형성되는 것을 특징으로 하는 반도체 장치의 실장구조.
- 제 3항에 있어서, 상기부가 개미홈형상인 것을 특징으로 하는 반도체 장치의 실장구조.
- 외부 회로 기판의 비도전면의 칩 접착 영역에 칩면적보다 큰부를 형성하여, 칩 접착 영역에도 부를 형성하여, 이 칩 접착 영역의부의 저면에 반도체 칩을 접착하여, 이 반도체 칩의 상 전극과 외부 회로 기판의 도전 패턴을 와이어로 접속하여, 상기 반도체 칩, 2개의부 및 그들의 주변의 패턴의 일부를 봉지용수지로 봉지하여 형성되는 것을 특징으로 하는 반도체 장치의 실장구조.
- 제 5항에 있어서, 상기한부가 개미홈형상인 것을 특징으로 하는 반도체 장치의 실장구조.
- 외부 회로 기판의 도전 패턴으로 감싸인 비도전면을 거친면으로 형성하여, 이 비도전면의 칩 접착 영역에 반도체 칩을 접착제로 접착시켜, 이 반도체 칩의상 전극과 외부 회로 기판의 도전 패턴을 와이어로 접속하여, 상기한 반도체 칩 및 그 주변의 도전 패턴이 일부를 봉지용수지로 봉지하여 형성되는 것을 특징으로 하는 반도체 장치의 실장구조.
- 외부 회로 기판의 도전 패턴으로 감싸인 비도전면에 칩면적보다 큰부를 형성하여, 상기 비도전면을 상기부 저면의 칩 부착면을 남겨 거친면으로 형성하여, 상기부 저면의 칩 부착면에 반도체 칩을 접착제로접착시켜, 이 반도체 칩의상 전극과 외부 회로 기판의 도전 패턴을 와이어로 접속하여, 상기부내의 반도체 칩 및 그 주변의 도전 패턴의 일부를 봉지용수지로 봉지하여 구성되는 것을 특징으로 하는 반도체 장치의 실장구조.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7867390A JP2890635B2 (ja) | 1990-03-29 | 1990-03-29 | 半導体装置 |
JP78673 | 1990-03-29 |
Publications (1)
Publication Number | Publication Date |
---|---|
KR910017598A true KR910017598A (ko) | 1991-11-05 |
Family
ID=13668386
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019910004443A KR910017598A (ko) | 1990-03-29 | 1991-03-21 | 반도체 장치의 실장 구조 |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP2890635B2 (ko) |
KR (1) | KR910017598A (ko) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001291792A (ja) * | 2000-04-06 | 2001-10-19 | Nec Corp | 半導体装置 |
JP4590961B2 (ja) * | 2004-07-20 | 2010-12-01 | 株式会社デンソー | 電子装置 |
JP2008192413A (ja) * | 2007-02-02 | 2008-08-21 | Nec Tokin Corp | 保護回路モジュール |
US8436461B2 (en) | 2010-05-21 | 2013-05-07 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device |
JP6261486B2 (ja) * | 2014-10-23 | 2018-01-17 | オリンパス株式会社 | 実装構造体、撮像モジュールおよび内視鏡装置 |
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1990
- 1990-03-29 JP JP7867390A patent/JP2890635B2/ja not_active Expired - Lifetime
-
1991
- 1991-03-21 KR KR1019910004443A patent/KR910017598A/ko not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
JPH03280452A (ja) | 1991-12-11 |
JP2890635B2 (ja) | 1999-05-17 |
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