KR900019040A - 다이나믹형 랜덤억세스메모리 - Google Patents

다이나믹형 랜덤억세스메모리 Download PDF

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Publication number
KR900019040A
KR900019040A KR1019900007092A KR900007092A KR900019040A KR 900019040 A KR900019040 A KR 900019040A KR 1019900007092 A KR1019900007092 A KR 1019900007092A KR 900007092 A KR900007092 A KR 900007092A KR 900019040 A KR900019040 A KR 900019040A
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KR
South Korea
Prior art keywords
bit line
potential
access memory
mos transistor
random access
Prior art date
Application number
KR1019900007092A
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English (en)
Inventor
다카시 오사와
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바 filed Critical 아오이 죠이치
Publication of KR900019040A publication Critical patent/KR900019040A/ko

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)

Abstract

내용 없음

Description

다이나믹형 랜덤억세스메모리
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 1실시예에 관한 DRAM의 일부를 나타낸 회로도.

Claims (5)

  1. 다이나믹형 메모리셀 어레이에서의 각 컬럼의 비트선쌍(BL,)과 비트선 센스앰프(NA)의 한쌍의 센스노오드의 사이에 각각 전하전송회로가 접속되어져 있고, 상기 비트선쌍을 소정의 타이밍에서 소정의 전압으로 선충 전하는 회로(PR)를 갖춘 다이나믹형 랜덤억세스메모리에 있어서, 상기 전하전송회로(NT1, NT2, PT1, PT2, S, D)는 비트선과 센스노오드의 두단자간의 전위차에 의해 임피던스가 변화함과 아울러 제3의 단자와 상기 두단자의 전위중 한쪽의 전위차에 의해 오프상태로 되는 소자가 비트선측 단자 및 비트선 센스앰프측 단자의 사이에 접속된 구성으로 되어 있고, 메모리셀의 신호가 비트선으로 독출된 다음에 상기 비트선 센스앰프가 활성화되며, 이 비트선 센스앰프의 동작후에 상기 전하전송회로가 오프상태로 제어되는 것을 특징으로 하는 다이나믹형 랜덤억세스메모리.
  2. 제1항에 있어서, 상기 전하전송회로로서 전계효과트랜지스터(NT1, NT2, PT1, PT2)를 이용하고, 이 전계효과트랜지스터의 게이트에 소정의 구동신호(øTj)를 공급하도록 된 것을 특징으로 하는 다이나믹형 랜덤억세스메모리.
  3. 제2항에 있어서, 상기 전계효과트랜지스터는 N챈널 MOS트랜지스터(NT1, NT2)이고, 이 MOS트랜지스터를 오프시킬 때에는 게이트에 주어지는 구동신호를 전원전위로부터 그 전원전위와 접지전위 사이의 중간전위(VM)로 떨어뜨리며, 이 MOS트랜지스터를 온시킬 때에는 게이트에 주어지는 구동신호를 전원전위(Vcc)로 올리는 것을 특징으로 하는 다이나믹형 랜덤억세스메모리.
  4. 제2항에 있어서, 상기 전계효과트랜지스터는 P챈널 MOS트랜지스터(PT1, PT2)이고, 이 MOS트랜지스터를 오프시킬 때에는 게이트에 주어지는 구동신호를 접지전위(Vss)로부터 그 접지전위와 전원전위 사이의 중간전위(VM)로 올리며, 이 MOS트랜지스터를 온 시킬 때에는 게이트에 주어지는 구동신호를 접지전위(Vss)로 떨어뜨리는 것을 특징으로 하는 다이나믹형 랜덤억세스메모리.
  5. 제1항에 있어서, 상기 전하전송회로로서 다이오드(D)와 스위치회로(S)를 병렬로 접속시켜 이용하고, 이 스위치회로를 스위칭 구동시키도록 된 것을 특징으로 하는 다이나믹형 랜덤억세스메모리.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900007092A 1989-05-15 1990-05-15 다이나믹형 랜덤억세스메모리 KR900019040A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1-121209 1989-05-15
JP1121209A JPH02301097A (ja) 1989-05-15 1989-05-15 ダイナミック型ランダムアクセスメモリ

Publications (1)

Publication Number Publication Date
KR900019040A true KR900019040A (ko) 1990-12-22

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Country Status (3)

Country Link
EP (1) EP0398244A3 (ko)
JP (1) JPH02301097A (ko)
KR (1) KR900019040A (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101036926B1 (ko) * 2009-12-30 2011-05-25 주식회사 하이닉스반도체 반도체 메모리 장치

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2523879B2 (ja) * 1989-06-16 1996-08-14 松下電器産業株式会社 センスアンプ回路
JPH0834257B2 (ja) * 1990-04-20 1996-03-29 株式会社東芝 半導体メモリセル
JPH07122989B2 (ja) * 1990-06-27 1995-12-25 株式会社東芝 半導体記憶装置
JP2564046B2 (ja) * 1991-02-13 1996-12-18 株式会社東芝 半導体記憶装置
JP2660111B2 (ja) * 1991-02-13 1997-10-08 株式会社東芝 半導体メモリセル
DE69222793T2 (de) * 1991-03-14 1998-03-12 Toshiba Kawasaki Kk Halbleiterspeicheranordnung
JP3181311B2 (ja) * 1991-05-29 2001-07-03 株式会社東芝 半導体記憶装置
US5283760A (en) * 1991-08-14 1994-02-01 Samsung Electronics Co., Ltd. Data transmission circuit
JP3464803B2 (ja) * 1991-11-27 2003-11-10 株式会社東芝 半導体メモリセル
EP0663666B1 (de) * 1994-01-12 1999-03-03 Siemens Aktiengesellschaft Integrierte Halbleiterspeicherschaltung und Verfahren zu ihrem Betrieb
US5684750A (en) * 1996-03-29 1997-11-04 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device with a sense amplifier including two types of amplifiers
JP2008077805A (ja) 2006-09-25 2008-04-03 Fujitsu Ltd 半導体記憶装置及びタイミング制御方法

Family Cites Families (4)

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Publication number Priority date Publication date Assignee Title
JPS5925311B2 (ja) * 1977-02-14 1984-06-16 日本電気株式会社 感知増幅器
DE2712735B1 (de) * 1977-03-23 1978-09-14 Ibm Deutschland Lese-/Schreibzugriffschaltung zu Speicherzellen eines Speichers und Verfahren zu ihrem Betrieb
JPS5472641A (en) * 1977-11-21 1979-06-11 Toshiba Corp Voltage detection circuit
JP2763772B2 (ja) * 1987-07-15 1998-06-11 オリンパス光学工業株式会社 コネクタ装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101036926B1 (ko) * 2009-12-30 2011-05-25 주식회사 하이닉스반도체 반도체 메모리 장치
US8213251B2 (en) 2009-12-30 2012-07-03 Hynix Semiconductor Inc. Semiconductor memory device and method for driving the same

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Publication number Publication date
JPH02301097A (ja) 1990-12-13
EP0398244A2 (en) 1990-11-22
EP0398244A3 (en) 1992-06-17

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