KR900005451A - 반도체메모리장치 - Google Patents
반도체메모리장치 Download PDFInfo
- Publication number
- KR900005451A KR900005451A KR1019890013279A KR890013279A KR900005451A KR 900005451 A KR900005451 A KR 900005451A KR 1019890013279 A KR1019890013279 A KR 1019890013279A KR 890013279 A KR890013279 A KR 890013279A KR 900005451 A KR900005451 A KR 900005451A
- Authority
- KR
- South Korea
- Prior art keywords
- memory
- row
- column
- columns
- address
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Databases & Information Systems (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
내용 없음.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제6도는 본 발명의 구성을 일반화시킨 경우의 반도체메모리장치의 회로구성도.
제7도는 제6도에 도시된 회로구성도중 셀어레이의 형태를 모식적으로 나타낸 설명도이다.
Claims (2)
- 복수의 메모리셀이 매트릭스형태로 배치되어 있으면서 행어드레스에 의해 상기 메모리셀중에서 행방향으로 배열된 메모리열이 선택되고 열어드레스에 의해 상기 메모리셀중에서 열방향으로 배열된 메모리열이 선택되어 그에 따라 상기 메모리셀이 선택되도록 된 반도체메모리장치에 있어서, 상기 하나의 열어드레스에 의해 선택되는 메모리열을 복수의 메모리열로 분할하는 복수메모리열선택수단(SSL)과, 선택된 복수의 메모리열중에서 하나의 메모리열을 선택하는 제1게이트수단(TRG1, TRG2)이 구비된 것을 특징으로 하는 반도체메모리장치.
- 복수의 메모리셀이 매트릭스형태로 배치되어 있으면서 행어드레스에 의해 상기 메모리셀중에서 행방향으로 배열된 메모리열이 선택되고 열어드레스에 의해 상기 메모리셀중에서 열방향으로 배열된 메모리열이 선택되어 그에 따라 상기 메모리셀이 선택되도록 된 반도체메모리장치에 있어서, 상기 하나의 열어드레스에 의해 선택된 메모리열을 복수의 메모리열로 분할하는 복수메모리열선택수단(WL1, WL2)과, 선택된 복수의 메모리열중에서 하나의 메모리열을 선택하는 제2게이트수단(전송게이트), 이 제2게이트수단에 의해 선택된 메모리셀의 데이터를 격납하고 출력하기 위해 상기 하나의 열어드레스에 의해 선택되는 상기 복수의 메모리열을 1조로 해서 각조마다 설치되는 레지스터수단(데이터레지스터)이 구비된 것을 특징으로 하는 반도체메모리장치.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63-229409 | 1988-09-13 | ||
JP88-229409 | 1988-09-13 | ||
JP63229409A JP2633645B2 (ja) | 1988-09-13 | 1988-09-13 | 半導体メモリ装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR900005451A true KR900005451A (ko) | 1990-04-14 |
KR920010822B1 KR920010822B1 (ko) | 1992-12-17 |
Family
ID=16891766
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019890013279A KR920010822B1 (ko) | 1988-09-13 | 1989-09-12 | 반도체메모리장치 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5051954A (ko) |
EP (1) | EP0359203B1 (ko) |
JP (1) | JP2633645B2 (ko) |
KR (1) | KR920010822B1 (ko) |
DE (1) | DE68923505T2 (ko) |
Families Citing this family (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07109703B2 (ja) * | 1989-11-15 | 1995-11-22 | 株式会社東芝 | 半導体メモリ装置 |
JP2575919B2 (ja) * | 1990-03-22 | 1997-01-29 | 株式会社東芝 | 半導体記憶装置の冗長回路 |
US5553032A (en) * | 1990-03-30 | 1996-09-03 | Fujitsu Limited | Dynamic random access memory wherein timing of completion of data reading is advanced |
JPH03283179A (ja) * | 1990-03-30 | 1991-12-13 | Fujitsu Ltd | 半導体記憶装置 |
US5594681A (en) * | 1990-03-30 | 1997-01-14 | Fujitsu Limited | Dynamic random access memory wherein timing of completion of data reading is advanced |
IL96808A (en) * | 1990-04-18 | 1996-03-31 | Rambus Inc | Introductory / Origin Circuit Agreed Using High-Performance Brokerage |
JPH0834257B2 (ja) * | 1990-04-20 | 1996-03-29 | 株式会社東芝 | 半導体メモリセル |
JP3179793B2 (ja) * | 1990-05-30 | 2001-06-25 | 三菱電機株式会社 | 半導体記憶装置およびその読出方法 |
JPH07122989B2 (ja) * | 1990-06-27 | 1995-12-25 | 株式会社東芝 | 半導体記憶装置 |
TW212852B (ko) * | 1990-09-20 | 1993-09-11 | Siemens Ag | |
JP2630059B2 (ja) * | 1990-11-09 | 1997-07-16 | 日本電気株式会社 | 半導体メモリ装置 |
JP2660111B2 (ja) * | 1991-02-13 | 1997-10-08 | 株式会社東芝 | 半導体メモリセル |
JP2564046B2 (ja) * | 1991-02-13 | 1996-12-18 | 株式会社東芝 | 半導体記憶装置 |
DE69222793T2 (de) * | 1991-03-14 | 1998-03-12 | Toshiba Kawasaki Kk | Halbleiterspeicheranordnung |
JP2928654B2 (ja) * | 1991-04-10 | 1999-08-03 | 株式会社東芝 | マルチポートdram |
JP3181311B2 (ja) * | 1991-05-29 | 2001-07-03 | 株式会社東芝 | 半導体記憶装置 |
KR940007640B1 (ko) * | 1991-07-31 | 1994-08-22 | 삼성전자 주식회사 | 공통 입출력선을 가지는 데이타 전송회로 |
JP3464803B2 (ja) * | 1991-11-27 | 2003-11-10 | 株式会社東芝 | 半導体メモリセル |
JPH05182458A (ja) * | 1991-12-26 | 1993-07-23 | Toshiba Corp | 半導体記憶装置 |
JPH08500687A (ja) | 1992-08-10 | 1996-01-23 | モノリシック・システム・テクノロジー・インコーポレイテッド | ウェハ規模の集積化のためのフォルトトレラントな高速度のバス装置及びバスインタフェース |
JP3279681B2 (ja) * | 1992-09-03 | 2002-04-30 | 株式会社日立製作所 | 半導体装置 |
JPH06302189A (ja) * | 1993-02-22 | 1994-10-28 | Toshiba Corp | 半導体記憶装置 |
US5384726A (en) * | 1993-03-18 | 1995-01-24 | Fujitsu Limited | Semiconductor memory device having a capability for controlled activation of sense amplifiers |
US5377150A (en) * | 1993-03-31 | 1994-12-27 | Sgs-Thomson Microelectronics, Inc. | Disabling sense amplifier |
JP3432548B2 (ja) * | 1993-07-26 | 2003-08-04 | 株式会社日立製作所 | 半導体記憶装置 |
US5742544A (en) | 1994-04-11 | 1998-04-21 | Mosaid Technologies Incorporated | Wide databus architecture |
US5655113A (en) * | 1994-07-05 | 1997-08-05 | Monolithic System Technology, Inc. | Resynchronization circuit for a memory system and method of operating same |
US5729501A (en) * | 1995-09-08 | 1998-03-17 | International Business Machines Corporation | High Speed SRAM with or-gate sense |
JP2783214B2 (ja) * | 1995-09-18 | 1998-08-06 | 日本電気株式会社 | 半導体メモリ装置 |
US6058065A (en) * | 1998-05-21 | 2000-05-02 | International Business Machines Corporation | Memory in a data processing system having improved performance and method therefor |
JP2002367364A (ja) * | 2001-06-06 | 2002-12-20 | Sanyo Electric Co Ltd | 磁気メモリ装置 |
US6760244B2 (en) * | 2002-01-30 | 2004-07-06 | Sanyo Electric Co., Ltd. | Magnetic memory device including storage elements exhibiting a ferromagnetic tunnel effect |
JP4278639B2 (ja) * | 2005-06-24 | 2009-06-17 | Okiセミコンダクタ株式会社 | シリアルアクセスメモリ |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4160275A (en) * | 1978-04-03 | 1979-07-03 | International Business Machines Corporation | Accessing arrangement for memories with small cells |
JPS5942399B2 (ja) * | 1979-12-21 | 1984-10-15 | 株式会社日立製作所 | メモリ装置 |
JPS5951074B2 (ja) * | 1980-03-28 | 1984-12-12 | 富士通株式会社 | 半導体記憶装置 |
JPS57198592A (en) * | 1981-05-29 | 1982-12-06 | Hitachi Ltd | Semiconductor memory device |
JPS581891A (ja) * | 1982-04-23 | 1983-01-07 | Hitachi Ltd | モノリシツク記憶装置 |
JPS5958689A (ja) * | 1982-09-28 | 1984-04-04 | Fujitsu Ltd | 半導体記憶装置 |
JPH069114B2 (ja) * | 1983-06-24 | 1994-02-02 | 株式会社東芝 | 半導体メモリ |
JPH0793009B2 (ja) * | 1984-12-13 | 1995-10-09 | 株式会社東芝 | 半導体記憶装置 |
JPS61229229A (ja) * | 1985-04-04 | 1986-10-13 | Canon Inc | 磁気記録媒体 |
JPS6289148A (ja) * | 1985-10-15 | 1987-04-23 | Mitsubishi Electric Corp | 2ポ−トメモリ |
JPS62287497A (ja) * | 1986-06-06 | 1987-12-14 | Fujitsu Ltd | 半導体記憶装置 |
-
1988
- 1988-09-13 JP JP63229409A patent/JP2633645B2/ja not_active Expired - Lifetime
-
1989
- 1989-09-11 US US07/406,420 patent/US5051954A/en not_active Expired - Lifetime
- 1989-09-12 KR KR1019890013279A patent/KR920010822B1/ko not_active IP Right Cessation
- 1989-09-12 DE DE68923505T patent/DE68923505T2/de not_active Expired - Fee Related
- 1989-09-12 EP EP89116871A patent/EP0359203B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
KR920010822B1 (ko) | 1992-12-17 |
DE68923505T2 (de) | 1996-02-01 |
JPH0276195A (ja) | 1990-03-15 |
EP0359203A3 (en) | 1992-02-26 |
EP0359203B1 (en) | 1995-07-19 |
EP0359203A2 (en) | 1990-03-21 |
US5051954A (en) | 1991-09-24 |
JP2633645B2 (ja) | 1997-07-23 |
DE68923505D1 (de) | 1995-08-24 |
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