KR890007434A - 반도체 장치 제조방법 - Google Patents

반도체 장치 제조방법 Download PDF

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Publication number
KR890007434A
KR890007434A KR1019880013487A KR880013487A KR890007434A KR 890007434 A KR890007434 A KR 890007434A KR 1019880013487 A KR1019880013487 A KR 1019880013487A KR 880013487 A KR880013487 A KR 880013487A KR 890007434 A KR890007434 A KR 890007434A
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South Korea
Prior art keywords
silicon
semiconductor
ion implantation
regions
exposed
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KR1019880013487A
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English (en)
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KR910009033B1 (ko
Inventor
페이겐슨 아나토리
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엘리 와이스
아메리칸 텔리폰 앤드 텔레그라프 캄파니
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Publication of KR890007434A publication Critical patent/KR890007434A/ko
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Publication of KR910009033B1 publication Critical patent/KR910009033B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/01—Bipolar transistors-ion implantation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Inorganic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

내용 없음

Description

반도체 장치 제조 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 제3도는 본 발명의 방법 및 장치의 제조 단계의 도시도.
* 도면의 주요부분에 대한 부호의 설명
1 : 실리콘 기판 3 : 에피텍셜층
5 : 매립층 21 : 폴리실리콘 영역

Claims (13)

  1. 반도체의 표면의 일부를 노출한 구멍을 형성하도록 반도체 기판상에 제1층(9,11)을 패턴하는 단계, 노출된 상기 표면의 일부를 가진 상기 구멍내에 측벽 스페이서(13)를 형성하는 단계, 측벽 스페이서에 의해 피복되지 않는 상기 표면의 일부상에 재질(15)을 생성하는 단계, 상기 스페이서 하부의 상기 반도체의 일부를 노출시키도록 상기 측벽 스페이서를 제거하는 단계 및, 상기 반도체의 상기 노출된 부분을 변형하는 단계로 이루어지는 것을 특징으로 하는 반도체 장치 제조 방법.
  2. 제1항에 있어서, 상기 노출된 부분은 실리콘으로 구성되는 것을 특징으로 하는 반도체 장치 제조 방법.
  3. 제2항에 있어서, 상기 제1층은 유전체로 구성되는 것을 특징으로 하는 반도체 장치 제조 방법.
  4. 제3항에 있어서, 상기 생성은 선택적인 화학적 증기 침전으로 이루어지는 것을 특징으로 하는 반도체 장치 제조 방법.
  5. 제4항에 있어서, 상기 생성물은 실리콘으로 이루어지는 것을 특징으로 하는 반도체 장치 제조 방법.
  6. 제5항에 있어서, 상기 실리콘 산화 단계를 포함하는 것을 특징으로 하는 반도체 장치 제조 방법.
  7. 제3항에 있어서, 상기 형성 단계는 실리콘 질화물을 침전하고 에칭하는 것을 특징으로 하는 반도체 장치 제조 방법.
  8. 제7항에 있어서, 상기 변형은 확산 또는 이온 이식으로 이루어지는 것을 특징으로 하는 반도체 장치 제조 방법.
  9. 제8항에 있어서, 상기 변형은 이온 이식을 포함하는 것을 특징으로 하는 반도체 장치 제조 방법.
  10. 제9항에 있어서, 상기 이온 이식은 대향 도전형의 두 영역을 형성하고, 상기 두 영역은 에미터 및 베이스 영역을 형성하는 것을 특징으로 하는 반도체 장치 제조 방법.
  11. 제6항에 있어서, 하부 재질의 일부를 노출하도록 상기 산화된 실리콘을 제거하고, 상기 노출부를 변형하는 단계를 포함하는 것을 특징으로 하는 반도체 장치 제조 방법.
  12. 제10항에 있어서, 상기 기판은 콜렉터 영역을 형성하는 것을 특징으로 하는 반도체 장치 제조 방법.
  13. 제12항에 있어서, 상기 에미터 베이스 및 콜렉터 영역에 대해 전기 접촉부를 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 장치 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880013487A 1987-10-20 1988-10-15 반도체 장치 제조 방법 KR910009033B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US111002 1987-10-20
US111,002 1987-10-20
US07/111,002 US4818713A (en) 1987-10-20 1987-10-20 Techniques useful in fabricating semiconductor devices having submicron features

Publications (2)

Publication Number Publication Date
KR890007434A true KR890007434A (ko) 1989-06-19
KR910009033B1 KR910009033B1 (ko) 1991-10-28

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Country Status (7)

Country Link
US (1) US4818713A (ko)
EP (1) EP0313250B1 (ko)
JP (1) JPH01124261A (ko)
KR (1) KR910009033B1 (ko)
CA (1) CA1299770C (ko)
DE (1) DE3886672T2 (ko)
ES (1) ES2047558T3 (ko)

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Also Published As

Publication number Publication date
EP0313250B1 (en) 1993-12-29
US4818713A (en) 1989-04-04
DE3886672D1 (de) 1994-02-10
KR910009033B1 (ko) 1991-10-28
DE3886672T2 (de) 1994-04-28
CA1299770C (en) 1992-04-28
ES2047558T3 (es) 1994-03-01
EP0313250A2 (en) 1989-04-26
EP0313250A3 (en) 1989-11-02
JPH01124261A (ja) 1989-05-17

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