KR870002750A - 실리콘의 플라즈마 에칭방법 - Google Patents

실리콘의 플라즈마 에칭방법 Download PDF

Info

Publication number
KR870002750A
KR870002750A KR1019860002536A KR860002536A KR870002750A KR 870002750 A KR870002750 A KR 870002750A KR 1019860002536 A KR1019860002536 A KR 1019860002536A KR 860002536 A KR860002536 A KR 860002536A KR 870002750 A KR870002750 A KR 870002750A
Authority
KR
South Korea
Prior art keywords
gas mixture
silicon
plasma
etching
chf
Prior art date
Application number
KR1019860002536A
Other languages
English (en)
Inventor
창 치-화
Original Assignee
에프. 토마스 듄랩, 쥬니어
인텔 코포레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 에프. 토마스 듄랩, 쥬니어, 인텔 코포레이션 filed Critical 에프. 토마스 듄랩, 쥬니어
Publication of KR870002750A publication Critical patent/KR870002750A/ko

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

내용 없음

Description

실리콘의 플라즈마 에칭방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명에 따른 포토리지스트막이 형성되어 있는 실리콘 기판의 정단면도.
제3도는 본 발명에 따른 제2도의 포토리지스트막에 골(opening)이 형성되어 있는 실리콘 기판의 정단면도.
제4도는 본 발명에 따른 제3도로부터 에칭되어진 실리콘 기판의 정단면도.
* 도면의 주요부분에 대한 부호의 설명
10 : 실리콘막 11 : 포토리지스트마스크
12 :오우버행(overhang) 13 : 에칭된 실리콘 표면
20 : 실리콘 기판 21 : 포토리지스트막
22 : 측면벽

Claims (8)

  1. 플라즈마기체 혼합물로 실리콘을 에칭하는 방법에 있어, 플라즈마기체 혼합물이 CHF3와 SF6으로 이루어지되, CHF3의 양이 SF6의 양보다 더 많이 첨가되어 이방성에칭으로 실시되어지는 것을 특징으로 하는 실리콘의 플라즈마 에칭방법.
  2. 제1항에 있어서, 플라즈마기체 혼합물에는 CHF3의 양이 SF6의 양보다 약 4배정도 더 많이 첨가되어서 이루어지는 것을 특징으로 하는 에칭방법.
  3. 제1항에 있어서, 플라즈마는 약 600와트의 RF전원에서 형성되어지는 것을 특징으로 하는 에칭방법.
  4. 플라즈마기체 혼합물로 실리콘을 에칭하는 방법에 있어서, 실리콘 표면에는 포토리지스트막을 피막시키고, 상기 포토리지스트막의 에칭하고자 하는 면에다 골을 형성시키며, SF6와 CHF3가 혼합된 기체혼합물을 실리콘상에 도입시키고, 상기 기체혼합물에 전기적 에너지를 부여하여 플들즈마가 형성되도록 한다음, 상기 플라즈마를 이용하여 에칭하고자 하는 깊이로 실리콘을 에칭시켜서, 이방성에칭이 이루어지도록 하는 것을 특징으로 하는 실리콘의 플라즈마 에칭방법.
  5. 제4항에 있어서, 기체혼합물은 CHF3약 80%와 SF6약 20%가 혼합되어서 이루어지는 것을 특징으로 하는 에칭방법.
  6. 제4항에 있어서, 전기적 에너지는 약 600와트의 전원으로 하여 이루어지는 것을 특징으로 하는 에칭방법.
  7. 제4항에 있어서, 기체혼합물은 약 125sccm의 유동율로 실리콘에 도입되어서 이루어지는 것을 특징으로 하는 에칭방법.
  8. 제4항에 있어서, 이방성에칭은 기체혼합물중 CHF3의 백분율에 의존하여 이루어지는 것을 특징으로 하는 에칭방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019860002536A 1985-08-23 1986-04-03 실리콘의 플라즈마 에칭방법 KR870002750A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US768875 1985-08-23
US06/768,875 US4666555A (en) 1985-08-23 1985-08-23 Plasma etching of silicon using fluorinated gas mixtures

Publications (1)

Publication Number Publication Date
KR870002750A true KR870002750A (ko) 1987-04-06

Family

ID=25083751

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860002536A KR870002750A (ko) 1985-08-23 1986-04-03 실리콘의 플라즈마 에칭방법

Country Status (5)

Country Link
US (1) US4666555A (ko)
JP (1) JPH0797577B2 (ko)
KR (1) KR870002750A (ko)
CN (1) CN1005882B (ko)
DE (1) DE3627311A1 (ko)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5180466A (en) * 1984-12-29 1993-01-19 Fujitsu Limited Process for dry etching a silicon nitride layer
DE3615519A1 (de) * 1986-05-07 1987-11-12 Siemens Ag Verfahren zum erzeugen von kontaktloechern mit abgeschraegten flanken in zwischenoxidschichten
US4904621A (en) * 1987-07-16 1990-02-27 Texas Instruments Incorporated Remote plasma generation process using a two-stage showerhead
JPS6432627A (en) * 1987-07-29 1989-02-02 Hitachi Ltd Low-temperature dry etching method
JPH0212915A (ja) * 1988-06-30 1990-01-17 Sharp Corp 窒化珪素絶縁膜の加工方法
IT1225636B (it) * 1988-12-15 1990-11-22 Sgs Thomson Microelectronics Metodo di scavo con profilo di fondo arrotondato per strutture di isolamento incassate nel silicio
JPH0383335A (ja) * 1989-08-28 1991-04-09 Hitachi Ltd エッチング方法
US5110411A (en) * 1990-04-27 1992-05-05 Micron Technology, Inc. Method of isotropically dry etching a poly/WSix sandwich structure
US5213659A (en) * 1990-06-20 1993-05-25 Micron Technology, Inc. Combination usage of noble gases for dry etching semiconductor wafers
US5284549A (en) * 1992-01-02 1994-02-08 International Business Machines Corporation Selective fluorocarbon-based RIE process utilizing a nitrogen additive
JP3215151B2 (ja) * 1992-03-04 2001-10-02 株式会社東芝 ドライエッチング方法
DE4317623C2 (de) * 1993-05-27 2003-08-21 Bosch Gmbh Robert Verfahren und Vorrichtung zum anisotropen Plasmaätzen von Substraten und dessen Verwendung
AU2683995A (en) * 1994-09-02 1996-03-27 Stichting Voor De Technische Wetenschappen Process for producing micromechanical structures by means of reactive ion etching
US6153501A (en) 1998-05-19 2000-11-28 Micron Technology, Inc. Method of reducing overetch during the formation of a semiconductor device
JP2953974B2 (ja) * 1995-02-03 1999-09-27 松下電子工業株式会社 半導体装置の製造方法
US6051501A (en) * 1996-10-09 2000-04-18 Micron Technology, Inc. Method of reducing overetch during the formation of a semiconductor device
US5866483A (en) * 1997-04-04 1999-02-02 Applied Materials, Inc. Method for anisotropically etching tungsten using SF6, CHF3, and N2
US6165375A (en) * 1997-09-23 2000-12-26 Cypress Semiconductor Corporation Plasma etching method
JP3067739B2 (ja) * 1998-06-30 2000-07-24 日本電気株式会社 エッチング方法
US6010966A (en) * 1998-08-07 2000-01-04 Applied Materials, Inc. Hydrocarbon gases for anisotropic etching of metal-containing layers
DE19844025A1 (de) * 1998-09-25 2000-03-30 Inst Oberflaechenmodifizierung Reaktives Ionen(strahl)ätzen von Oberflächen
US6312616B1 (en) 1998-12-03 2001-11-06 Applied Materials, Inc. Plasma etching of polysilicon using fluorinated gas mixtures
US6583063B1 (en) 1998-12-03 2003-06-24 Applied Materials, Inc. Plasma etching of silicon using fluorinated gas mixtures
US6235214B1 (en) 1998-12-03 2001-05-22 Applied Materials, Inc. Plasma etching of silicon using fluorinated gas mixtures
US6383938B2 (en) * 1999-04-21 2002-05-07 Alcatel Method of anisotropic etching of substrates
US6372634B1 (en) 1999-06-15 2002-04-16 Cypress Semiconductor Corp. Plasma etch chemistry and method of improving etch control
US6322716B1 (en) 1999-08-30 2001-11-27 Cypress Semiconductor Corp. Method for conditioning a plasma etch chamber
US6221784B1 (en) 1999-11-29 2001-04-24 Applied Materials Inc. Method and apparatus for sequentially etching a wafer using anisotropic and isotropic etching
US6391790B1 (en) 2000-05-22 2002-05-21 Applied Materials, Inc. Method and apparatus for etching photomasks
US7115523B2 (en) * 2000-05-22 2006-10-03 Applied Materials, Inc. Method and apparatus for etching photomasks
US7183201B2 (en) 2001-07-23 2007-02-27 Applied Materials, Inc. Selective etching of organosilicate films over silicon oxide stop etch layers
KR100810954B1 (ko) * 2001-11-08 2008-03-10 제온 코포레이션 플라즈마 반응용 가스, 그 제조방법 및 이용
EP1497849B1 (en) * 2002-04-17 2010-06-23 Lam Research Corporation Method of manufacturing a silicon electrode for plasma reaction chambers
US20040072081A1 (en) * 2002-05-14 2004-04-15 Coleman Thomas P. Methods for etching photolithographic reticles
AU2004261207B2 (en) * 2003-07-28 2011-02-17 Salter Labs, Llc Respiratory therapy system including a nasal cannula assembly
US8293430B2 (en) * 2005-01-27 2012-10-23 Applied Materials, Inc. Method for etching a molybdenum layer suitable for photomask fabrication
US8631799B2 (en) * 2008-01-25 2014-01-21 Salter Labs Respiratory therapy system including a nasal cannula assembly
JP5107842B2 (ja) * 2008-09-12 2012-12-26 東京エレクトロン株式会社 基板処理方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1260365A (en) * 1985-05-06 1989-09-26 Lee Chen Anisotropic silicon etching in fluorinated plasma
US4601782A (en) * 1985-06-20 1986-07-22 International Business Machines Corp. Reactive ion etching process

Also Published As

Publication number Publication date
DE3627311A1 (de) 1987-02-26
US4666555A (en) 1987-05-19
CN86103233A (zh) 1987-02-18
JPS6246526A (ja) 1987-02-28
CN1005882B (zh) 1989-11-22
JPH0797577B2 (ja) 1995-10-18

Similar Documents

Publication Publication Date Title
KR870002750A (ko) 실리콘의 플라즈마 에칭방법
KR940022724A (ko) 드라이에칭방법
KR930020591A (ko) 건식에칭방법
JPS5684476A (en) Etching method of gas plasma
KR930014829A (ko) 에칭방법
JPS5687666A (en) Plasma etching method
KR870006638A (ko) 드라이 에칭 방법
KR970008397A (ko) 식각용액 및 이를 이용한 반도체 장치의 식각방법
KR950021178A (ko) 반도체 장치의 제조 방법
JPS55164077A (en) Method for etching by gas plasma
KR970072162A (ko) 백금 박막의 건식 식각 방법
JPS5561027A (en) Gas plasma etching
KR970063553A (ko) 에치율을 향상시킨 이방성 에칭방법
JPS6417443A (en) Manufacture of semiconductor device
KR970077448A (ko) 반도체장치의 비어(via) 홀 형성방법
KR960039203A (ko) 반도체장치의 금속배선 형성방법
KR970052216A (ko) 반도체 소자의 콘택홀 형성방법
JPS5694759A (en) Wiring forming method
JPS57124443A (en) Forming method for electrode layer
KR970018357A (ko) 반도체장치의 트랜치 형성방법
JPS5534418A (en) Method of selectively etching semiconductor
JPS5548933A (en) Forming of mesa groove
KR970072170A (ko) 플라즈마에칭장치 및 플라즈마에칭방법
KR960019515A (ko) 콘택식각방법
JPS57210632A (en) Forming method for wiring pattern

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application