KR840003162A - 이득 제어 증폭기 - Google Patents

이득 제어 증폭기 Download PDF

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Publication number
KR840003162A
KR840003162A KR1019820005620A KR820005620A KR840003162A KR 840003162 A KR840003162 A KR 840003162A KR 1019820005620 A KR1019820005620 A KR 1019820005620A KR 820005620 A KR820005620 A KR 820005620A KR 840003162 A KR840003162 A KR 840003162A
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KR
South Korea
Prior art keywords
amplifier
terminal
transistor
input
phase period
Prior art date
Application number
KR1019820005620A
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English (en)
Inventor
레이놀드 사리 베이코
Original Assignee
오레그 이. 엘버
웨스턴 일렉트릭 캄파니, 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 오레그 이. 엘버, 웨스턴 일렉트릭 캄파니, 인코포레이티드 filed Critical 오레그 이. 엘버
Publication of KR840003162A publication Critical patent/KR840003162A/ko

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/20—Automatic control
    • H03G3/30—Automatic control in amplifiers having semiconductor devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/72—Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G1/00—Details of arrangements for controlling amplification
    • H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G1/00—Details of arrangements for controlling amplification
    • H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
    • H03G1/0035—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using continuously variable impedance elements
    • H03G1/007—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using continuously variable impedance elements using FET type devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G1/00—Details of arrangements for controlling amplification
    • H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
    • H03G1/0088—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using discontinuously variable devices, e.g. switch-operated

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Control Of Amplification And Gain Control (AREA)
  • Amplifiers (AREA)
  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)

Abstract

내용 없음

Description

이득 제어 증폭기
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 가변 상호 콘덕턴스 궤환 회로망에서 스위치 캐패시터를 갖는 이득 제어 증폭기의 회로 구성도.
제2도는 제1도의 증폭기의 궤환회로망에 사용될 수 있는 것과 같은 토글(toggle)스위치의 회로구성도.
제3도는 제1도의 증폭기에서 높은 진폭 입력 신호에 대하여 왜곡 억제 회로망을 갖는 회로 구성도.

Claims (6)

  1. 궤환 회로망에 인가된 제어 전압에 따라 이득이 변하는 이득 제어 증폭기에 있어서, 제1증폭기와, 제1증폭기의 출력 및 입력 사이에 접속된 부궤환 회로망과, 제어 신호에 따라 가변하는 궤환회로망의 상호 콘덕턴스와, 직렬로 접속된 제1 및 제2캐패시터를 포함하는 궤환 회로망과 제1위상 기간동안에는 제1증폭기의 입력에 그리고 제2위상 기간 동안에는 기준 전위단자에 제1패캐패시터의 한쪽 단자를 접속하기 위한 제1스위치 수단과, 제2위상 기간과 중첩되지 않은 제1위상 기간과, 제1위상 기간동안에는 제1 증폭기의 출력에 그리고 제2위상기간동안에는 기준 전위 단자에 제2캐패시터의 한쪽 단자를 접속하기 위한 제2스위치 장치 및 제어신호에 응답하며 제1 및 제2캐패시터에서 기준전위 단자로 적어도 하나의 전류통로를 제공하는 가변저항 수단을 포함하는 것을 특징으로 하는 이득 제어 증폭기.
  2. 제1항의 증폭기에 있어서, 가변저항 수단이 접속된 제1트랜지스터를 포함하여 공통마디와 기준전위 단자 사이에 동적 저항 통로를 제공하며, 제2트랜지스터가 제어신호에 따라 변하는 바이어스를 제1트랜지스터에 공급하는 것을 특징으로 하는 이득제어 증폭기.
  3. 제2항의 증폭기에 있어서, 상기 제1증폭기의 입력이 반전 입력이며, 이득 제어 증폭기에 입력신호에 응답하는 왜극 억제 회로망을 제공하며 고 입력 신호 렙레에서 출력 신호 파형 왜곡을 감소하는 제1트랜지스터의 제어 전극에 접속하고, 상기 억제 회로망이 반전입력 및 입력신호를 받아들이는 단자 사이에 접속된 제1 임피던스를 포함하며, 제2증폭기가 제2임피던스를 통하여 입력신호 단자에 접속된 반전 입력을 가지며, 비반전 입력이 기준전위 단자에 접속되며, 제3 및 제4캐패시터가 공통 마디를 형성하기 위해 한 단자가 서로 접속되며, 제3캐패시터의 다른쪽 단자가 제1 및 제2캐패시터의 공통 마디에 접속되며, 제4캐패시터의 다른쪽 단자가 제1트랜지스터의 제어전극에 접속되며, 제3스위치 수단이 제1트랜지스터의 제어 전극을 제1위상기간동안 제2증폭기의 출력에 접속하고 제2위상기간동안에는 기준 전위 단자에 접속하며, 제4스위치 수단이 제3 및 제4캐패시터의 공통 마디를 제1위상기간 동안에는 제2증폭기의 반전 입력에 접속하고 제2위상 기간동안에는 기준 전위 단자에 접속하며, 제5캐패시터가 제2증폭기의 반전입력 및 출력사이에 접속하는 것을 특징으로 하는 이득제어 증폭기.
  4. 제3항의 증폭기에서, 트랜지스터가 전계 효과 트랜지스터인 것을 특징으로 하는 이득 제어 증폭기.
  5. 제3 혹은 4항의 증폭기에서 트랜지스터가 MOS소자인 것을 특징으로 하는 이득제어 증폭기.
  6. 제1항의 증폭기에 있어서, 상기 제1증폭기의 입력이 반전입력이며, 제어신호에 응답하는 가변 저항 수단이 제공되며 제1 및 제2 캐패시터의 공통 마디에서 반전 입력에 전류통로가 제공된 것을 특징으로 하는 이득제어 증폭기.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019820005620A 1981-12-15 1982-12-15 이득 제어 증폭기 KR840003162A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US81-331,513 1981-12-15
US06/331,513 US4441080A (en) 1981-12-17 1981-12-17 Amplifier with controlled gain

Publications (1)

Publication Number Publication Date
KR840003162A true KR840003162A (ko) 1984-08-13

Family

ID=23294283

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019820005620A KR840003162A (ko) 1981-12-15 1982-12-15 이득 제어 증폭기

Country Status (10)

Country Link
US (1) US4441080A (ko)
JP (1) JPS58111416A (ko)
KR (1) KR840003162A (ko)
CA (1) CA1187567A (ko)
DE (1) DE3246213A1 (ko)
FR (1) FR2518849B1 (ko)
GB (1) GB2111776B (ko)
HK (1) HK7886A (ko)
IT (1) IT1154639B (ko)
NL (1) NL8204871A (ko)

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Also Published As

Publication number Publication date
FR2518849A1 (fr) 1983-06-24
DE3246213A1 (de) 1983-08-18
GB2111776A (en) 1983-07-06
IT1154639B (it) 1987-01-21
US4441080A (en) 1984-04-03
IT8224809A1 (it) 1984-06-16
NL8204871A (nl) 1983-07-18
CA1187567A (en) 1985-05-21
IT8224809A0 (it) 1982-12-16
FR2518849B1 (fr) 1986-03-21
GB2111776B (en) 1985-03-27
JPS58111416A (ja) 1983-07-02
HK7886A (en) 1986-02-07

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