KR20170025248A - Thin Film Transistor comprising double layer gate insulator and fabricating method thereof - Google Patents
Thin Film Transistor comprising double layer gate insulator and fabricating method thereof Download PDFInfo
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- KR20170025248A KR20170025248A KR1020150121445A KR20150121445A KR20170025248A KR 20170025248 A KR20170025248 A KR 20170025248A KR 1020150121445 A KR1020150121445 A KR 1020150121445A KR 20150121445 A KR20150121445 A KR 20150121445A KR 20170025248 A KR20170025248 A KR 20170025248A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13069—Thin film transistor [TFT]
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Abstract
Description
The present invention relates to a dual-layer gate-type thin film transistor for performing driving and switching operations and a method for manufacturing the same, and more particularly to a thin-film transistor including a high-quality double-layer gate insulating film having high mobility and a method for manufacturing the same.
Various demands for display devices have been increasing due to the development of information technology. Accordingly, various flat panel display devices such as a liquid crystal display (LCD), an organic light emitting diode (OLED), and a plasma display panel (PDP) have been studied. LCDs that replace CRTs (Cathode Ray Tube) are most commonly used for portable image display devices because of their excellent image quality, light weight, thinness, and low power consumption. In addition to their use in portable applications such as monitors for notebook computers, A television receiving and displaying a signal, a monitor of a computer, and the like.
Currently, amorphous silicon thin film transistors (a-Si TFTs, a-Si thin film transistors) are widely used as driving and switching devices for such displays. However, due to the trend toward larger and higher quality displays, - High performance TFTs with higher mobility than Si TFTs and manufacturing techniques are needed.
A polycrystalline silicon thin film transistor (poly-Si TFT) having a much higher performance than an a-Si TFT has high mobility and thus has an advantage that it can be applied to a high-resolution display which is difficult to realize in a conventional a-Si TFT. -Si TFT requires complicated process and high process temperature compared to a-Si TFT, and it is difficult to apply it to industry due to the additional cost.
Therefore, there is a demand for a new TFT technology having both advantages of a-Si TFT and advantages of poly-Si TFT. Research on this is proceeding actively, and a representative example thereof is a metal oxide thin film transistor. Metal oxide thin film transistors are attracting attention due to their high mobility, transparency to visible light, and low temperature processability compared with a-Si TFTs. However, gate insulating films such as silicon oxide require high temperature deposition above 300 DEG C using expensive vacuum based PECVD systems. Accordingly, recently, in place of silicon oxide, Al 2 O 3 , Y 2 O 3 , HfO 2 and ZrO 2 However, it also requires a high annealing temperature. As a result, the mechanical characteristics of the thin film are deteriorated and the gate leakage current is increased due to the tunneling phenomenon.
The applicant of the present application has proposed a method of fabricating a semiconductor device by introducing a double-layer gate insulating film having an upper insulating film including a lower gate insulating film including silicon oxide and an inorganic insulating material having a high dielectric constant and thereby improving the sub threshold gate swing, threshold voltage, Layer gate-type thin film transistor which can be easily applied to a flexible flexible substrate by providing a thin film transistor and forming a high-quality double-layer gate insulating film at a lower processing temperature.
It is an object of the present invention to provide a dual-layer gate-type thin film transistor having an improved sub-threshold gate swing, threshold voltage and current on / off ratio as well as high mobility by including a double- Method.
In order to attain the above object, a dual-layer gate-type thin film transistor according to the present invention is characterized in that the gate electrode is formed of indium (In), zinc (Zn), tin (Sn), aluminum (Al), magnesium (Mg), hafnium Ga) and titanium (Ti); A lower gate insulating film including silicon oxide disposed on one surface of the active layer and at least one selected from zinc (Zn), zirconium (Zr), hafnium (Hf), aluminum (Al), titanium (Ti), and lanthanum A bilayer gate insulating film having a top gate insulating film including a metal oxide and disposed on top of the bottom gate insulating film; A gate conductive film disposed on one surface of the double-layer gate insulating film and overlapping a part or all of the active layer; And source and drain electrodes disposed on both sides of the active layer. At this time, the lower gate insulating film and the upper gate insulating film of the double layer gate insulating film are each formed by annealing at 150 to 300 ° C.
In addition, the dual-layer gate-type thin film transistor indicator according to the present invention includes a first step of forming a lower gate insulating film by applying silicon oxide on a substrate and then annealing the substrate; And at least one metal oxide selected from zinc (Zn), zirconium (Zr), hafnium (Hf), aluminum (Al), titanium (Ti), and lanthanum (La) is applied to the upper portion of the lower insulating film, Forming a gate insulating film; and annealing the first and second steps (T 1 ) at a temperature of 150 to 300 ° C.
The thin film transistor according to the present invention includes a bilayer gate insulating film having a lower gate insulating film containing silicon oxide and an upper insulating film including an inorganic insulating material having a high dielectric constant. Thus, the thin film transistor has high charge mobility and thermal stability It can be remarkably improved.
In addition, it is possible to provide a thin film transistor having improved performance such as a subthreshold swing, a threshold voltage, and the like while minimizing a leakage current.
The present invention can manufacture a thin film transistor having a flexible and stable device characteristic by forming a double layer gate insulating film using a low temperature solution process at a temperature of 300 DEG C or less and improve the interfacial characteristics with the channel even at a lower process temperature, Has a threshold gate swing value, can easily adjust the formed thickness, and can reduce the leakage current.
1A is a cross-sectional view illustrating a double-layer gate-type thin film transistor of a top gate structure according to an embodiment of the present invention.
1B is a cross-sectional view illustrating a double-layer gate-type thin film transistor of a bottom gate structure according to an embodiment of the present invention.
2A shows a transfer curve of a single-layer gate type thin film transistor according to Comparative Example 1 of the present invention.
2B shows a transfer curve of a single-layer gate-type thin film transistor according to Comparative Example 2 of the present invention.
2C shows a transfer curve of the double-layer gate type thin film transistor according to the first embodiment of the present invention.
3A is an atomic force microscope (AFM) image of a single-layer gate insulating film according to Comparative Example 1 of the present invention.
3B is an atomic force microscope (AFM) image of a double-layer gate insulating film according to Example 1 of the present invention.
4 shows the leakage currents of the double-layer gate-type thin film transistor according to the first embodiment of the present invention and the single-layer gate-type thin film transistor according to the first and second comparative examples.
A thin film transistor including a dual-layer gate insulating film according to the present invention and a method of manufacturing the same will be described in detail below. Unless defined otherwise in the technical terms and scientific terms used herein, And a description of well-known functions and configurations that may unnecessarily obscure the gist of the present invention will be omitted in the following description.
It will also be appreciated that the terms "below," "above," "upper," "lower," "horizontal," or " Relative terms such as "a " are used herein to describe a relationship with one constituent member, layer or region with another constituent member, layer or region, as shown in the figures, But it is understood that other directions of the device are also encompassed.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" include singular forms unless the context clearly dictates otherwise.
The present invention is formed to have a laminated structure of an upper gate insulating film including an inorganic insulator on a lower gate insulating film containing silicon oxide, and can have high mobility and improved thermal stability, (Organic Luminescence Emitted Diode) that operates while flowing a current to the organic EL display device, thereby providing a highly reliable device.
In addition, the dual-layer gate insulating film according to the present invention can achieve desired device characteristics without performing a high-temperature deposition process or an additional heat treatment process, which must be accompanied by the conventional process for forming a high-quality gate insulating film. As described above, the double-layer gate insulating film according to the present invention can be processed at a low temperature, and thus it is possible to manufacture a thin film transistor having a flexible and stable device characteristic which has been difficult to apply due to the conventional high temperature process.
A dual-layer gate-type thin film transistor according to the present invention is a thin film transistor formed of indium (In), zinc (Zn), tin (Sn), aluminum (Al), magnesium (Mg), hafnium (Hf), gallium (Ga) An active layer comprising at least one metal oxide selected; A lower gate insulating film including silicon oxide disposed on one surface of the active layer and at least one selected from zinc (Zn), zirconium (Zr), hafnium (Hf), aluminum (Al), titanium (Ti), and lanthanum A bilayer gate insulating film having a top gate insulating film including a metal oxide and disposed on top of the bottom gate insulating film; A gate conductive film disposed on one surface of the double-layer gate insulating film and overlapping a part or all of the active layer; And source and drain electrodes disposed on both sides of the active layer. The lower gate insulating film and the upper gate insulating film are each annealed at a temperature of 150 to 300 ° C.
The dual-layer gate insulating film according to an embodiment of the present invention includes a lower
Preferably, the double-layered gate insulating film according to the present invention includes a lower
More preferably, the upper
The double layer gate insulating film according to one embodiment of the present invention can effectively improve the leakage current due to the tunneling phenomenon that can be easily generated in the gate insulating film formed of a single layer and thus can have remarkably improved electrical characteristics.
The double layer gate insulating film according to an embodiment of the present invention can be deposited at a high deposition rate even at a low temperature to form a uniform insulating film without cracks or tunneling having a high dielectric constant property and excellent strength and low moisture permeability , Which not only has an improved stability at a high temperature but also has a high lifetime characteristic.
The upper and lower gate
In addition, the upper
At this time, in order to optimize the characteristics of the double-layer gate insulating film according to the present invention, the lower gate insulating film may be in the range of 100 to 200 nm, and the upper gate insulating film may be in the range of 20 to 100 nm. The current can be remarkably reduced, and performance such as subthreshold swing, threshold voltage, and the like can be improved.
1A, an
A dual-layer gate-type thin film transistor 200 according to another aspect of the present invention includes a gate
The structure of the double-layer gate-type thin film transistors 100 and 200 shown in FIGS. 1A and 1B is illustrative, and the present invention is not limited thereto. For example, the double-layer gate-type thin film transistor according to the present invention may have a double-gate structure as well known in the art, and the source and
In the dual-layer gate-type thin film transistor according to another aspect of the present invention, Ti, Cr, W, Ta, and Mo are used to improve adhesion characteristics between the bilayer
The
The active layer according to an exemplary embodiment of the present invention can be formed at a low temperature of 200 ° C or lower and can have a device characteristic equal to or higher than the charge mobility obtained in a conventional poly-Si TFT using polycrystalline silicon .
The gate
The source and
The present invention relates to a method for manufacturing a semiconductor device, comprising: a first step of forming a lower gate insulating film by applying silicon oxide on a substrate and then annealing; And at least one metal oxide selected from zinc (Zn), zirconium (Zr), hafnium (Hf), aluminum (Al), titanium (Ti), and lanthanum (La) is applied to the upper portion of the lower insulating film, Forming a gate insulating film on the gate insulating film; and (2) forming a gate insulating film on the gate insulating film. In this case, the annealing temperature (T 1 ) in the first and second steps is in the range of 150 to 300 ° C.
As described above, the double-layer gate insulating film according to the present invention can be formed by a sputtering or atomic layer deposition process capable of a low-temperature deposition process at 300 ° C or less, and can be applied to a substrate such as a flexible plastic due to such characteristics . Particularly, when the present invention is applied to a flexible flexible substrate, a roll-to-roll process is possible, thereby enabling a large-area deposition process of a double-layer gate-type thin film transistor according to the present invention.
The annealing temperature (T 1 ) according to an embodiment of the present invention may preferably be a temperature in the range of 180 to 250 ° C to produce a bilayer gate insulating film having economically excellent insulating characteristics.
Also, the lower gate insulating film of the double-layer gate insulating film manufactured using the manufacturing method according to the present invention includes silicon oxide. In this case, when silicon nitride or the like having a relatively high dielectric constant relative to silicon oxide is used for the lower gate insulating film, a relatively high charge mobility can be realized, but the parasitic capacitance also increases relatively. As a result, Which is disadvantageous to high-speed driving.
That is, the double-layered gate insulating film according to the present invention is formed by forming a lower insulating film containing silicon oxide having a relatively low dielectric constant, and depositing zinc (Zn), zirconium (Zr), hafnium (Al), titanium (Ti), and lanthanum (La), the thermal stability and the oxidation stability are significantly improved, and when exposed to electrical or optical stress, Can be minimized. At this time, the upper gate insulating film of the bilayer gate insulating film may be selected from at least one metal oxide selected from zirconium (Zr), hafnium (Hf), titanium (Ti) and lanthanum (La) , A metal oxide mixed with zirconium (Zr) and lanthanum (La), but the present invention is not limited thereto. At this time, the zirconium and lanthanum are preferably mixed with 0.5 to 5 mol of lanternum to 1 mol of zirconium.
In the manufacturing method according to an embodiment of the present invention, the application of the first and second steps may be performed by a method selected from inkjet printing, dispensing, spin coating, nanoimprinting, gravure printing, offset printing, And may preferably be performed by jet printing, dispensing, spin coating or the like, more preferably by spin coating, but is not limited thereto.
In addition, in the manufacturing method according to the embodiment of the present invention, the substrate is not limited to the type of substrate that can be used in the art. For example, glass, quartz, sapphire, graphite, graphene, metals, metal oxides, metal carbides, metal nitrides, plastics and silicon wafers. The substrate may have a metal electrode layer formed on the surface of the substrate to improve conductivity. The metal electrode layer includes a metal having conductivity, and examples of the metal electrode layer include, but are not limited to, metals having conductivity, and examples thereof include Mo, W, Bi, Mg, Al, Si, Ca, Sc, Ba, La, Hf, Ta, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Sr, Y, Zr, Nb, Tc, Ru, Rh, Pd, Ag, Cd, In Sn, Sb, , Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Po, and the like. In order to obtain excellent conductivity and low haze value, molybdenum A metal electrode layer including at least one selected from the group consisting of Al, Mo, Pt, Al, Ir, Ru, RuO 2 , But is not limited thereto.
Hereinafter, the present invention will be described in more detail based on the following examples. However, the following examples are illustrative of the present invention but are not limited thereto.
Coated on a silicon wafer (5 cm x 5 cm) with a solution of perhydropolysilazane (1.90 M) (10 ml) at 3000 rpm for 30 seconds and pre-baked at 150 ° C for 5 minutes. Thereafter, H 2 O steam annealing was performed at 180 ° C for 1 hour to form a lower gate insulating film (SiO 2 Thin film) was formed. Zirconium chloride and lanthanum nitrate hexahydrate were spin-coated on the lower gate insulating film at 3000 rpm for 30 seconds using a 0.15 M ZrLaO solution in ethanol at a ratio of 2: 1, And pre-baked for 5 minutes. Thereafter, annealing was performed at 180 DEG C for 1 hour to form an upper gate insulating film (ZrLaO Thin film) was formed to form a bilayer gate insulating film. IZO (Indium Tin Oxide) semiconductor channels were deposited on the upper gate insulating film by sputtering in an Ar atmosphere at 100 W DC power and 2 mTorr pressure, and ITO (Indium Tin Oxide) S / Time heat treatment to fabricate a double layer gate type thin film transistor.
The transfer curve of the dual-layer gate-type thin-film transistor manufactured by the above-described method is measured and shown in FIG. 2C. The transfer characteristics of the double-layer gate-type thin-film transistor are shown in Table 1 below.
In addition, FIG. 3B shows an atomic force microscope (AFM) in order to confirm the state where the double layer gate insulating film manufactured by the above manufacturing method is bonded onto the substrate.
In Example 1, a bilayer gate type thin film transistor was fabricated under the same conditions except that the annealing temperature of the upper gate insulating film was 250 캜.
In Example 1, a double-layer gate-type thin film transistor was fabricated under the same conditions except that the annealing temperature of the upper gate insulating film was 300 ° C.
(Comparative Example 1)
Coated on a silicon wafer (5 cm x 5 cm) with a solution of perhydropolysilazane (1.90 M) (10 ml) at 3000 rpm for 30 seconds and pre-baked at 150 ° C for 5 minutes. Thereafter, H 2 O steam annealing was performed at 180 ° C for 1 hour to form a gate insulating film (SiO 2 Thin film) was formed. The SiO 2 thin film was used as a single-layer gate insulating film, and an ITO electrode was stacked on the single-layer gate insulating film to form a capacitor. An IZO (Indium Zinc Oxide) semiconductor channel was deposited on the single-layer gate insulating film using a sputtering method, and an ITO (Indium Tin Oxide) S / D electrode was deposited on the single-layer gate insulating film, followed by heat treatment at 180 ° C for 1 hour to fabricate a single- .
The transfer curve of the single-layer gate-type thin-film transistor manufactured by the above-described manufacturing method is measured and shown in FIG. 2A, and its migration characteristics are shown in Table 1 below.
Further, FIG. 3A shows an atomic force microscope (AFM) in order to confirm the state where the single-layer gate insulating film manufactured by the above manufacturing method is bonded onto the substrate.
(Comparative Example 2)
Zirconium chloride and lanthanum nitrate hexahydrate were dissolved in ethanol at a ratio of 2: 1 to a silicon wafer (5 cm × 5 cm) to prepare a 0.15 M ZrLaO 3 solution. The ZrLaO 3 solution was spin-coated at 3000 rpm for 30 seconds and pre-baked at 100 ° C for 5 minutes. Thereafter, annealing was performed at 180 캜 for 1 hour to form a gate insulating film (ZrLaO Thin film) was formed. The ZrLaO thin film was used as a single-layer gate insulating film, and an ITO electrode was stacked on the single-layer gate insulating film to form a capacitor. An IZO (Indium Zinc Oxide) semiconductor channel was deposited on the single-layer gate insulating film using a sputtering method, and an ITO (Indium Tin Oxide) S / D electrode was deposited on the single-layer gate insulating film, followed by heat treatment at 180 ° C for 1 hour to fabricate a single- .
The transfer curve of the single-layer gate-type thin film transistor manufactured by the above-described manufacturing method is measured and shown in FIG. 2B.
As shown in FIGS. 2A to 2C, the dual-layer gate-type thin-film transistor of Example 1 according to the present invention has an off-state drain current Is about 10 3 to 10 7 times lower than that of the other. In addition, the double-layer gate-type thin-film transistor of Example 1 has a low off-state drain current of about 10 7 times that of the single-layer gate-type thin-film transistor of Comparative Example 2, It can be seen that the characteristics of the Ion / off ratio of the device can be remarkably improved.
The following Table 1 shows the results of confirming the electrical characteristics of Examples 1 to 3 and Comparative Examples 1 and 2. The mobility (μ FE ), the subthreshold gate swing (SS), the threshold voltage (V th ), and the ratio of Ion / off (I on / off ratio) were measured as the transfer characteristics of the thin film transistor.
As shown in Table 1, the double-layered gate-type thin-film transistor of the embodiment of the present invention improved the current flickering ratio by 10 times or more and the sub-threshold gate swing was 0.16 , 0.19, and 0.23 V / decade, respectively. In addition, the mobility of the single-layer gate thin film transistor of Comparative Example 1 was found to be higher than 100 by the increase of the gate leakage current and the hygroscopicity of the SiO 2 thin film.
Uniformities of the insulating films prepared in Examples 1 to 3 and Comparative Examples 1 and 2 of the present invention were visually evaluated. As a result, unlike Examples 1 to 3, which were uniformly deposited without defects, 2, cracks or tunneled cracks were identified.
Further, it was confirmed that the double layer gate type thin film transistor according to the embodiment of the present invention has a threshold voltage reduced by about 5 times as compared with the single layer gate type thin film transistor of Comparative Example 1. As shown in FIG. 4, Layer gate-type thin-film transistor is superior to the single-layer gate-type thin-film transistor of FIG. 2 by about 10 times (absolute value of leakage current: 1 V). It is considered that a pinhole or the like existing when forming an insulator with a single layer serves as a leakage current path. However, when an insulator is formed by a double layer, even if such a pinhole is formed, This is because it is possible to effectively suppress this effect.
Accordingly, it can be seen that the characteristics of the double layer gate type thin film transistor according to the present invention are remarkably improved as compared with the single layer gate type thin film transistor including the SiO 2 or ZrLaO gate insulating layer.
The present invention relates to a dual-layer gate-type thin film transistor, and more particularly, to a double-layer gate-type thin film transistor having a gate insulating film, a gate insulating film, a gate insulating film, Lower gate insulating film, 13b: upper gate insulating film, 14b:
Claims (12)
A lower gate insulating film including silicon oxide disposed on one surface of the active layer and at least one selected from zinc (Zn), zirconium (Zr), hafnium (Hf), aluminum (Al), titanium (Ti), and lanthanum A bilayer gate insulating film having a top gate insulating film including a metal oxide and disposed on top of the bottom gate insulating film;
A gate conductive film disposed on one surface of the double-layer gate insulating film and overlapping a part or all of the active layer; And
Wherein the lower gate insulating film and the upper gate insulating film are annealed at a temperature in the range of 150 to 300 占 폚.
Wherein the lower gate insulating film comprises silicon oxide and the upper gate insulating film comprises at least one metal oxide selected from zirconium (Zr), hafnium (Hf), and lanthanum (La).
Wherein the lower gate insulating film and the sub gate insulating film have a thickness of 20 nm to 200 nm, respectively.
Wherein the thin film transistor has a lower gate structure in which the gate double layer insulating film and the active layer are sequentially formed on the gate conductive film.
Wherein the thin film transistor has a top gate structure in which the gate double layer insulating film and the gate conductive film are sequentially formed on the active layer.
Wherein at least one of the source and drain electrodes comprises a transparent conductive oxide thin film.
Wherein the transparent conductive oxide thin film comprises at least one selected from indium-zinc-oxide, indium-tin-oxide, tin fluoride, indium oxide and tin oxide.
At least one metal oxide selected from zinc (Zn), zirconium (Zr), hafnium (Hf), aluminum (Al), titanium (Ti), and lanthanum (La) is applied on the lower insulating film, Wherein the annealing temperature (T 1 ) in the first and second steps satisfies the following condition: < EMI ID = 1.0 >
150 ° C? T 1 ? 300 ° C
Wherein the annealing temperature (T 1 ) is in the range of 180 to 250 ° C.
Wherein the lower gate insulating film comprises silicon oxide and the upper gate insulating film comprises at least one metal oxide selected from zirconium (Zr), hafnium (Hf), and lanthanum (La) Way.
Wherein the application of the first and second steps is performed by a method selected from inkjet printing, dispensing, spin coating, nanoimprinting, gravure printing, and offset printing.
Wherein the substrate is selected from glass, metal, metal oxide, plastic, and silicon wafers.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113594183A (en) * | 2021-07-27 | 2021-11-02 | 上海大学 | Three-dimensional double-active-layer oxide thin film transistor and application thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113594183A (en) * | 2021-07-27 | 2021-11-02 | 上海大学 | Three-dimensional double-active-layer oxide thin film transistor and application thereof |
| CN113594183B (en) * | 2021-07-27 | 2023-09-22 | 上海大学 | Three-dimensional double-active-layer oxide thin film transistor and application thereof |
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