CN118039702A - Top gate Schottky oxide thin film transistor and preparation method thereof - Google Patents

Top gate Schottky oxide thin film transistor and preparation method thereof Download PDF

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Publication number
CN118039702A
CN118039702A CN202311656748.2A CN202311656748A CN118039702A CN 118039702 A CN118039702 A CN 118039702A CN 202311656748 A CN202311656748 A CN 202311656748A CN 118039702 A CN118039702 A CN 118039702A
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source
active region
drain
layer
forming
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张盛东
张羽晴
陆磊
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Peking University Shenzhen Graduate School
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Peking University Shenzhen Graduate School
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention relates to a top gate Schottky oxide thin film transistor, comprising: a substrate; a source electrode and a drain electrode disposed on the substrate; an active region including a first portion disposed on the substrate between the source and drain electrodes, the active region further including a second portion connected to the first portion overlying and directly contacting top surfaces of the source and drain electrode portions, the active region forming a schottky contact with the source and drain electrodes; an insulating layer disposed on the source, drain and active regions; and a gate electrode disposed over the insulating layer. The invention also relates to a preparation method of the top gate Schottky oxide thin film transistor.

Description

Top gate Schottky oxide thin film transistor and preparation method thereof
Technical Field
The invention relates to a thin film transistor and a preparation method thereof, in particular to a top gate Schottky oxide thin film transistor and a preparation method thereof.
Background
With the continuous development of electronic information technology, a display is taken as the most important way for information display and man-machine interaction, and long-standing development and progress are also obtained. For both LCD and OLED displays, the performance of Thin Film Transistors (TFTs) as important driving and switching elements in active displays greatly affects the brightness, speed, contrast, etc. of the display. Conventional amorphous silicon (a-Si) TFTs have failed to meet the requirements for high resolution, high frame rate display due to their low mobility, while polysilicon (poly-Si) TFTs have failed to meet the requirements for large size display due to the presence of grain boundaries. At present, the metal oxide TFT which is widely focused and researched has the advantages of high visible light transmittance, low process temperature, low process cost, compatibility with the current production line process and the like besides better uniformity of a-Si and higher carrier mobility of poly-Si, so that the metal oxide TFT is hopefully applied to the next-generation transparent flexible display technology with large size, high frame frequency and high resolution.
Conventional oxide TFTs generally have output characteristics that are not strictly saturated, and a large saturation voltage, which makes their applications limited. The gain of the analog part is not high, as in the case of manufacturing the drive circuit. When used as a display pixel circuit such as an AMOLED, the unsaturated output characteristic makes compensation accuracy not high, and a higher saturation voltage makes power consumption larger.
Disclosure of Invention
Aiming at the technical problems in the prior art, the invention provides a top gate Schottky oxide thin film transistor, which comprises: a substrate; a source electrode and a drain electrode disposed on the substrate; an active region including a first portion disposed on the substrate between the source and drain electrodes, the active region further including a second portion connected to the first portion covering top surfaces of the source and drain electrode portions, the active region forming a schottky contact with the source and drain electrodes; an insulating layer disposed on the source, drain and active regions; and a gate electrode disposed over the insulating layer.
In particular, the transistor further includes a protective layer disposed over the active region and under the insulating layer.
In particular, the transistor further comprises a buffer layer or a light shielding layer disposed between the substrate and the source, drain and the substrate and the active region.
In particular, the transistor wherein the work function of the material forming the source and drain electrodes is greater than the work function of the active layer.
In particular, the transistor, wherein the size of the overlapping portion between the active region and the source or drain is 0.1 μm to 10 μm, and/or the size of the overlapping portion between the gate electrode and the source or drain is 0.1 μm to 10 μm.
In particular, the transistor wherein the thickness of the active region is 10nm to 200nm and/or the thickness of the source (drain) electrode is 10nm to 400nm and/or the thickness of the gate electrode is 10nm to 500nm.
The invention also provides a preparation method of the top gate Schottky oxide thin film transistor, which comprises the following steps: forming a first conductive layer on a substrate and patterning the first conductive layer to form a source electrode and a drain electrode electrically isolated from each other; forming an active layer on the substrate and on the source and drain electrodes, and patterning the active layer to form an active region between and covering a portion of the source and drain electrodes; forming an insulating layer at least over the active region, source electrode and drain electrode; and forming a second conductive layer over the insulating layer, and patterning the second conductive layer to form a gate electrode over at least the active region between the source and drain electrodes.
In particular, the method further comprises forming contact holes in the insulating layer over the areas of the source and drain electrodes not covered by the active region, and forming electrical contacts in the contact holes to electrically connect the source and drain electrodes.
In particular, the method further comprises forming a protective layer over the active region prior to forming the insulating layer and prior to patterning the active layer; patterning the protective layer to leave a portion located above the active layer between the source and drain electrodes and a portion covering a portion of the source and drain electrodes; and patterning the active layer to remove portions not covered by the protective layer, thereby forming the active region.
In particular, the method further comprises depositing a buffer layer or a light shielding layer on the substrate prior to forming the first conductive layer.
Drawings
Preferred embodiments of the present invention will be described in further detail below with reference to the attached drawing figures, wherein:
fig. 1 is a schematic diagram of a top gate schottky oxide thin film transistor structure according to one embodiment of the present invention;
fig. 2A-2I are schematic flow diagrams of a process for fabricating a top gate schottky oxide thin film transistor according to one embodiment of the present invention;
fig. 3 is a flow chart of a method of fabricating a top gate schottky oxide thin film transistor according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments of the application. In the drawings, like reference numerals describe substantially similar components throughout the different views. Various specific embodiments of the application are described in sufficient detail below to enable those skilled in the art to practice the teachings of the application. It is to be understood that other embodiments may be utilized or structural, logical, or electrical changes may be made to embodiments of the present application.
It is found that the output impedance of the metal oxide TFT can be effectively improved, the saturation voltage is reduced, and the device has the characteristics of high stress stability, easy miniaturization and the like by converting the contact part of the active region and the conductive electrodes of the source region and the drain region from ohmic contact to Schottky contact.
The schottky oxide TFT currently studied generally adopts a bottom gate overlap structure, i.e., an active region is deposited after a gate is formed and then conductive electrodes of source and drain regions are formed on the active region. In the process of sputtering and growing the conductive electrodes of the source region and the drain region, a large amount of oxygen vacancies are generated on the surface of the active region due to the bombardment effect of plasma on the active region, so that an effective and stable Schottky barrier is difficult to form at the contact part of the active region and the conductive electrodes of the source region and the drain region. In order to overcome the above problems and obtain a schottky oxide TFT with high gain, low power consumption and stable performance, there is a need for a method of effectively forming a schottky barrier at the contact portion of the active region with the conductive electrodes of the source and drain regions.
The invention provides a top gate Schottky oxide thin film transistor. Compared with the traditional device, the device has the characteristics of high output impedance, low saturation voltage, high stress stability, easy miniaturization, good heat resistance and the like. Importantly, because the active region of the top gate Schottky transistor is formed after the source electrode and the drain electrode are formed, the defect of the contact surface is reduced, and therefore the contact part of the active region and the conductive electrodes of the source region and the drain region can form an effective and stable Schottky barrier.
Fig. 1 is a schematic diagram of a top gate schottky oxide thin film transistor structure according to one embodiment of the present invention. As shown, a top gate schottky oxide thin film transistor 100 may include a substrate 101. According to one embodiment, the substrate 101 material may comprise glass, silicon wafer, or a flexible material. The flexible material may be polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyimide (PI), flexible glass, or the like.
As shown in fig. 1, a source electrode 102 and a drain electrode 103 electrically isolated from each other may be provided on a substrate 101. According to one embodiment, the source 102 and drain 103 may comprise a single layer or multiple layers of metal. In some embodiments, the source 102 and drain 103 may include a metal having a work function greater than that of the active region 104, such as platinum, nickel, gold, palladium, iridium, rhodium, or the like. In some embodiments, for the case of metal oxide semiconductors (e.g., IGZO) as the active region, the source drain electrode may be selected from metals with a work function greater than 4.8eV to form a good schottky contact.
According to one embodiment, the thickness of the source 102 and drain 103 may be 10nm to 400nm, and may be, for example, 40nm. The above data and materials are exemplary choices, and are more advantageous for the design of the process, which is a preferred embodiment. However, the scheme of the invention is not limited thereto. In some embodiments, the source and drain electrodes have positions that are symmetrical to each other, and thus can be interchanged.
According to one embodiment, the distance between the source 102 and the drain 103 may be 5 μm.
As shown in fig. 1, the transistor 100 may further include an active region 104 between the source 102 and the drain 103. According to one embodiment, the material of the active region 104 may be a metal oxide semiconductor material. In some embodiments, the middle portion of the active region 104 may be in direct contact with the substrate 101, and the area of the portion thereof in contact with the substrate 101 is defined by two protrusions formed of the source electrode 102 and the drain electrode 103. According to one embodiment, the active region 104 further includes portions having both ends in direct contact with the top surfaces of the source electrode 102 and the drain electrode 103, wherein the portions in direct contact with the top surfaces of the source electrode 102 and the drain electrode 103 and the portions in direct contact with the substrate 101 are connected to each other to constitute the active region 104, as shown in fig. 1. The active region, the source electrode and the drain electrode of the structure are contacted on the side face and the top face, and compared with the Schottky contact area of the traditional structure, the Schottky contact area of the traditional structure is larger, so that the heating region is more dispersed, and the heat resistance is better.
In some embodiments, the active region 104 may include a single metal oxide, such as zinc oxide (ZnO), indium oxide (In 2O3), tin oxide (SnO 2), gallium oxide (Ga 2O3), etc., or may include a multiple metal oxide, such as Indium Gallium Zinc Oxide (IGZO), indium Zinc Oxide (IZO), zinc Tin Oxide (ZTO), hafnium Indium Zinc Oxide (HIZO), or Indium Tin Zinc Oxide (ITZO), etc. According to one embodiment, the active region 104 may be 40nm thick. The above data and materials are exemplary choices, and are more advantageous for the design of the process, which is a preferred embodiment. However, the scheme of the invention is not limited thereto.
In some embodiments, the source 102, drain 103, and active region 104 may be comprised of other materials. The materials for the source 102, drain 103 and active region 104 are selected so long as good schottky contact between the active region 104 and the source 102 and drain 103 is ensured. In general, in order to enable schottky contact that generates a rectifying action between a semiconductor and a metal, it is necessary to satisfy the condition: the difference between the work function of the active region semiconductor and the work function of the metal of the source-drain electrode is not less than 0.2-0.3 eV.
Because the active region 104 forms schottky contact with the source electrode 102 and the drain electrode 103, compared with the conventional ohmic contact structure, the active region has the advantages of effectively improving the output impedance of the TFT, reducing the saturation voltage, along with high stress stability, easy miniaturization and the like. And also effectively reduces leakage current of transistor 100 due to the unidirectional conductivity of the schottky contact.
In some embodiments, the active region 104 may be a dual active layer of oxide semiconductor with high and low oxygen content. Such a double layer structure can form a good schottky contact with the source electrode 102 and the drain electrode 103.
According to one embodiment, the size of the portion of the active region 104 overlapping the top surface of the source electrode 102 or the drain electrode 103 may be 2 μm.
In some embodiments, transistor 100 may optionally further include a protective layer 109. A protective layer 109 may be disposed on the active region 104. According to one embodiment, the material of the protective layer 109 may be at least one or more of silicon oxide, silicon nitride, a high-k dielectric material, and an organic dielectric material, and the thickness thereof may be 10nm to 400nm, for example, 100nm. The above data and materials are exemplary choices, and are more advantageous for the design of the process, which is a preferred embodiment. However, the scheme of the invention is not limited thereto.
According to one embodiment, the protective layer 109 may completely cover the entire active region 104 to reduce the influence of water, oxygen, photoresist, etc. on the active region 104 during the active region patterning process, thereby further improving the stability of the transistor. The protective layer 109 is an alternative structure and in some embodiments the protective layer 109 may not be included in the structure of the transistor 100.
As shown in fig. 1, the transistor 100 may further include an insulating layer 105 overlying the substrate 101, the source 102, the drain 103, and the protective layer 109 (over the active region 104 if no protective layer is present in the structure).
According to one embodiment, the insulating layer 105 may be a stacked structure including the same dielectric material obtained by changing growth conditions of temperature, gas ratio, power, and the like. According to one embodiment, the material of the insulating layer 105 may be at least one of silicon oxide, silicon nitride, a high-permittivity dielectric material, and an organic dielectric material, and the thickness of the insulating layer 105 may be 5nm to 400nm, for example, 200nm. The laminated structure of the same dielectric material obtained by adopting different growth conditions such as temperature, gas proportion, power and the like has greatly improved insulativity compared with a dielectric material structure with single property. The above data and materials are exemplary choices, and are more advantageous for the design of the process, which is a preferred embodiment. However, the scheme of the invention is not limited thereto.
Transistor 100 may also include electrical contact 107 and electrical contact 108. The electrical contacts 107 and 108 are electrically connected to the source 102 and the drain 103, respectively, through contact holes, thereby achieving the purpose of applying a voltage to the source and the drain. The material of the electrical contacts 107 and 108 may include at least one of a metal, a conductive metal oxide, or other conductive material.
As shown in fig. 1, transistor 100 may also include a gate electrode 106. A gate electrode 106 is disposed on the insulating layer 105 over the active region 104 between the source electrode 102 and the drain electrode 103. According to one embodiment, the material of the gate electrode 106 may include at least one of a metal, a conductive metal oxide, or other conductive material. According to one embodiment, the thickness of the gate electrode 106 may be 50nm to 400nm, for example 150nm.
The schottky transistor 100 described in the embodiments of the present application has a top gate structure, and the area of the gate covered in the active region is larger than that of the conventional bottom gate schottky transistor structure, so that the schottky transistor has better voltage resistance.
In some embodiments, the transistor 100 may further include a buffer layer or a light shielding layer (not shown in the figures). The buffer layer may be disposed between the substrate and other structures besides the substrate. The material of the buffer layer may be at least one of silicon oxide, silicon nitride, a high dielectric constant dielectric material, and an organic dielectric material, wherein the high dielectric constant dielectric material may include aluminum oxide, hafnium oxide, zirconium oxide, and the like.
The light shielding layer may be disposed between the substrate and other structures than the substrate, and the material of the light shielding layer may be at least one of a metal such as aluminum, titanium, copper, molybdenum, or tantalum, a non-metal such as a-Si, and an organic material. The buffer layer or the light shielding layer may have a thickness of 5nm to 400nm. The above data and materials are exemplary choices, and are more advantageous for the design of the process, which is a preferred embodiment. However, the scheme of the invention is not limited thereto. The presence of the buffer layer facilitates the growth of other structures on transistor 100. Under the condition that the substrate is made of transparent materials, the shading layer is additionally arranged to shade the influence of light rays taken in from the direction of the substrate on the active area, so that the stability of the device is improved.
As will be appreciated by those skilled in the art, the above description is merely illustrative of the structure of a top gate schottky oxide thin film transistor. There are many other structures or modifications, variations, or alternatives to these structures that provide different characteristics or functions. These structures and modifications, variations or modifications thereof are also applicable to the aspects of the present invention under the technical concept of the present invention.
The invention also provides a manufacturing method of the top gate Schottky oxide thin film transistor. Fig. 2A-2I are schematic process flow diagrams of a top gate schottky oxide thin film transistor fabricated according to an embodiment of the present invention. In this embodiment, silicon may be used as the substrate, the source and drain materials may be platinum (Pt), the active region material may be Indium Gallium Zinc (IGZO), and the source and drain electrodes and the gate electrode may be molybdenum (Mo) for example. As will be appreciated by those skilled in the art, other materials and processes meeting the above conditions may also achieve similar structures.
As shown in fig. 2A-2I, a fabrication process 200 of a top gate schottky oxide thin film transistor may include:
As shown in fig. 2A, a first conductive layer 233 is formed over a substrate 201.
According to one embodiment, the first conductive layer 233 (e.g., metallic Pt) may be deposited on the substrate 201 by direct current magnetron sputtering or other means.
As shown in fig. 2B, the first conductive layer 233 is patterned to form two source/drain electrodes 202 and 203 electrically isolated from each other. According to one embodiment, the distance between the source/drain electrodes 202 and 203 may be 5 μm.
In some embodiments, the source/drain electrode material may employ a single or multiple layers of metal material having a work function of 4.8eV or more, such as platinum, nickel, gold, palladium, iridium, rhodium, or the like.
As shown in fig. 2C, an active region film 231 is formed on the substrate 201, the source electrode 202, and the drain electrode 203.
According to one embodiment, an Indium Gallium Zinc Oxide (IGZO) active region film 231 may be deposited on the substrate 201, the source electrode 202, and the drain electrode 203 using a direct current magnetron sputtering method. In some embodiments, the active region film 231 may be a bilayer structure of the same material obtained by changing growth conditions of temperature, gas ratio, power, and the like. The active region thus formed can form a good schottky contact with the source 202 and drain 203. However, the above data and materials are merely exemplary choices, and are more advantageous for the design of the process, which is a preferred embodiment.
In the conventional process, the active region is often formed first and then the source/drain electrode is formed, so that during the process of forming the source/drain electrode, a large amount of oxygen vacancies are generated on the surface of the active region due to the bombardment effect of plasma on the active region, so that an effective and stable schottky barrier is difficult to form at the contact part of the active region and the source/drain electrode, and finally ohmic contact is formed at the contact part of the active region and the source/drain electrode. The invention adopts the top gate overlapped structure, namely, the mode of forming the source/drain electrode and then depositing the active region, so that the active region is prevented from being bombarded by plasma in the growth process of the source/drain electrode, and the active region and the source/drain electrode form good Schottky contact.
Alternatively, as shown in fig. 2D, a protective layer film 232 is formed on the active region film 231.
According to one embodiment, a protective layer film 232, such as SiO 2, may be deposited on the IGZO active zone film 231 using, for example, a plasma chemical vapor deposition (PECVD) method. In some embodiments, the process of manufacturing the top gate schottky oxide thin film transistor may not be included, so that it may be possible to operate without forming the protective layer.
As shown in fig. 2E, the active region film 231 is patterned.
According to one embodiment, photoresist is spin coated on the SiO 2 protective layer film 232. After photolithography, a portion of the protective layer film 232 over the source and drain electrodes and only over the active region and the substrate may be etched first using a Reactive Ion Etching (RIE) method using a reticle, thereby forming a patterned protective layer 209. The active region film 231 may then be patterned using a dilute hydrochloric acid (HCl) solution etch using a reticle, etching away portions not covered by the protective layer 209, thereby forming the active region 204, and exposing portions of the source and drain top surfaces.
According to one embodiment, the same reticle may be used when patterning the active region film 231 and the protective layer film 232. The protective layer 209 can reduce the influence of water, oxygen, photoresist, etc. on the active region 204 during the patterning of the active region 204, thereby further improving the stability of the transistor.
As shown in fig. 2F, an insulating layer 205 is formed over the substrate 201, the source 202, the drain 203, and the active region 204.
According to one embodiment, a PECVD process is used to deposit an insulating layer 205 over the substrate 201, source 202, drain 203 and active region 204. In some embodiments, the insulating layer 205 may be at least one of silicon oxide, silicon nitride, a high-k dielectric material, and an organic dielectric material, including a stacked structure of the same dielectric material obtained by changing growth conditions such as temperature, gas ratio, power, and the like. In some embodiments, the insulating layer 205 may be grown by methods including plasma enhanced chemical vapor deposition, atomic layer deposition, magnetron sputtering, reactive sputtering, or spin coating.
As shown in fig. 2G, a gate electrode 206 is formed over the insulating layer 205.
According to one embodiment, a conductive layer, such as metallic molybdenum (Mo), is deposited by dc magnetron sputtering over the active region 204 between the source and drain electrodes on the insulating layer 205. Then, the gate electrode 206 is formed after photolithography and etching. In some embodiments, the material of the gate electrode 206 may include at least one of a metal, a conductive metal oxide, or other conductive material.
As shown in fig. 2H, contact holes for the source electrode 202, the drain electrode 203 are formed in portions of the insulating layer 205 that are in direct contact with the top surfaces of the source electrode and the drain electrode.
As shown in fig. 2I, electrical contacts 207 and 208 are formed in the contact holes on the source 202 and drain 203, respectively.
According to one embodiment, a conductive layer, such as metallic molybdenum (Mo), is deposited over insulating layer 205, gate electrode 206, source 202, and drain 203 using dc magnetron sputtering. Then, a source electrical contact 207 and a drain electrical contact 208 are formed after photolithography and etching. In some embodiments, the material of the source electrical contact 207 and the drain electrical contact 208 may include at least one of a metal, a conductive metal oxide, or other conductive material.
In some embodiments, a buffer layer or a light shielding layer may optionally be deposited on the substrate 201 prior to the process steps shown in fig. 2A. The buffer layer or shading layer deposition method adopts plasma enhanced chemical vapor deposition, magnetron sputtering or reactive sputtering, atomic layer deposition or spin coating technology and the like. The material of the buffer layer may be at least one of silicon oxide, silicon nitride, a high dielectric constant dielectric material, and an organic dielectric material, wherein the high dielectric constant dielectric material may include aluminum oxide, hafnium oxide, zirconium oxide, and the like. The material of the light shielding layer may be at least one of a metal such as aluminum, titanium, copper, molybdenum, tantalum, or the like, a non-metal such as a-Si, and an organic material. The buffer layer or the light shielding layer may have a thickness of 5nm to 400nm. The presence of the buffer layer facilitates the growth of other structures on the transistor. Under the condition that the substrate is made of transparent materials, the shading layer is additionally arranged to shade the influence of light rays taken in from the direction of the substrate on the active area, so that the stability of the device is improved.
In some embodiments, an annealing process may optionally be added after the step shown in fig. 2F. The annealing atmosphere may be oxygen, nitrogen, air, compressed air, or other gases, and the annealing temperature may be 150-500 ℃. The annealing treatment may further enhance the insulation and mechanical strength of the insulating layer 205.
Fig. 3 is a flow chart of a method of fabricating a top gate schottky oxide thin film transistor according to an embodiment of the present invention.
Step 301: a first conductive layer is formed on the substrate and patterned to form a source and a drain electrically isolated from each other.
Step 302: an active layer is formed on the substrate, the source electrode and the drain electrode.
Step 303: a protective layer is formed over the active region.
Step 304: the protective layer and the active layer are patterned to form a protective layer and an active region between and covering a portion of the source and drain electrodes.
Step 305: an insulating layer is formed over at least the protective layer, the active region, the source electrode, and the drain electrode.
Step 306: a second conductive layer is formed over the insulating layer, and a gate electrode is patterned over the second conductive layer over at least the active region between the source and drain electrodes.
Step 307: a contact hole is formed in the insulating layer over a region of the source and drain electrodes not covered by the active region, and an electrical contact is formed in the contact hole to electrically connect the source and drain electrodes.
In some embodiments, optionally, a buffer layer or a light shielding layer may be deposited on the substrate prior to step 301.
In the conventional process, the active region is often formed first and then the source/drain electrode is formed, so that during the process of forming the source/drain electrode, a large amount of oxygen vacancies are generated on the surface of the active region due to the bombardment effect of plasma on the active region, so that an effective and stable schottky barrier is difficult to form at the contact part of the active region and the source/drain electrode, and finally ohmic contact is formed at the contact part of the active region and the source/drain electrode. The invention adopts the top gate overlapped structure, namely, the mode of forming the source/drain electrode and then depositing the active region, so that the active region is prevented from being bombarded by plasma in the growth process of the source/drain electrode, and the active region and the source/drain electrode form good Schottky contact. The top gate Schottky oxide thin film transistor structure and the preparation method thereof can effectively reduce the saturation voltage of the device and improve the output impedance and the stability under stress such as bias, illumination, high temperature and the like.
The above embodiments are provided for illustrating the present invention and not for limiting the present invention, and various changes and modifications may be made by one skilled in the relevant art without departing from the scope of the present invention, therefore, all equivalent technical solutions shall fall within the scope of the present disclosure.

Claims (10)

1. A top gate schottky oxide thin film transistor comprising:
A substrate;
A source electrode and a drain electrode disposed on the substrate;
An active region including a first portion disposed on the substrate between the source and drain electrodes, the active region further including a second portion connected to the first portion overlying and directly contacting top surfaces of the source and drain electrode portions, the active region forming a schottky contact with the source and drain electrodes;
an insulating layer disposed on the source, drain and active regions; and
And a gate electrode disposed over the insulating layer.
2. The transistor of claim 1, further comprising a protective layer disposed over the active region and under the insulating layer.
3. The transistor of claim 1, further comprising a buffer layer and/or a light shielding layer disposed between the substrate and source, drain, and the substrate and the active region.
4. The transistor of claim 1, wherein a work function of a material forming the source and drain is greater than a work function of the active layer.
5. The transistor according to claim 1, wherein a size of an overlapping portion between the active region and the source or drain is 0.1 μm to 10 μm, and/or a size of an overlapping portion between the gate electrode and the source or drain is 0.1 μm to 10 μm.
6. The transistor according to claim 1, wherein a thickness of the active region is 10nm to 200nm, and/or a thickness of the source/drain is 10nm to 400nm, and/or a thickness of the gate electrode is 10nm to 500nm.
7. A preparation method of a top gate Schottky oxide thin film transistor comprises the following steps:
forming a first conductive layer on a substrate and patterning the first conductive layer to form a source electrode and a drain electrode electrically isolated from each other;
forming an active layer on the substrate and on the source and drain electrodes, and patterning the active layer to form an active region between the source and drain electrodes and overlying and directly contacting a portion of the source and drain electrodes, the active region forming a schottky contact with the source and drain electrodes;
forming an insulating layer at least over the active region, source electrode and drain electrode; and
A second conductive layer is formed over the insulating layer and patterned to form a gate electrode over at least the active region between the source and drain electrodes.
8. The method of claim 7, further comprising forming contact holes in an insulating layer over regions of the source and drain electrodes not covered by the active region, and forming electrical contacts in the contact holes to electrically connect the source and drain electrodes.
9. The method of claim 7, further comprising forming a protective layer over the active region prior to forming the insulating layer and prior to patterning the active layer;
Patterning the protective layer to leave a portion located above the active layer between the source and drain electrodes and a portion covering a portion of the source and drain electrodes; and
Patterning the active layer to remove portions not covered by the protective layer, thereby forming the active region.
10. The method of claim 7, further comprising forming a buffer layer and/or a light shielding layer on the substrate prior to forming the first conductive layer.
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