KR20060039613A - 플립 칩 조립 구조를 가지는 칩-온-보드 패키지 및 그제조 방법 - Google Patents
플립 칩 조립 구조를 가지는 칩-온-보드 패키지 및 그제조 방법 Download PDFInfo
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- KR20060039613A KR20060039613A KR20040088783A KR20040088783A KR20060039613A KR 20060039613 A KR20060039613 A KR 20060039613A KR 20040088783 A KR20040088783 A KR 20040088783A KR 20040088783 A KR20040088783 A KR 20040088783A KR 20060039613 A KR20060039613 A KR 20060039613A
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- Prior art keywords
- chip
- insulating film
- metal
- board package
- integrated circuit
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 239000002184 metal Substances 0.000 claims abstract description 117
- 229910052751 metal Inorganic materials 0.000 claims abstract description 117
- 238000000034 method Methods 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 8
- 239000010931 gold Substances 0.000 claims description 6
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- 230000001070 adhesive effect Effects 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000004593 Epoxy Substances 0.000 claims description 3
- 239000004642 Polyimide Substances 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 2
- 238000000465 moulding Methods 0.000 description 9
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
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- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
Claims (13)
- 제1 표면과, 상기 제1 표면에 반대되는 제2 표면과, 내부에 형성된 관통 구멍을 가지는 절연성 필름;상기 절연성 필름의 상기 제1 표면에 형성되고, 상기 관통 구멍을 통하여 부분적으로 노출되는 금속 패턴;활성면을 가지며, 상기 활성면이 상기 절연성 필름을 향하도록 상기 절연성 필름의 상기 제2 표면에 배치되는 집적회로 칩; 및상기 집적회로 칩의 상기 활성면에 형성되며, 상기 절연성 필름의 상기 관통 구멍을 통하여 상기 금속 패턴과 물리적으로 접합되고 전기적으로 연결되는 금속 범프를 포함하는 칩-온-보드 패키지.
- 제1 항에 있어서,상기 금속 범프는 상기 절연성 필름의 두께보다 큰 높이를 가지는 것을 특징으로 하는 칩-온-보드 패키지.
- 제2 항에 있어서,상기 금속 범프의 높이는 약 40㎛이고, 상기 절연성 필름의 두께는 약 10㎛ 내지 20㎛인 것을 특징으로 하는 칩-온-보드 패키지.
- 제1 항에 있어서,상기 금속 범프의 소재는 금인 것을 특징으로 하는 칩-온-보드 패키지.
- 제1 항에 있어서,상기 절연성 필름의 소재는 에폭시 또는 폴리이미드인 것을 특징으로 하는 칩-온-보드 패키지.
- 제1 항에 있어서,상기 금속 범프의 폭은 약 20㎛인 것을 특징으로 하는 칩-온-보드 패키지.
- 제1 항에 있어서,상기 관통 구멍의 직경은 약 1㎜인 것을 특징으로 하는 칩-온-보드 패키지.
- 제1 표면과, 상기 제1 표면에 반대되는 제2 표면을 가지는 절연성 필름의 내부에 관통 구멍을 형성하는 단계;상기 절연성 필름의 상기 제1 표면에, 상기 관통 구멍을 통하여 부분적으로 노출되도록 금속 패턴을 형성하는 단계;집적회로 칩의 활성면에 금속 범프를 형성하는 단계; 및상기 활성면이 상기 절연성 필름을 향하도록 상기 절연성 필름의 상기 제2 표면에 상기 집적회로 칩을 배치하고, 상기 관통 구멍을 통하여 상기 금속 범프와 상기 금속 패턴을 물리적으로 접합되고 전기적으로 연결하는 단계를 포함하는 칩-온-보드 패키지의 제조 방법.
- 제8 항에 있어서,상기 관통 구멍의 형성 단계는 펀치를 이용하여 이루어지는 것을 특징으로 하는 칩-온-보드 패키지의 제조 방법.
- 제8 항에 있어서,상기 금속 패턴의 형성 단계는 상기 절연성 필름의 상기 제1 표면 전체에 금속판을 부착하는 단계와, 상기 금속판을 원하는 형태로 사진 식각하는 단계를 포함하는 것을 특징으로 하는 칩-온-보드 패키지의 제조 방법.
- 제8 항에 있어서,상기 금속 범프의 형성 단계는 전해도금 또는 스터드 범핑을 이용하여 이루어지는 것을 특징으로 하는 칩-온-보드 패키지의 제조 방법.
- 제8 항에 있어서,상기 금속 범프와 상기 금속 패턴의 접합 단계는 상기 집적회로 칩의 상기 활성면과 상기 절연성 필름의 상기 제2 표면 사이에 비도전성 접착제를 개재하여 접합하는 단계를 포함하는 것을 특징으로 하는 칩-온-보드 패키지의 제조 방법.
- 제1 항 내지 제7 항 중의 어느 한 항에 기재된 칩-온-보드 패키지를 카드 본체의 내부에 장착하고, 상기 칩-온-보드 패키지의 상기 금속 패턴을 접촉 단자로 사용하는 것을 특징으로 하는 집적회로 카드.
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KR20040088783A KR100610144B1 (ko) | 2004-11-03 | 2004-11-03 | 플립 칩 조립 구조를 가지는 칩-온-보드 패키지의 제조 방법 |
US11/181,145 US7315086B2 (en) | 2004-11-03 | 2005-07-13 | Chip-on-board package having flip chip assembly structure and manufacturing method thereof |
US11/941,421 US20080081456A1 (en) | 2004-11-03 | 2007-11-16 | Chip-on-board package having flip chip assembly structure and manufacturing method thereof |
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KR20040088783A KR100610144B1 (ko) | 2004-11-03 | 2004-11-03 | 플립 칩 조립 구조를 가지는 칩-온-보드 패키지의 제조 방법 |
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KR20060039613A true KR20060039613A (ko) | 2006-05-09 |
KR100610144B1 KR100610144B1 (ko) | 2006-08-09 |
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KR20040088783A KR100610144B1 (ko) | 2004-11-03 | 2004-11-03 | 플립 칩 조립 구조를 가지는 칩-온-보드 패키지의 제조 방법 |
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KR (1) | KR100610144B1 (ko) |
Families Citing this family (6)
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KR100891330B1 (ko) * | 2007-02-21 | 2009-03-31 | 삼성전자주식회사 | 반도체 패키지 장치와, 반도체 패키지의 제조방법과,반도체 패키지 장치를 갖는 카드 장치 및 반도체 패키지장치를 갖는 카드 장치의 제조 방법 |
US7745260B2 (en) * | 2008-09-22 | 2010-06-29 | Freescale Semiconductor, Inc. | Method of forming semiconductor package |
US9508626B2 (en) * | 2010-04-23 | 2016-11-29 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming openings in thermally-conductive frame of FO-WLCSP to dissipate heat and reduce package height |
CN102646606B (zh) * | 2011-02-16 | 2014-12-24 | 中电智能卡有限责任公司 | Ic卡模块的封装方法 |
EP3151167B1 (en) * | 2015-09-30 | 2020-05-20 | Nxp B.V. | Dual-interface ic card module |
CN108963035B (zh) * | 2018-07-30 | 2020-04-03 | 安徽科技学院 | 一种带侧面保护的cob封装光电芯片的制作方法 |
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EP0482940B1 (en) * | 1990-10-24 | 1996-03-27 | Nec Corporation | Method of forming an electrical connection for an integrated circuit |
JPH0547847A (ja) | 1991-08-09 | 1993-02-26 | Seiko Epson Corp | 半導体装置 |
JP2606110B2 (ja) | 1993-12-15 | 1997-04-30 | 日本電気株式会社 | 多層基板およびその製造方法 |
JPH08236586A (ja) * | 1994-12-29 | 1996-09-13 | Nitto Denko Corp | 半導体装置及びその製造方法 |
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KR19980025889A (ko) | 1996-10-05 | 1998-07-15 | 김광호 | 중합체층이 개재된 반도체 칩과 기판 간의 범프 접속 구조 |
JP3301355B2 (ja) * | 1997-07-30 | 2002-07-15 | 日立電線株式会社 | 半導体装置、半導体装置用tabテープ及びその製造方法、並びに半導体装置の製造方法 |
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JP2003086629A (ja) | 2001-09-13 | 2003-03-20 | Hitachi Ltd | Cof型半導体装置及びその製造方法 |
SG115455A1 (en) * | 2002-03-04 | 2005-10-28 | Micron Technology Inc | Methods for assembly and packaging of flip chip configured dice with interposer |
KR100510518B1 (ko) * | 2003-01-30 | 2005-08-26 | 삼성전자주식회사 | 반도체 장치 및 반도체 장치의 패키지 방법 |
-
2004
- 2004-11-03 KR KR20040088783A patent/KR100610144B1/ko active IP Right Grant
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2005
- 2005-07-13 US US11/181,145 patent/US7315086B2/en active Active
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2007
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US7315086B2 (en) | 2008-01-01 |
KR100610144B1 (ko) | 2006-08-09 |
US20060091511A1 (en) | 2006-05-04 |
US20080081456A1 (en) | 2008-04-03 |
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