KR20020052489A - A method for forming a metal line of a semiconductor device - Google Patents

A method for forming a metal line of a semiconductor device Download PDF

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KR20020052489A
KR20020052489A KR1020000081780A KR20000081780A KR20020052489A KR 20020052489 A KR20020052489 A KR 20020052489A KR 1020000081780 A KR1020000081780 A KR 1020000081780A KR 20000081780 A KR20000081780 A KR 20000081780A KR 20020052489 A KR20020052489 A KR 20020052489A
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forming
contact hole
layer
tungsten layer
semiconductor device
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KR1020000081780A
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Korean (ko)
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KR100557612B1 (en
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정종열
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박종섭
주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

Abstract

PURPOSE: A method for forming metal interconnection a semiconductor device is provided to prevent voids in a contact plug by using SF6 gases. CONSTITUTION: An interlayer dielectric(23) is formed on a semiconductor substrate(21) having a conductive layer. A contact hole is formed to expose the conductive layer by selectively etching the interlayer dielectric. A barrier metal film(27) is formed on the resultant structure. A first tungsten film(31) is deposited on the surface of the contact hole. The overhang portions of the tungsten film(31) are removed by etch-back using SF6 gases. Then, a contact plug is formed by sufficiently filling a second tungsten film(33) into the contact hole and planarization.

Description

반도체소자의 금속배선 형성방법{A method for forming a metal line of a semiconductor device}A method for forming a metal line of a semiconductor device

본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 특히 금속배선 콘택플러그 형성공정시 보이드 ( void ) 가 유발되는 현상을 방지하여 반도체소자의 특성 및 신뢰성을 향상시키는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring of a semiconductor device, and more particularly, to a method of improving void characteristics and reliability by preventing voids from occurring during a metal wiring contact plug forming process.

일반적으로, 소자간이나 소자와 외부회로 사이를 전기적으로 접속시키기 위한 반도체소자의 배선은, 배선을 위한 소정의 콘택홀 및 비아홀을 배선재료로 매립하여 배선층을 형성하고 후속공정을 거쳐 이루어지며, 낮은 저항을 필요로 하는 곳에는 금속배선을 사용한다.In general, the wiring of a semiconductor device for electrically connecting between devices or between an element and an external circuit is made through a subsequent process by filling a predetermined contact hole and via hole for wiring with a wiring material and forming a wiring layer. Metal wiring is used where resistance is required.

상기 금속배선은 알루미늄(Al)에 소량의 실리콘이나 구리가 포함되거나 실리콘과 구리가 모두 포함되어 비저항이 낮으면서 가공성이 우수한 알루미늄합금을 배선재료로 하여 물리기상증착 ( Physical Vapor Deposition, 이하에서 PVD 라 함 ) 방법의 스퍼터링으로 상기의 콘택홀 및 비아홀을 매립하는 방법이 가장 널리 이용되고 있다.The metal wiring includes a small amount of silicon or copper in aluminum (Al), or both silicon and copper, and has a low resistivity and excellent workability. The method of filling the contact hole and the via hole by sputtering of the method is most widely used.

그리고, 상기 금속배선은 다층으로 형성하는 경우가 발생하게 되었다.In addition, the metal wiring may be formed in multiple layers.

그러나, 반도체소자의 고집적화에 따라 콘택홀 부분을 텅스텐으로 매립하는 텅스텐 콘택플러그를 형성하고 이에 접속되는 금속배선을 형성하는 공정으로 금속배선을 형성하였다.However, in accordance with the high integration of semiconductor devices, metal wirings have been formed by forming a tungsten contact plug which fills contact hole portions with tungsten and forms metal wirings connected thereto.

도 1 은 종래기술에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도이다.1 is a cross-sectional view showing a metal wiring formation method of a semiconductor device according to the prior art.

먼저, 불순물 접합영역, 소자분리막, 워드라인, 비트라인, 캐패시터를 형성하고 그 상부를 평탄화시키는 하부절연층이 구비되는 반도체기판(11)을 형성한다.First, a semiconductor substrate 11 having a lower insulating layer for forming an impurity junction region, an isolation layer, a word line, a bit line, and a capacitor and planarizing an upper portion thereof is formed.

그리고, 상기 반도체기판(11) 상부에 층간절연막(13)을 형성한다. 그리고, 금속배선 콘택마스크(도시안됨)를 이용한 사진식각공정으로 상기 층간절연막(13)을 식각하여 상기 반도체기판(11)을 노출시키는 콘택홀(14)을 형성한다.An interlayer insulating film 13 is formed on the semiconductor substrate 11. The interlayer insulating layer 13 is etched by a photolithography process using a metal wiring contact mask (not shown) to form a contact hole 14 exposing the semiconductor substrate 11.

그리고, 상기 콘택홀(14) 표면을 포함한 전체표면상부에 장벽금속층(15)을 형성한다.The barrier metal layer 15 is formed on the entire surface including the surface of the contact hole 14.

그리고, 상기 콘택홀(14)을 매립하는 텅스텐층(17)을 전체표면상부에 증착한다.Then, a tungsten layer 17 filling the contact hole 14 is deposited on the entire surface.

그리고, 평탄화식각공정으로 텅스텐층(17) 및 장벽금속층(15)을 식각하여 상기 콘택홀(14)을 매립하는 콘택플러그를 형성한다.Then, the tungsten layer 17 and the barrier metal layer 15 are etched by the planarization etching process to form a contact plug to bury the contact hole 14.

그러나, 상기 콘택플러그가 구비되는 콘택홀(14) 내에 보이드(19)가 형성된다.However, a void 19 is formed in the contact hole 14 provided with the contact plug.

상기한 바와같이 종래기술에 따른 반도체소자의 금속배선 형성방법은, 콘택홀을 매립하는 콘택플러그 형성공정시 내부에 보이드가 유발되어 소자의 특성 및 신뢰성을 저하시키고 그에 따른 반도체소자의 수율 및 생산성을 저하시키는 문제점이 있다.As described above, in the method of forming a metal wiring of a semiconductor device according to the prior art, voids are induced in the contact plug forming process of filling contact holes, thereby degrading the characteristics and reliability of the device, thereby improving the yield and productivity of the semiconductor device. There is a problem of deterioration.

따라서, 본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, SF6 가스를 이용한 식각공정과 증착공정을 반복하여 보이드 없는 콘택플러그를 형성함으로써 반도체소자의 특성 및 신뢰성을 향상시키는 반도체소자의 금속배선 형성방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the problems of the prior art, the metal wiring of the semiconductor device is formed to improve the characteristics and reliability of the semiconductor device by forming a void-free contact plug by repeating the etching process and the deposition process using SF6 gas. The purpose is to provide a method.

도 1 은 종래기술에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도.1 is a cross-sectional view showing a metal wiring formation method of a semiconductor device according to the prior art.

도 2a 내지 도 2d 는 본 발명의 실시예에 반도체소자의 금속배선 형성방법을 도시한 단면도.2A to 2D are cross-sectional views illustrating a method for forming metal wirings in a semiconductor device in accordance with an embodiment of the present invention.

< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>

11,21 : 반도체기판13,23 : 층간절연막11,21 semiconductor substrate 13,23 interlayer insulating film

14,25 : 콘택홀15,27 : 장벽금속층14,25: contact hole 15,27: barrier metal layer

17 : 텅스텐층19 : 보이드17: tungsten layer 19: void

31 : 제1텅스텐층33 : 제2텅스텐층31: first tungsten layer 33: second tungsten layer

이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 금속배선 형성방법은,In order to achieve the above object, a metal wiring forming method of a semiconductor device according to the present invention,

제1도전층 상부에 층간절연막을 형성하는 공정과,Forming an interlayer insulating film on the first conductive layer;

상기 층간절연막을 식각하여 상기 제1도전층을 노출시키는 콘택홀을 형성하는 공정과,Etching the interlayer insulating film to form a contact hole exposing the first conductive layer;

상기 콘택홀 표면을 포함한 전체표면상부에 장벽금속층을 형성하는 공정과,Forming a barrier metal layer on the entire surface including the contact hole surface;

상기 콘택홀 표면에 텅스텐층을 증착하는 공정과,Depositing a tungsten layer on the contact hole surface;

상기 텅스텐층의 오버행된 부분을 SF6가스를 이용하여 전면식각하는 공정과,Etching the overhanged portion of the tungsten layer using SF 6 gas;

상기 텅스텐층의 증착공정 및 전면식각공정을 반복하여 상기 콘택플러그를 매립하는 텅스텐층을 형성하는 공정과,Forming a tungsten layer to bury the contact plug by repeating the deposition process and the entire surface etching process of the tungsten layer;

상기 텅스텐층과 장벽금속층을 평탄화식각하여 상기 콘택홀을 매립하는 콘택플러그를 형성하는 공정을 포함하는 것을 특징으로 한다.And forming a contact plug to bury the contact hole by planarizing etching the tungsten layer and the barrier metal layer.

한편, 본 발명의 원리는 다음과 같다.On the other hand, the principle of the present invention is as follows.

오버행 ( over hang ) 이 유발되는 콘택홀의 입구 부분에 증착되는 텅스텐층을 SF6 가스를 이용한 전면식각공정으로 식각하는 공정을 반복하여 텅스텐층을 증착함으로써 콘택홀 입구에서의 텅스텐 성장을 억제하고 측면에서의 성장이 더 많아지도록 하여 콘택홀의 모양에 크게 좌우되지 않고 중앙의 빈 공간, 즉 보이드가 유발되지 않도록 텅스텐을 증착하는 것이다.By repeating the process of etching the tungsten layer deposited at the inlet of the contact hole causing over hang by the front etching process using SF6 gas, the tungsten layer is deposited to suppress the tungsten growth at the inlet of the contact hole and Tungsten is deposited so that there is more growth so that it does not depend greatly on the shape of the contact hole and does not cause voids in the center, that is, voids.

이하, 본 발명을 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2d 는 본 발명에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도이다.2A through 2D are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to the present invention.

도 2a를 참조하면, 불순물 접합영역, 소자분리막, 워드라인, 비트라인, 캐패시터를 형성하고 그 상부를 평탄화시키는 하부절연층이 구비되는 반도체기판(21)을 형성한다.Referring to FIG. 2A, a semiconductor substrate 21 having a lower insulating layer for forming an impurity junction region, an isolation layer, a word line, a bit line, and a capacitor and planarizing an upper portion thereof is formed.

그리고, 상기 반도체기판(21) 상부에 층간절연막(23)을 형성한다. 그리고, 금속배선 콘택마스크(도시안됨)를 이용한 사진식각공정으로 상기 층간절연막(23)을 식각하여 상기 반도체기판(21)을 노출시키는 콘택홀(25)을 형성한다.An interlayer insulating film 23 is formed on the semiconductor substrate 21. The interlayer insulating layer 23 is etched by a photolithography process using a metal wiring contact mask (not shown) to form a contact hole 25 exposing the semiconductor substrate 21.

그리고, 상기 콘택홀(25) 표면을 포함한 전체표면상부에 장벽금속층(27)을 형성한다.A barrier metal layer 27 is formed on the entire surface including the contact hole 25 surface.

도 2b를 참조하면, 상기 콘택홀(25) 표면을 포함한 전체표면상부에 물리기상증착 ( physical vapor deposition, 이하에서 PVD 라 함 ) 방법으로 제1텅스텐층(31)을 증착한다.Referring to FIG. 2B, the first tungsten layer 31 is deposited on the entire surface including the contact hole 25 by physical vapor deposition (hereinafter, referred to as PVD).

도 2c를 참조하면, 상기 텅스텐층(31)을 SF6가스를 이용하여 전면식각하여 상기 콘택홀(25)의 상측, 즉 오버행 (over hang ) 된 부분을 식각한다.Referring to FIG. 2C, the tungsten layer 31 is etched using SF 6 gas to etch the upper side of the contact hole 25, that is, the overhanged portion.

도 2d를 참조하면, 상기 도 2b 및 도 2c 의 공정을 다수 반복하여 상기 콘택홀(25)을 매립하는 제2텅스텐층(33)을 전체표면상부에 형성한다.Referring to FIG. 2D, the second tungsten layer 33 filling the contact hole 25 is formed on the entire surface by repeating the processes of FIGS. 2B and 2C.

이때, 상기 제2텅스텐층(33)은 상기 도 2b 및 도 2c 의 공정인 증착과 식각공정을 다수 반복하여 상기 콘택홀(25)을 매립하는 텅스텐층을 말한다.In this case, the second tungsten layer 33 refers to a tungsten layer filling the contact hole 25 by repeating a plurality of deposition and etching processes in the processes of FIGS. 2B and 2C.

후속공정으로 상기 제2텅스텐층(33)과 장벽금속층(27)을 평탄화식각하여 상기 콘택홀(25)만을 매립하는 콘택플러그를 형성한다.In a subsequent process, the second tungsten layer 33 and the barrier metal layer 27 are planarized and etched to form a contact plug filling only the contact hole 25.

이때, 상기 평탄화식각공정은 상기 층간절연막(23)과 상기 제2텅스텐층(33), 장벽금속층(27)의 식각선택비 차이를 이용한 CMP 공정이나 전면식각공정으로 실시한 것이다.In this case, the planarization etching process may be performed by a CMP process or an entire surface etching process using a difference in etching selectivity between the interlayer insulating layer 23, the second tungsten layer 33, and the barrier metal layer 27.

본 발명의 다른 실시예는 콘택플러그를 형성하는 다른 공정, 예를들어 다층금속배선 형성공정, 비트라인, 캐패시터 등의 콘택공정에 적용하는 것이다.Another embodiment of the present invention is applied to other processes for forming a contact plug, for example, a multi-layer metal wiring forming process, a bit process, a contact process such as a capacitor.

이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 금속배선 형성방법은, 콘택플러그를 텅스텐층으로 형성하되, 오버행이 유발되는 부분을 전면식각하는 공정을 병행하여 오버행 부분이 유발되지않도록 함으로써 콘택홀의 내부에 보이드가 유발되지 않도록 콘택플러그를 형성하여 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 효과가 있다.As described above, in the method of forming the metal wiring of the semiconductor device according to the present invention, the contact plug is formed of a tungsten layer, but the overhang is not caused by performing the entire etching process on the part where the overhang is caused. By forming a contact plug so that no void is caused, there is an effect of improving the characteristics and reliability of the semiconductor device and thereby enabling high integration of the semiconductor device.

Claims (3)

제1도전층 상부에 층간절연막을 형성하는 공정과,Forming an interlayer insulating film on the first conductive layer; 상기 층간절연막을 식각하여 상기 제1도전층을 노출시키는 콘택홀을 형성하는 공정과,Etching the interlayer insulating film to form a contact hole exposing the first conductive layer; 상기 콘택홀 표면을 포함한 전체표면상부에 장벽금속층을 형성하는 공정과,Forming a barrier metal layer on the entire surface including the contact hole surface; 상기 콘택홀 표면에 텅스텐층을 증착하는 공정과,Depositing a tungsten layer on the contact hole surface; 상기 텅스텐층의 오버행된 부분을 SF6 가스를 이용하여 전면식각하는 공정과,Etching the overhanged portion of the tungsten layer using SF6 gas; 상기 텅스텐층의 증착공정 및 전면식각공정을 반복하여 상기 콘택플러그를 매립하는 텅스텐층을 형성하는 공정과,Forming a tungsten layer to bury the contact plug by repeating the deposition process and the entire surface etching process of the tungsten layer; 상기 텅스텐층과 장벽금속층을 평탄화식각하여 상기 콘택홀을 매립하는 콘택플러그를 형성하는 공정을 포함하는 반도체소자의 금속배선 형성방법.And forming a contact plug to fill the contact hole by planarizing etching the tungsten layer and the barrier metal layer. 제 1 항에 있어서,The method of claim 1, 상기 텅스텐층은 PVD 방법으로 증착하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.The tungsten layer is a metal wiring forming method of a semiconductor device, characterized in that deposited by the PVD method. 제 1 항에 있어서,The method of claim 1, 상기 콘택플러그 형성공정을 비트라인, 캐패시터 또는 다층 금속배선의 형성공정에 적용하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.And forming the contact plug in a bit line, a capacitor, or a multilayer metal wiring.
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KR20030035877A (en) * 2001-10-31 2003-05-09 미쓰비시덴키 가부시키가이샤 Semiconductor device fabrication method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030035877A (en) * 2001-10-31 2003-05-09 미쓰비시덴키 가부시키가이샤 Semiconductor device fabrication method

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