KR100458476B1 - Method for forming metal interconnection of semiconductor device to improve filling characteristic of metal thin film and avoid generation of void - Google Patents

Method for forming metal interconnection of semiconductor device to improve filling characteristic of metal thin film and avoid generation of void Download PDF

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KR100458476B1
KR100458476B1 KR1019970075711A KR19970075711A KR100458476B1 KR 100458476 B1 KR100458476 B1 KR 100458476B1 KR 1019970075711 A KR1019970075711 A KR 1019970075711A KR 19970075711 A KR19970075711 A KR 19970075711A KR 100458476 B1 KR100458476 B1 KR 100458476B1
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layer
forming
spacer
semiconductor device
metal wiring
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KR1019970075711A
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KR19990055756A (en
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김영석
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations

Abstract

PURPOSE: A method for forming a metal interconnection of a semiconductor device is provided to improve a filling characteristic of a metal thin film and avoid generation of a void by forming a spacer at both sides of a contact hole such that the spacer is composed of a diffusion blocking layer like a Ti layer or a TiN layer. CONSTITUTION: The first and second insulation layers(15,17) having a difference of etch selectivity are sequentially formed on a semiconductor substrate. A predetermined thickness of a part of the second insulation layer reserved for a metal interconnection contact is dry-etched until before the first insulation layer is exposed and the rest of the second insulation layer is eliminated by a wet etch process. A diffusion blocking layer is formed on the resultant structure. The diffusion blocking layer is blanket-etched to form a spacer on the sidewall of the second insulation layer. The first insulation layer is etched to form a contact hole for a metal interconnection by using the second insulation layer and the spacer as an etch mask. A conductive layer for the metal interconnection is formed on the resultant structure.

Description

반도체소자의 금속배선 형성방법Metal wiring formation method of semiconductor device

본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로서, 특히 콘택홀의 입구부분에 형성된 문턱에 Ti 또는 TiN 층 스페이서를 형성하고, 금속배선을 형성함으로써 상기 금속배선의 매립 특성을 향상시켜 보이드가 발생하는 것을 방지하고, 콘택 저항을 감소시켜 소자의 동작속도를 향상시키는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring in a semiconductor device. In particular, a Ti or TiN layer spacer is formed on a threshold formed at an inlet of a contact hole, and a metal wiring is formed to improve the buried property of the metal wiring to generate voids. To reduce the contact resistance and improve the operation speed of the device.

일반적으로, 소자간이나 소자와 외부회로 사이를 전기적으로 접속시키기 위한 반도체소자의 배선은, 배선을 위한 소정의 콘택홀 및 비아홀을 배선재료로 매립하여 배선층을 형성하고, 후속 공정을 거쳐 이루어지며 낮은 저항을 필요로 하는 곳에는 금속배선을 사용한다.In general, the wiring of a semiconductor device for electrically connecting between devices or between an element and an external circuit is formed by filling a predetermined contact hole and via hole for wiring with a wiring material, forming a wiring layer, and performing a subsequent process. Metal wiring is used where resistance is required.

상기 금속배선은 알루미늄(Al)에 소량의 실리콘이나 구리가 포함되거나 실리콘과 구리가 모두 포함되어 비저항이 낮으면서 가공성이 우수한 알루미늄합금을 배선재료로 하여 물리기상증착(physical vapor deposition, 이하 PVD 라함)방법의 스퍼터링으로 상기의 콘택홀 및 비아홀을 매립하는 방법으로 형성된다.The metal wiring includes a small amount of silicon or copper in aluminum (Al), or both silicon and copper, and has a low resistivity and has excellent workability and uses an aluminum alloy as a wiring material for physical vapor deposition (hereinafter referred to as PVD). It is formed by the method of filling the contact hole and the via hole by sputtering of the method.

근래에는 반도체소자의 초고집적화에 따라 금속 콘택의 크기는 작아지고, 단차비는 높아져서 스퍼터링에 의한 금속배선의 층덮힘이 불량하게 되어 신뢰성을 얻기가 어려워졌다.In recent years, as the semiconductor device has been highly integrated, the size of the metal contact becomes smaller and the step difference ratio becomes higher, resulting in poor layer coverage of the metal wiring by sputtering, making it difficult to obtain reliability.

상기와 같이 종래기술에 따른 반도체소자의 금속배선 형성방법은, 습식 및 건식식각 공정을 실시하여 형성된 콘택홀의 입구부분에 상기 습식식각 공정으로 인하여 문턱이 형성되는데, 후속 금속박막을 형성하는 스퍼터 공정시 ⓐ 부분과 같이 문턱에 금속이 집중되어 층덮힘이 불량하게 됨으로써 ⓑ 와 같은 보이드를 형성하여 ⓒ 부분과 같이 금속배선이 단락되거나 콘택 저항을 증가시키는 문제점이 있다. (도 1a, 1b참조)As described above, in the method of forming a metal wiring of a semiconductor device according to the prior art, a threshold is formed in the inlet portion of a contact hole formed by performing wet and dry etching processes due to the wet etching process. As the metal is concentrated on the threshold as in the ⓐ part, the layer covering is poor, thereby forming voids such as ⓑ, which causes short circuiting of the metal wires and increases contact resistance as in the ⓒ part. (See FIGS. 1A and 1B)

본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 콘택홀 양쪽 가장자리에 확산방지막인 Ti층 또는 TiN 층으로 스페이서를 형성시켜 문턱을 제거함으로써 금속박막의 매립 특성을 향상시켜 보이드가 발생하는 것을 방지하고, 콘택 저항을 감소시키며 그에 따른 소자의 동작 속도 및 수율을 향상시키는 반도체소자의 금속배선 형성방법을 제공하는데 그 목적이 있다.The present invention is to solve the problems of the prior art, by forming a spacer with a Ti layer or a TiN layer as a diffusion barrier on both edges of the contact hole to remove the threshold to improve the buried property of the metal thin film to prevent the generation of voids In addition, the object of the present invention is to provide a method for forming a metal wiring of a semiconductor device which reduces contact resistance and thereby improves the operation speed and yield of the device.

이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 금속배선 형성방법은,In order to achieve the above object, a metal wiring forming method of a semiconductor device according to the present invention,

반도체기판 상부에 식각선택비 차이가 있는 제1절연막 및 제2절연막을 순차적으로 형성하는 공정과,Sequentially forming a first insulating film and a second insulating film having an etch selectivity difference on the semiconductor substrate;

금속배선 콘택으로 예정되어 있는 부분의 제2절연막을 상기 제1절연막이 노출되기 전까지 소정 두께 건식식각하고, 습식식각방법으로 남은 부분을 제거하는 공정과,A step of dry etching the second insulating film of the portion scheduled as the metal wiring contact until the first insulating film is exposed, and removing the remaining portion by the wet etching method;

상기 구조 상부에 확산방지막을 형성하는 공정과,Forming a diffusion barrier on the structure;

상기 확산방지막을 전면식각하여 상기 제 2 절연막의 측벽에 스페이서를 형성하는 공정과,Forming a spacer on the sidewall of the second insulating layer by etching the entire diffusion barrier layer;

상기 제2절연막 및 스페이서를 식각마스크로 사용하여 상기 제1절연막을 식각하여 금속배선용 콘택홀을 형성하는 공정과,Etching the first insulating layer by using the second insulating layer and the spacer as an etching mask to form a contact hole for metal wiring;

상기 구조 상부에 금속배선용 도전층을 형성하는 공정을 포함하는 것을 특징으로 한다.And forming a conductive layer for metal wiring on the structure.

이하, 본 발명에 따른 반도체소자의 금속배선 형성방법에 관하여 첨부 도면을 참조하여 상세히 설명한다.Hereinafter, a method of forming metal wirings of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2g 는 본 발명에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도이다.2A to 2G are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to the present invention.

먼저, 비트라인 및 워드라인 등과 같은 하부도전층(13)이 형성되어 있는 하부절연막(11) 상부에 제1절연막(15) 및 제2절연막(17)을 순차적으로 형성한다. 여기서, 상기 제1절연막(15)은 에스.오.지.(spin on glass, 이하 SOG 라 함), 비.피.에스.지.(boro phospho silicate glass, 이하 BPSG 라 함) 또는 피.이.-테오스(plasma enhanced tetra ethyl ortho silicate glass, 이하 PE-TEOS 라 함)를 사용하여 형성하고, 상기 제2절연막(17)은 상기 제1절연막(15)과 식각선택비가 큰 질화막을 사용하여 형성한다. (도 2a, 2b참조)First, the first insulating layer 15 and the second insulating layer 17 are sequentially formed on the lower insulating layer 11 on which the lower conductive layer 13 such as the bit line and the word line is formed. Herein, the first insulating layer 15 may include S.O.G. (SOG), boro phospho silicate glass (hereinafter, referred to as BPSG) or P.G. .-Theos (plasma enhanced tetra ethyl ortho silicate glass, hereinafter referred to as PE-TEOS), and the second insulating film 17 is a nitride film having a large etching selectivity with the first insulating film 15 Form. (See Figures 2A and 2B)

다음, 상기 제2절연막(17)을 금속배선용 콘택 마스크(19)를 이용한 식각공정으로 제거한다. 이때, 상기 식각공정은 건식식각공정을 실시하여 상기 제2절연막(17)의 일부를 제거한 다음, 습식식각공정을 실시하여 완전히 제거하는 방법으로 진행한다.Next, the second insulating layer 17 is removed by an etching process using the metallization contact mask 19. In this case, the etching process may be performed by performing a dry etching process to remove a part of the second insulating layer 17 and then performing a wet etching process to completely remove the second insulating layer 17.

한편, 상기 제2절연막(17)을 제거하는 식각공정은 건식식각공정은 생략하고, 습식식각공정으로만 실시할 수도 있다. (도 2d참조)Meanwhile, the etching process for removing the second insulating layer 17 may be performed only by the wet etching process without the dry etching process. (See FIG. 2D)

그 다음, 상기 구조 상부에 Ti 또는 TiN 층(21)을 전면적으로 형성한다. (도 2e참조)Next, a Ti or TiN layer 21 is formed over the structure. (See Figure 2E)

다음, 상기 Ti 또는 TiN 층(21)을 전면식각공정으로 식각하여 상기 제2절연막(17) 식각공정시 형성된 문턱에 Ti 또는 TiN 층(21) 스페이서를 형성한다.Next, the Ti or TiN layer 21 is etched by the entire surface etching process to form the Ti or TiN layer 21 spacer on the threshold formed during the etching process of the second insulating layer 17.

그리고, 상기 제2절연막(17) 및 Ti 또는 TiN 층(21) 스페이서를 식각마스크로 사용하여 상기 제1절연막(15)을 식각하여 콘택홀을 형성한다. (도 2f참조)The first insulating layer 15 is etched using the second insulating layer 17 and the spacer of the Ti or TiN layer 21 as an etching mask to form a contact hole. (See Figure 2f)

그 후, 상기 구조 상부에 금속박막(23)을 형성하여 상기 하부구조물(13)과 접촉되는 금속배선을 형성한다. (도 2g참조)Thereafter, a metal thin film 23 is formed on the structure to form a metal wiring in contact with the lower structure 13. (See Fig. 2g)

이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 금속배선 형성방법은, 금속배선용 콘택홀 형성공정을 실시하는 경우 콘택홀 입구부분에 습식식각으로 인하여 형성된 문턱에 Ti 또는 TiN 층 스페이서를 형성하여 라운딩시킴으로써 금속박막이 상기 콘택홀의 입구에 집중되는 것을 방지하여 상기 콘택홀의 하부에 보이드(void)가 발생하는 것을 방지하여 금속배선의 매립 특성을 강화시켜 콘택 저항을 감소시키고 그에 따른 반도체소자의 수율 및 특성을 향상시키는 이점이 있다.As described above, in the method of forming the metal wiring of the semiconductor device according to the present invention, when the contact hole forming process for the metal wiring is performed, a Ti or TiN layer spacer is formed and rounded on the threshold formed by wet etching at the contact hole inlet. The metal thin film is prevented from being concentrated at the inlet of the contact hole, thereby preventing voids from occurring in the lower portion of the contact hole, thereby strengthening the buried characteristics of the metal wiring, thereby reducing the contact resistance and thereby increasing the yield and characteristics of the semiconductor device. There is an advantage to improve.

도 1a 및 도 1b 는 종래기술에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도.1A and 1B are cross-sectional views illustrating a metal wiring forming method of a semiconductor device according to the prior art.

도 2a 내지 도 2g 는 본 발명의 실시예에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도. 2A to 2G are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.

<도면의 주요부분에 대한 부호 설명><Description of Signs of Major Parts of Drawings>

11 : 하부절연막 13 : 하부구조물11: lower insulating film 13: lower structure

15 : 제1절연막 17 : 제2절연막15: first insulating film 17: second insulating film

19 : 콘택 마스크 21 : Ti 또는 TiN 층19: contact mask 21: Ti or TiN layer

23 : 금속박막23: metal thin film

Claims (4)

반도체기판 상부에 식각선택비 차이가 있는 제1절연막 및 제2절연막을 순차적으로 형성하는 공정과,Sequentially forming a first insulating film and a second insulating film having an etch selectivity difference on the semiconductor substrate; 금속배선 콘택으로 예정되어 있는 부분의 제2절연막을 상기 제1절연막이 노출되기 전까지 소정 두께 건식식각하고, 습식식각방법으로 남은 부분을 제거하는 공정과,A step of dry etching the second insulating film of the portion scheduled as the metal wiring contact until the first insulating film is exposed, and removing the remaining portion by the wet etching method; 상기 구조 상부에 확산방지막을 형성하는 공정과,Forming a diffusion barrier on the structure; 상기 확산방지막을 전면식각하여 상기 제 2 절연막의 측벽에 스페이서를 형성하는 공정과,Forming a spacer on the sidewall of the second insulating layer by etching the entire diffusion barrier layer; 상기 제2절연막 및 스페이서를 식각마스크로 사용하여 상기 제1절연막을 식각하여 금속배선용 콘택홀을 형성하는 공정과,Etching the first insulating layer by using the second insulating layer and the spacer as an etching mask to form a contact hole for metal wiring; 상기 구조 상부에 금속배선용 도전층을 형성하는 공정을 포함하는 반도체소자의 금속배선 형성방법. And forming a conductive layer for metal wiring on the structure. 제 1 항에 있어서,The method of claim 1, 상기 제1절연막은 SOG, BPSG 또는 PE-TEOS 를 사용하여 형성하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.And the first insulating layer is formed using SOG, BPSG or PE-TEOS. 제 1 항에 있어서,The method of claim 1, 상기 제2절연막은 질화막으로 형성하는것을 특징으로 하는 반도체소자의 금속배선 형성방법.And the second insulating film is formed of a nitride film. 제 1 항에 있어서,The method of claim 1, 상기 확산방지막은 Ti 또는 TiN 층으로 형성하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.The diffusion barrier layer is formed of a Ti or TiN layer metal wiring method of the semiconductor device, characterized in that formed.
KR1019970075711A 1997-12-27 1997-12-27 Method for forming metal interconnection of semiconductor device to improve filling characteristic of metal thin film and avoid generation of void KR100458476B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960030327A (en) * 1995-01-05 1996-08-17 김주용 Contact hole formation method of semiconductor device
JPH0963989A (en) * 1995-08-18 1997-03-07 Nec Corp Semiconductor device and manufacture thereof
US5882535A (en) * 1997-02-04 1999-03-16 Micron Technology, Inc. Method for forming a hole in a semiconductor device
KR100367695B1 (en) * 1995-06-30 2003-02-26 주식회사 하이닉스반도체 Method for forming via contact in semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960030327A (en) * 1995-01-05 1996-08-17 김주용 Contact hole formation method of semiconductor device
KR100367695B1 (en) * 1995-06-30 2003-02-26 주식회사 하이닉스반도체 Method for forming via contact in semiconductor device
JPH0963989A (en) * 1995-08-18 1997-03-07 Nec Corp Semiconductor device and manufacture thereof
US5882535A (en) * 1997-02-04 1999-03-16 Micron Technology, Inc. Method for forming a hole in a semiconductor device

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