KR100265972B1 - Method for forming mutilayer og semiconductor device - Google Patents

Method for forming mutilayer og semiconductor device Download PDF

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KR100265972B1
KR100265972B1 KR1019970082303A KR19970082303A KR100265972B1 KR 100265972 B1 KR100265972 B1 KR 100265972B1 KR 1019970082303 A KR1019970082303 A KR 1019970082303A KR 19970082303 A KR19970082303 A KR 19970082303A KR 100265972 B1 KR100265972 B1 KR 100265972B1
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South Korea
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contact hole
conductive layer
forming
insulating film
layer
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KR1019970082303A
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Korean (ko)
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KR19990061998A (en
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윤종원
이남일
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium

Abstract

PURPOSE: A method for forming a multi layer interconnection is to form a metallic interconnection having no bridge fail in regardless of a step difference of a wafer. CONSTITUTION: The first metallic interconnection is formed on a substrate having a lower structure, and an interlayer dielectric(20) is formed on the entire surface of the substrate. A contact hole is formed in the interlayer dielectric to expose the first metallic interconnection. A barrier metallic layer(30) and aluminium are deposited on the interlayer dielectric having the contact hole. The aluminium formed on the interlayer dielectric having no contact hole is dry-etched to form an aluminium plug(52a) for filling a portion of the contact hole. An insulating film(60) is deposited on the entire surface of the substrate in a thick thickness, and is patterned to open the aluminium plug. The first conductive layer(50) is deposited on the insulating pattern to bury the contact hole.

Description

반도체장치의 다층배선 형성방법{Method for forming mutilayer og semiconductor device}Method for forming mutilayer og semiconductor device

본 발명은 반도체장치의 다층배선 형성방법에 관한 것으로서, 보다 상세하게는 층간연결을 위해 사용되는 텅스텐 플러그 대신 알루미늄 플러그를 사용하여 어떠한 단차선에서도 완벽한 콘택홀 매립과 금속배선을 형성하여 후속공정시 용이하도록 평탄화하는 반도체장치의 다층배선 형성방법에 관한 것이다.The present invention relates to a method for forming a multi-layer wiring of a semiconductor device, and more particularly, by using an aluminum plug instead of a tungsten plug used for interlayer connection, perfect contact hole filling and metal wiring can be formed in any stepped line to facilitate subsequent processing. The present invention relates to a method for forming a multilayer wiring of a semiconductor device which is planarized so as to be flattened.

반도체장치의 배선은 반도체장치의 속도, 수율 및 신뢰성에 큰 영향을 주기 때문에, 반도체장치의 배선 형성공정은 반도체장치 제조공정 중에 매우 중요한 위치를 차지하고 있다.Since the wiring of the semiconductor device greatly influences the speed, yield and reliability of the semiconductor device, the wiring forming process of the semiconductor device occupies a very important position in the semiconductor device manufacturing process.

일반적으로, 반도체장치는 그 집적도가 증가하고 내부 회로가 복잡해지는 추세에 부응하여 다층의 배선 구조를 가지며, 이러한 다층배선은 화학기상증착(CVD)방법으로 형성된 텅스텐 플러그를 통하여 서로 연결된다.In general, semiconductor devices have a multi-layered wiring structure in response to a trend of increasing integration and increasing internal circuits, and the multi-layered wirings are connected to each other through tungsten plugs formed by chemical vapor deposition (CVD).

도1은 일반적인 반도체장치의 다층배선 형성방법을 설명하기 위한 텅스텐 플러그 형성공정을 단계적으로 도시한 단면도이다.1 is a cross-sectional view illustrating a tungsten plug forming process step by step for explaining a method for forming a multilayer wiring of a general semiconductor device.

도1a는 제1금속배선(5)을 형성하고 평탄화를 위한 SOG막을 도포한 후 SOG막을 에치백(etch back)하여 제1평탄화된 절연막(10)을 형성한다. 계속해서 층간절연막(20)을 형성하고 제1금속배선(5) 상부의 층간절연막(20)이 노출되도록 층간절연막(20) 상부에 감광막 패턴을 형성하여 이 감광막 패턴을 식각 마스크로 하여 층간절연막(20)을 이방성 식각하여 콘택홀(25)을 형성한 후 감광막 패턴을 제거한다. 그리고 전면에 티타늄(Ti)막과 질화 티타늄(TiN)막이 순차적으로 적층된 장벽금속층(30)을 800 내지 1000Å의 두께로 형성한 상태를 나타낸 단면도이다.FIG. 1A shows a first planarized insulating film 10 by forming a first metal wiring 5, applying a SOG film for planarization, and then etching back the SOG film. Subsequently, an interlayer insulating film 20 is formed, and a photosensitive film pattern is formed on the interlayer insulating film 20 so that the interlayer insulating film 20 on the first metal wiring 5 is exposed, and the photosensitive film pattern is used as an etching mask. 20) is anisotropically etched to form the contact holes 25 and then remove the photoresist pattern. And it is sectional drawing which shows the state which formed the barrier metal layer 30 in which the titanium (Ti) film and the titanium nitride (TiN) film was laminated | stacked on the front surface in the thickness of 800-1000 GPa.

도1b는 도1a에서 형성된 콘택홀(25)을 채우도록 장벽금속층(30) 위로 텅스텐(40)을 화학기상증착방법으로 4000Å 내지 7000Å의 두께만큼 증착한 상태를 나타낸 단면도이다.FIG. 1B is a cross-sectional view illustrating a state in which tungsten 40 is deposited on the barrier metal layer 30 by a chemical vapor deposition method so as to fill the contact hole 25 formed in FIG.

도1c는 도1b에서 형성된 텅스텐(40)을 SF6기체를 사용하여 장벽금속층(30)이 노출될때까지 에치백하여 텅스텐 플러그(40a)를 형성한 상태를 나타낸 단면도이다.1C is a cross-sectional view illustrating a state in which the tungsten 40 formed in FIG. 1B is etched back using the SF 6 gas until the barrier metal layer 30 is exposed, thereby forming a tungsten plug 40a.

도1d는 도1c에서 형성된 텅스텐 플러그(40a) 위로 제1도전층(50)으로 알루미늄을 증착한 상태를 나타낸 단면도이다.FIG. 1D is a cross-sectional view illustrating a state in which aluminum is deposited as the first conductive layer 50 on the tungsten plug 40a formed in FIG. 1C.

위와 같이 반도체장치의 다층배선 병성방법에 의하면, 콘택홀의 매립이 용이한 텅스텐 플러그를 이용하여 다층배선을 전기적으로 서로 연결시켜 주지만 턴스텐 자체의 비저항이 상당히 크기 때문에 텅스텐 플러그에 의한 RC지연이 증가하여 반도체장치의 속도가 떨어질 뿐만 아니라 저항에 따른 주울(Joule)열이 발생하여 금속배선이 단선된다는 문제점이 있다.According to the multi-layer wiring pathing method of the semiconductor device as described above, the multi-layer wiring is electrically connected to each other by using a tungsten plug which is easy to bury the contact hole, but the RC delay caused by the tungsten plug is increased because the specific resistance of the turnsten itself is large. Not only does the speed of the semiconductor device decrease, but also Joule heat is generated due to the resistance, which causes a problem that the metal wiring is disconnected.

본 발명은 상기와 같은 문제점을 해결하기 위해 창작된 것으로서, 본 발명의 목적은 다층 배선시 비저항이 적은 금속 화학적기계적연마공정을 도입하여 웨이퍼의 단차와는 무관하게 브리지페일이 존재하지 않는 금속배선을 형성하고 금속배선후 완전한 웨이퍼의 평탄화를 이루도록 한 반도체장치의 금속배선 형성방법을 제공함에 있다.The present invention has been made to solve the above problems, and an object of the present invention is to introduce a metal chemical mechanical polishing process with a low specific resistance when multi-layer wiring to provide a metal wiring in which bridge bridge does not exist regardless of wafer step. The present invention provides a method of forming a metal wiring in a semiconductor device to form and planarize a complete wafer after metal wiring.

도 1a 내지 도 1d는 일반적인 반도체장치의 다층배선 형성방법을 설명하기 위해 다층배선 형성공정을 단계적으로 나타낸 단면도이다.1A to 1D are cross-sectional views illustrating a process of forming a multilayer wiring in order to explain a method of forming a multilayer wiring of a general semiconductor device.

도 2a 내지 도 2i는 본 발명에 의한 반도체장치의 다층배선 형성방법을 설명하기 위해 다층배선 형성공정을 단계적으로 나타낸 단면도이다.2A to 2I are cross-sectional views illustrating a process of forming a multilayer wiring in order to explain a method of forming a multilayer wiring of a semiconductor device according to the present invention.

- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings

10 : 제1평탄화된 절연막 20 : 층간절연막10: first planarized insulating film 20: interlayer insulating film

30 : 장벽금속층 40a : 텅스텐 플러그30: barrier metal layer 40a: tungsten plug

50 : 제1도전층 52a : 알루미늄 플러그50: first conductive layer 52a: aluminum plug

54 : 제2도전층 60 : 제2평탄화된 절연막54 second conductive layer 60 second planarized insulating film

70 : 감광막 패턴70 photosensitive film pattern

상기와 같은 목적을 실현하기 위한 본 발명은 하부구조물이 형성된 반도체기판 상부에 제1금속배선, 기판 전면에 평탄화된 층간절연막을 차례로 형성하는 단계와, 층간 절연막내에 제1금속배선을 노출시키는 콘택홀을 형성하는 단계와, 콘택홀이 형성된 층간 절연막에 장벽금속층과 알루미늄을 차례로 증착하는 단계와, 콘택홀이 형성되지 않는 층간 절연막 상부의 알루미늄을 감광막없이 건식식각하여 콘택홀의 일부를 채우는 알루미늄플러그를 형성하는 단계와, 기판 전면에 평탄화된 절연막을 두껍게 증착하는 단계와, 평탄화된 절연막을 패터닝하여 알루미늄 플러그를 개방하는 단계와, 절연막 패턴 사이의 콘택홀에 매립되도록 제1도전층을 증착하는 단계와, 제1도전층을 증착한 후에 평탄화공정으로 제1도전층과 평탄화된 절연막의 특정부위까지 제거하는 단계와, 평탄화된 결과물에 콘택홀을 완전히 매립하기 위하여 제2도전층을 증착하고 평탄화공정으로 제2도전층을 평탄화하여 제1도전층과 제2도전층으로 이루어진 제2금속배선을 형성하는 단계로 이루어진다.According to an aspect of the present invention, there is provided a method of forming a first metal wiring on an upper surface of a semiconductor substrate on which a lower structure is formed, and then forming a planarized interlayer insulating film on the entire surface of the substrate, and contact holes exposing the first metal wiring in the interlayer insulating film. Forming a barrier layer, and sequentially depositing a barrier metal layer and aluminum on the interlayer insulating film on which the contact hole is formed; and forming an aluminum plug to fill a part of the contact hole by dry etching the aluminum on the upper interlayer insulating film on which the contact hole is not formed. Depositing a planarized insulating film thickly on the entire surface of the substrate, patterning the planarized insulating film to open the aluminum plug, depositing a first conductive layer so as to be embedded in the contact hole between the insulating film patterns; After depositing the first conductive layer, the planarization process is performed to the specific portion of the first conductive layer and the planarized insulating film. A second conductive layer is deposited to completely fill the contact hole in the flattened resultant, and the second conductive layer is planarized to form a second metal wiring including the first conductive layer and the second conductive layer. It consists of steps.

상기와 같이 이루어진 본 발명은 알루미늄 플러그를 사용함으로써 콘택홀의 매립시 매립의 불용이함을 2차에 걸친 알루미늄의 도전층 증착과 평탄화로 콘택홀을 완전히 매립시킬 수 있어 전도성이 좋은 알루미늄으로 다층배선을 하게 된다.The present invention made as described above makes it possible to completely fill the contact hole by depositing and planarizing the conductive layer of aluminum over the second time. do.

이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이며 종래 구성과 동일한 부분은 동일한 부호 및 명칭을 사용한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.

도2는 본 발명에 따른 반도체장치의 다층배선 형성방법을 설명하기 위해 다층배선 형성공정을 단계적으로 나타낸 단면도이다.2 is a cross-sectional view illustrating a process of forming a multilayer wiring step by step in order to explain a method of forming a multilayer wiring of a semiconductor device according to the present invention.

도2a는 제1금속배선(5)을 형성하고 평탄화를 위한 SOG막을 도포한 후 SOG막을 에치백(etch back)하여 제1평탄화된 절연막(10)을 형성한 후 계속해서 층간절연막(20)을 형성하고 제1금속배선(5) 상부의 층간절연막(20)이 노출되도록 층간절연막(20) 상부에 감광막 패턴을 형성하여 이 감광막 패턴을 식각 마스크로 하여 층간절연막(20)을 이방성 식각하여 콘택홀(25)을 형성한 후 감광막 패턴을 제거한다. 그리고 전면에 티타늄(Ti)막과 질화 티타늄(TiN)막이 순차적으로 적층된 장벽금속층(30)을 800Å 내지 1000Å의 두께로 형성한 상태를 나타낸 단면도이다.FIG. 2A shows the formation of the first metallization line 5, coating the SOG film for planarization, and then etching back the SOG film to form the first flattened insulating film 10, followed by the interlayer insulating film 20. And a photoresist pattern is formed on the interlayer insulating layer 20 so that the interlayer insulating layer 20 on the first metal wiring 5 is exposed. The interlayer insulating layer 20 is anisotropically etched using the photoresist pattern as an etch mask to form a contact hole. After forming (25), the photosensitive film pattern is removed. And it is sectional drawing which shows the state which formed the barrier metal layer 30 in which the titanium (Ti) film and the titanium nitride (TiN) film was laminated | stacked on the front surface in the thickness of 800 kV-1000 kV.

도2b는 도2a에서 형성된 장벽금속층(30)과 콘택홀(25) 전면에 알루미늄(52)을 증착한 형태를 나타낸 단면도이다.FIG. 2B is a cross-sectional view illustrating the deposition of aluminum 52 on the barrier metal layer 30 and the contact hole 25 formed in FIG. 2A.

도2b에 도시된 바와 같이 콘택홀(25) 내부에 매립된 알루미늄(52)은 완전한 매립이 이루어지지 않음을 알 수 있다.As shown in FIG. 2B, the aluminum 52 embedded in the contact hole 25 may not be completely embedded.

도2c는 도2b에서 증착한 알루미늄(52)을 감광막없이 건식식각하여 콘택홀이 형성되지 않는 층간 절연막(20) 상부에 알루미늄이 남아있지 않도록 하면서 콘택홀의 일부를 채우는 알루미늄플러그(52a)를 형성한다.FIG. 2C dry-etches the aluminum 52 deposited in FIG. 2B without a photoresist to form an aluminum plug 52a which fills a part of the contact hole while preventing aluminum from remaining on the interlayer insulating film 20 where the contact hole is not formed. .

도2d는 도2c에서의 식각공정이 끝난후 웨이터의 단차를 감소시키는데 용이하게 제2평탄화된 절연막(60)(예컨대, BPSG막)을 10000Å정도의 두께로 두껍게 증착한 상태를 나타낸 단면도이다.FIG. 2D is a cross-sectional view showing a state in which a second planarized insulating film 60 (for example, a BPSG film) is thickly deposited to a thickness of about 10000 [mu] s easily to reduce the step difference of the waiter after the etching process in FIG.

도2e는 도2d에서 두껍게 증착한 제2평탄화된 절연막(60) 위에 이후 형성될 금속배선의 영역을 정의하는 네가티브 감광막 패턴(70)을 도포한 상태를 나타낸 단면도이다.FIG. 2E is a cross-sectional view showing a state where a negative photosensitive film pattern 70 is applied on the second planarized insulating film 60 thickly deposited in FIG. 2D to define an area of a metal wiring to be formed later.

도2f는 도2e에서 도포된 감광막 패턴(70)을 마스크로 삼아 제2평탄화된 절연막(60)을 식각하여 알루미늄 플러그(52a)가 노출되는 콘택홀을 형성한다.Referring to FIG. 2F, the second planarized insulating layer 60 is etched using the photoresist pattern 70 applied in FIG. 2E as a mask to form a contact hole through which the aluminum plug 52a is exposed.

이때 식각공정은 실제로는 절연막 식각을 통하여 이루어지기 때문에 현재 콘택에치에서 진행하고 있는 에치타겟(etch target)이나 에스펙비(aspect ratio) 등을 고려할 경우 식각에는 아무런 문제가 없다.In this case, since the etching process is actually performed through the insulating layer etching, there is no problem in etching when considering the etch target or the aspect ratio which is currently being performed in the contact etch.

도2g는 도2f에서 절연막 패턴(60)에 의해 콘택홀이 형성된 결과물에 제1도전층(50)으로 알루미늄을 증착한 상태를 나타낸 단면도이다.2G is a cross-sectional view illustrating a state in which aluminum is deposited as the first conductive layer 50 on a resultant in which contact holes are formed by the insulating film pattern 60 in FIG.

이때 알루미늄의 증착조건설정은 상부의 알루미늄이 하부로 밀려들어가게 함으로서 어느 정도의 콘택홀매립이 이루어지도록 한다.At this time, the deposition condition of the aluminum is set to a certain degree of contact hole filling by allowing the upper aluminum to be pushed to the lower.

도2h는 도2g에서 증착한 제1도전층(50)인 알루미늄을 화학적기계적연마공정을 사용하여 제1도전층(50) 및 제2평탄화된 절연막(60)인 BPSG막을 1차 연마한 상태를 나타낸 단면도이다.FIG. 2H illustrates a state in which the first conductive layer 50 deposited in FIG. 2G is first polished on the BPSG film, which is the first conductive layer 50 and the second planarized insulating layer 60, using a chemical mechanical polishing process. It is sectional drawing shown.

이때 1차 연마타켓은 알루미늄막의 2차증착시 금속라인의 매립이 가능할 수 있도록 조절한다.At this time, the primary polishing target is adjusted to enable the embedding of the metal line during the second deposition of the aluminum film.

도2i는 도2h에서 1차연마하여 평탄화된 결과물 전면에 제2도전층(54)으로서 알루미늄을 다시 증착하고, 2차 화학적기계적 연마 공정으로 제2평탄화된 절연막(60)까지 평탄화하여 금속배선을 형성한 상태를 나타낸 단면도이다.FIG. 2I shows the deposition of aluminum as the second conductive layer 54 on the entire surface of the flattened resultant by primary polishing in FIG. 2H and planarization to the second planarized insulating film 60 by the second chemical mechanical polishing process. It is sectional drawing which showed the formed state.

상기 제2도전층(54)의 증착으로 콘택홀에는 제1도전층(50)과 제2도전층(54)으로 구성되며 하부의 알루미늄 플러그와 연결되는 제2금속배선을 형성하게 된다.The deposition of the second conductive layer 54 forms a second metal wiring in the contact hole, which is composed of the first conductive layer 50 and the second conductive layer 54 and connected to the lower aluminum plug.

상기한 바와 같이 본 발명은 다층배선을 비저항이 작은 알루미늄 플러그를 이용한 금속평탄화 공정을 도입함으로써 웨이퍼의 단차와는 무관하게 브리지 오류가 존재하지 않는 금속배선을 형성할 수 있다는 이점이 있다.As described above, the present invention has the advantage of forming a metal wiring in which the bridge error does not exist regardless of the step height of the wafer by introducing a metal leveling process using an aluminum plug having a low specific resistance.

또한, 금속배선 형성후 완전한 웨이퍼의 평탄화를 이룩함으로서 다층배선 공정시 후속공정이 용이하여 소자의 수율증가 및 특성개선을 가능하게 되어 반도체장치의 신뢰성이 향상된다는 이점이 있다.In addition, since the wafer is completely formed after the metal wiring is formed, the subsequent process is easy in the multi-layer wiring process, so that the yield of the device can be improved and the characteristics can be improved, thereby improving the reliability of the semiconductor device.

Claims (4)

하부구조물이 형성된 반도체기판 상부에 제1금속배선, 상기 기판 전면에 평탄화된 층간절연막을 차례로 형성하는 단계와,Sequentially forming a first metal wiring on the semiconductor substrate on which the lower structure is formed, and a planarized interlayer insulating film on the entire surface of the substrate; 상기 층간 절연막내에 제1금속배선을 노출시키는 콘택홀을 형성하는 단계와,Forming a contact hole exposing a first metal wiring in the interlayer insulating film; 상기 콘택홀이 형성된 층간 절연막에 장벽금속층과 알루미늄을 차례로 증착하는 단계와,Sequentially depositing a barrier metal layer and aluminum on the interlayer insulating layer on which the contact hole is formed; 상기 콘택홀이 형성되지 않는 층간 절연막 상부의 알루미늄을 감광막없이 건식식각하여 콘택홀의 일부를 채우는 알루미늄플러그를 형성하는 단계와,Forming an aluminum plug to fill a part of the contact hole by dry etching the aluminum on the interlayer insulating layer without the contact hole without a photoresist; 상기 기판 전면에 평탄화된 절연막을 두껍게 증착하는 단계와,Thickly depositing a planarized insulating film on the entire surface of the substrate; 상기 평탄화된 절연막을 패터닝하여 알루미늄 플러그를 개방하는 단계와,Patterning the planarized insulating film to open an aluminum plug; 상기 절연막 패턴 사이의 콘택홀에 매립되도록 제1도전층을 증착하는 단계와,Depositing a first conductive layer so as to be buried in the contact hole between the insulating film patterns; 상기 제1도전층을 증착한 후에 평탄화공정으로 상기 제1도전층과 상기 평탄화된 절연막의 특정부위까지 제거하는 단계와,Removing the first conductive layer and a specific portion of the planarized insulating layer by a planarization process after depositing the first conductive layer; 상기 평탄화된 결과물에 상기 콘택홀을 완전히 매립하기 위하여 제2도전층을 증착하고 평탄화공정으로 제2도전층을 평탄화하여 제1도전층과 제2도전층으로 이루어진 제2금속배선을 형성하는 단계Depositing a second conductive layer to completely fill the contact hole in the flattened resultant, and forming a second metal wiring including a first conductive layer and a second conductive layer by planarizing the second conductive layer. 로 이루어진 것을 특징으로 하는 반도체장치의 다층배선 형성방법.A method for forming a multilayer wiring of a semiconductor device, characterized in that consisting of. 제1항에 있어서, 상기 평탄화된 절연막은 10000Å정도의 두께로 두껍게 형성된 것을 특징으로 하는 반도체장치의 다층배선 형성방법.The method of claim 1, wherein the planarized insulating film is formed thick with a thickness of about 10000 GPa. 제1항에 있어서, 상기 제1도전층 및 제2도전층은 알루미늄인 것을 특징으로 하는 반도체장치의 다층배선 형성방법.The method of claim 1, wherein the first conductive layer and the second conductive layer are aluminum. 제1항에 있어서, 상기 평탄화 공정은 화학적기계연마방법에 의한 것임을 특징으로 하는 반도체장치의 다층배선 형성방법.The method of claim 1, wherein the planarization process is performed by a chemical mechanical polishing method.
KR1019970082303A 1997-12-31 1997-12-31 Method for forming mutilayer og semiconductor device KR100265972B1 (en)

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Citations (2)

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Publication number Priority date Publication date Assignee Title
JPH06268075A (en) * 1993-03-16 1994-09-22 Kawasaki Steel Corp Semiconductor device with multilayer interconnection structure and manufacture thereof
JPH07122639A (en) * 1993-10-28 1995-05-12 Kawasaki Steel Corp Formation of multilayer wiring structure

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06268075A (en) * 1993-03-16 1994-09-22 Kawasaki Steel Corp Semiconductor device with multilayer interconnection structure and manufacture thereof
JPH07122639A (en) * 1993-10-28 1995-05-12 Kawasaki Steel Corp Formation of multilayer wiring structure

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