KR20020043395A - 반도체 패키지 - Google Patents
반도체 패키지 Download PDFInfo
- Publication number
- KR20020043395A KR20020043395A KR1020000073055A KR20000073055A KR20020043395A KR 20020043395 A KR20020043395 A KR 20020043395A KR 1020000073055 A KR1020000073055 A KR 1020000073055A KR 20000073055 A KR20000073055 A KR 20000073055A KR 20020043395 A KR20020043395 A KR 20020043395A
- Authority
- KR
- South Korea
- Prior art keywords
- chip
- bonding
- semiconductor package
- heat slug
- wire
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
Claims (5)
- 베이스층의 수지층과, 이 수지층의 양면에 식각 처리된 전도성패턴과, 상기 전도성패턴의 일부를 외부로 노출시키면서 수지층상에 도포된 커버코트로 구성되어 있는 인쇄회로기판과; 상기 인쇄회로기판의 칩탑재영역에 접착수단에 의하여 상하로 적층 부착된 상부칩 및 하부칩과; 상기 상부칩과 하부칩의 본딩패드와, 인쇄회로기판의 와이어 본딩용 전도성패턴간에 연결된 와이어와; 상기 상부칩 및 하부칩, 와이어등을 몰딩하고 있는 수지로 구성된 반도체 패키지에 있어서,상기 상부칩과 하부칩 사이에 열전도성의 히트슬러그를 부착하고, 상부칩 및 하부칩의 파워 또는 그라운드용 와이어가 상기 히트 슬러그에 본딩되어 달성된 것을 특징으로 하는 반도체 패키지.
- 제 1 항에 있어서, 상기 히트 슬러그는 외곽면에 다수의 요홈이 등간격으로 배열된 판형으로 성형된 것을 특징으로 하는 반도체 패키지.
- 제 1 항에 있어서, 상기 히트 슬러그는 각 모서리에 수직 절곡된 연장단이 일체로 성형된 판형으로 성형된 것을 특징으로 하는 반도체 패키지.
- 제 1 항에 있어서, 상기 상부칩과 하부칩의 그라운드 본딩 영역에 해당되는 히트슬러그의 상면 일정부위에는 와이어와의 본딩 결합력이 우수한 재질로 도금된 것을 특징으로 하는 반도체 패키지.
- 제 1 항 또는 제 3 항에 있어서, 상기 히트슬러그의 연장단 하단끝은 마더보드에 실장되는 부분으로서 반도체 패키지의 저면으로 노출된 것을 특징으로 하는 반도체 패키지.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020000073055A KR100649869B1 (ko) | 2000-12-04 | 2000-12-04 | 반도체 패키지 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020000073055A KR100649869B1 (ko) | 2000-12-04 | 2000-12-04 | 반도체 패키지 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20020043395A true KR20020043395A (ko) | 2002-06-10 |
KR100649869B1 KR100649869B1 (ko) | 2006-11-24 |
Family
ID=27679428
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020000073055A KR100649869B1 (ko) | 2000-12-04 | 2000-12-04 | 반도체 패키지 |
Country Status (1)
Country | Link |
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KR (1) | KR100649869B1 (ko) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6857470B2 (en) | 2002-11-20 | 2005-02-22 | Samsung Electronics Co., Ltd. | Stacked chip package with heat transfer wires |
KR100533763B1 (ko) * | 2002-10-29 | 2005-12-06 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지 |
KR100712499B1 (ko) * | 2004-07-09 | 2007-05-02 | 삼성전자주식회사 | 열 배출 효율이 증대된 멀티 칩 패키지 및 그 제조방법 |
KR100714917B1 (ko) * | 2005-10-28 | 2007-05-04 | 삼성전자주식회사 | 차폐판이 개재된 칩 적층 구조 및 그를 갖는 시스템 인패키지 |
KR100876875B1 (ko) * | 2002-11-20 | 2008-12-31 | 주식회사 하이닉스반도체 | 강화된 열방출 능력을 갖는 칩 스택 패키지 |
CN100449754C (zh) * | 2002-09-18 | 2009-01-07 | 恩益禧电子股份有限公司 | 半导体器件及其制造方法 |
KR101481571B1 (ko) * | 2007-08-21 | 2015-01-14 | 삼성전자주식회사 | 반도체 패키지 장치 및 그의 제작방법 |
US9390992B2 (en) | 2013-07-11 | 2016-07-12 | Samsung Electronics Co., Ltd. | Semiconductor packages including a metal layer between first and second semiconductor chips |
CN112349662A (zh) * | 2019-08-07 | 2021-02-09 | 三星电机株式会社 | 半导体封装件 |
KR20210032081A (ko) * | 2019-09-16 | 2021-03-24 | 삼성전자주식회사 | 반도체 패키지 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100236016B1 (ko) * | 1996-12-16 | 1999-12-15 | 구자홍 | 적층형 반도체 패키지 및 그의 어셈블리 방법 |
KR200301799Y1 (ko) * | 1998-06-30 | 2003-06-18 | 주식회사 하이닉스반도체 | 멀티 칩 패키지 |
KR20020039010A (ko) * | 2000-11-20 | 2002-05-25 | 윤종용 | 방열판을 갖는 이중 칩 패키지 |
-
2000
- 2000-12-04 KR KR1020000073055A patent/KR100649869B1/ko active IP Right Grant
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7667312B2 (en) | 2002-09-18 | 2010-02-23 | Nec Electronics Corporation | Semiconductor device including a heat-transmitting and electromagnetic-noise-blocking substance and method of manufacturing the same |
CN100449754C (zh) * | 2002-09-18 | 2009-01-07 | 恩益禧电子股份有限公司 | 半导体器件及其制造方法 |
KR100899314B1 (ko) * | 2002-09-18 | 2009-05-27 | 엔이씨 일렉트로닉스 가부시키가이샤 | 반도체 장치 및 그 제조 방법 |
KR100533763B1 (ko) * | 2002-10-29 | 2005-12-06 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지 |
US6857470B2 (en) | 2002-11-20 | 2005-02-22 | Samsung Electronics Co., Ltd. | Stacked chip package with heat transfer wires |
KR100876875B1 (ko) * | 2002-11-20 | 2008-12-31 | 주식회사 하이닉스반도체 | 강화된 열방출 능력을 갖는 칩 스택 패키지 |
KR100712499B1 (ko) * | 2004-07-09 | 2007-05-02 | 삼성전자주식회사 | 열 배출 효율이 증대된 멀티 칩 패키지 및 그 제조방법 |
KR100714917B1 (ko) * | 2005-10-28 | 2007-05-04 | 삼성전자주식회사 | 차폐판이 개재된 칩 적층 구조 및 그를 갖는 시스템 인패키지 |
US7723836B2 (en) | 2005-10-28 | 2010-05-25 | Samsung Electronics Co., Ltd. | Chip stack structure having shielding capability and system-in-package module using the same |
KR101481571B1 (ko) * | 2007-08-21 | 2015-01-14 | 삼성전자주식회사 | 반도체 패키지 장치 및 그의 제작방법 |
US9390992B2 (en) | 2013-07-11 | 2016-07-12 | Samsung Electronics Co., Ltd. | Semiconductor packages including a metal layer between first and second semiconductor chips |
CN112349662A (zh) * | 2019-08-07 | 2021-02-09 | 三星电机株式会社 | 半导体封装件 |
KR20210032081A (ko) * | 2019-09-16 | 2021-03-24 | 삼성전자주식회사 | 반도체 패키지 |
Also Published As
Publication number | Publication date |
---|---|
KR100649869B1 (ko) | 2006-11-24 |
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