KR19990003156A - Manufacturing Method of Semiconductor Device - Google Patents
Manufacturing Method of Semiconductor Device Download PDFInfo
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- KR19990003156A KR19990003156A KR1019970026960A KR19970026960A KR19990003156A KR 19990003156 A KR19990003156 A KR 19990003156A KR 1019970026960 A KR1019970026960 A KR 1019970026960A KR 19970026960 A KR19970026960 A KR 19970026960A KR 19990003156 A KR19990003156 A KR 19990003156A
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- insulating film
- semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Abstract
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 식각 공정시 발생하는 마이크로 로딩 효과(Micro loading effect)를 감소시켜 양호한 패턴을 형성하는 반도체 소자의 제조 방법에 관한 것이다. 상기 목적을 달성하기 위하여, 본 발명에 따라 다양한 크기의 콘택을 갖고 소정 영역의 배선을 형성하는 반도체 소자를 제조하는 방법으로써, 하부에 소정의 패턴이 형성된 반도체 기판 상에 절연막을 형성하는 단계; 사진 공정을 통하여, 상기 절연막 상에 상기 소정 영역의 배선을 형성하기 위한 마스크 패턴을 형성하는 단계; 상기 절연막을 식각하는 식각 물질 중 미세 패턴에 대해 식각 속도가 빠른 제 1 식각 물질로, 상기 마스크 패턴으로 노출된 콘택 영역을 소정 깊이 식각하는 단계;및 상기 절연막을 식각하는 식각 물질 중 식각으로 노출되는 콘택면과의 식각 선택비가 양호한 제 2 식각 물질로, 나머지 콘택 영역을 식각하여 균일한 깊이의 다양한 콘택을 형성하는 단계를 포함하는 것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which a good pattern is formed by reducing a micro loading effect generated during an etching process. In order to achieve the above object, according to the present invention, a method for manufacturing a semiconductor device having a contact of various sizes and forming a wiring of a predetermined region, comprising: forming an insulating film on a semiconductor substrate having a predetermined pattern formed thereon; Forming a mask pattern on the insulating film to form wiring of the predetermined region through a photo process; Etching a contact depth exposed to the mask pattern with a first etching material having a high etching speed with respect to a fine pattern among the etching materials for etching the insulating film; and exposing the etching material among the etching materials for etching the insulating film; And a second etching material having a good etching selectivity with respect to the contact surface, wherein the remaining contact region is etched to form various contacts having a uniform depth.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 콘택 식각 공정시 발생하는 마이크로 로딩 효과를 감소시켜 양호한 패턴을 형성하는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which a good pattern is formed by reducing micro loading effects generated during a contact etching process.
일반적으로 식각 물질에 노출된 식각 면적 또는 패턴의 밀도에 따라 식각 속도가 달라지는 현상을 로딩 효과(Loading Effect)라고 한다. 즉, 동일한 밀도의 플라즈마로 식각을 하더라도 식각 물질에 노출되는 식각 면적 또는 패턴 크기가 다르면, 식각 공정 진행 중 식각 물질에 공급되는 밀도가 반응 면적에 따라 달라지게 된다. 그리고 아주 좁은 부위를 식각하는 경우 이와 같은 현상을 마이크로 로딩 효과(Micro loading effect)라고 한다. 이와 같은 현상은 주로 식각 공정시의 압력에 기인하며, 또한 부산물(By-product)의 발생에 영향을 받는다. 따라서, 콘택홀과 같이 개구해야 할 크기가 작아질수록 반응 부산물이 반도체 기판 상의 표면에 남을 확률이 상대적으로 커지고, 이런 부산물은 식각 속도를 저하시키게 된다.In general, a phenomenon in which the etching rate is changed according to the etching area or the density of the pattern exposed to the etching material is called a loading effect. That is, even when etching with the plasma having the same density, if the etching area or pattern size exposed to the etching material is different, the density supplied to the etching material during the etching process varies depending on the reaction area. In the case of etching a very narrow part, this phenomenon is called a micro loading effect. This phenomenon is mainly due to the pressure during the etching process and is also affected by the generation of by-products. Therefore, as the size of the opening to be smaller, such as a contact hole, becomes smaller, the probability that the reaction by-products remain on the surface of the semiconductor substrate is increased, and these by-products lower the etching rate.
도 1은 식각되는 콘택 크기에 대한 각 가스별 식각 속도를 나타낸다. 도 1에 나타난 바와 같이, 콘택의 크기가 미세해질수록 식각 가스에 따라 식각 속도가 다르다. 즉, CF4가스가 C2F6, C3F8또는 C4F8가스에 비해 미세 콘택에서 식각 속도가 빠르다.Figure 1 shows the etching rate for each gas for the contact size to be etched. As shown in FIG. 1, as the contact size becomes smaller, the etching rate varies according to the etching gas. That is, the CF 4 gas has a faster etching rate in the microcontact than C 2 F 6 , C 3 F 8 or C 4 F 8 gas.
종래에 금속 배선의 콘택홀을 형성하기 위하여, 일반적으로 고밀도 플라즈마를 사용하며 포토 레지스트 또는 하부의 폴리실리콘 등과의 식각 선택비를 고려하여 C2F6, C3F8또는 C4F8가스 등을 사용하였다. 그러나, 도 1에 도시된 바와 같이, 미세 콘택으로 갈수록 식각 속도가 저하된다. 또한, 높은 탄소 비율로 인해 많은 탄소계 폴리머가 발생된다. 도 2에 비교된 바와 같이, 반도체 기판(20) 상의 실리콘 산화막(21)에 콘택을 형성하는 경우, 마스크 패턴(22)의 개구된 영역이 작은 영역에서 식각 속도가 떨어져 마이크로 로딩 효과를 수반하게 되고, 이로 인해 미세 콘택이 원하는 대로 형성되지 않거나 콘택의 접촉 저항이 높아지게 된다.Conventionally, in order to form a contact hole of a metal wiring, a high density plasma is generally used, and a C 2 F 6 , C 3 F 8, or C 4 F 8 gas or the like is considered in consideration of an etching selectivity with a photoresist or polysilicon underneath. Was used. However, as shown in FIG. 1, the etching rate decreases toward the fine contact. In addition, high carbon ratios result in many carbon-based polymers. As compared with FIG. 2, in the case of forming a contact on the silicon oxide film 21 on the semiconductor substrate 20, the etching speed is decreased in the small area of the open area of the mask pattern 22, resulting in a micro loading effect. As a result, the fine contact is not formed as desired or the contact resistance of the contact is increased.
상기에서 언급한 바와 같이, 금속 배선의 큰택홀을 형성하기 위하여, 일반적으로 고밀도 플라즈마인 C2F6, C3F8또는 C4F8가스 등을 사용하였다. 그러나, 이러한 식각 가스는 미세 콘택에서 마이크로 로딩 효과를 수반하여, 미세 콘택이 제대로 형성되지 않거나 콘택면에서의 접촉 저항을 높이는 문제점이 있다.As mentioned above, in order to form a large tack hole of a metal wiring, a C 2 F 6 , C 3 F 8 or C 4 F 8 gas, which is generally a high density plasma, was used. However, such an etching gas is accompanied with a micro loading effect in the fine contact, there is a problem that the fine contact is not formed properly or to increase the contact resistance on the contact surface.
따라서, 본 발명은 다양한 크기의 콘택을 갖는 반도체 소자의 콘택 형성시 1차로 미세 패턴에서 식각 속도가 빠른 식각 물질을 사용하여 소정 부분 식각한 다음, 2차로 하부층과 식각 선택비가 양호한 식각 물질로 그 나머지를 식각함으로써 균일한 깊이로 식각된 콘택을 형성하는 반도체 소자의 제조 방법을 제공하는 데 그 목적이 있다.Therefore, the present invention is to etch a predetermined portion using an etching material having a high etching rate in the first fine pattern when forming a contact of a semiconductor device having a contact of various sizes, and then to the second layer as an etching material having a good etching selectivity. An object of the present invention is to provide a method for manufacturing a semiconductor device by forming a contact etched to a uniform depth by etching.
도 l은 식각되는 콘택 크기에 대한 각 가스별 식각 속도를 나타낸 그래프.Figure 1 is a graph showing the etching rate for each gas relative to the size of the contact etched.
도 2는 종래 기술에 따른 반도체 소자의 콘택을 나타내는 단면도.2 is a cross-sectional view showing a contact of a semiconductor device according to the prior art.
도 3A 내지 도 3C는 본 발명의 실시예에 따른 반도체 소자의 콘택의 제조 공정을 나타내는 공정 단면도.3A to 3C are cross-sectional views illustrating a process for manufacturing a contact of a semiconductor device according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
20, 30 : 반도체 기판, 21, 31 : 실리콘 산화막, 22, 32 : 마스크 패턴20, 30: semiconductor substrate, 21, 31: silicon oxide film, 22, 32: mask pattern
상기 목적을 달성하기 위하여, 본 발명에 따라 다양한 크기의 콘택을 갖고 소정 영역의 배선을 형성하는 반도체 소자를 제조하는 방법으로써, 하부에 소정의 패턴이 형성된 반도체 기판 상에 절연막을 형성하는 단계; 사진 공정을 통하여, 상기 절연막 상에 상기 소정 영역의 배선을 형성하기 위한 마스크 패턴을 형성하는 단계; 상기 절연막을 식각하는 식각 물질 중 미세 패턴에 대해 식각 속도가 빠른 제 1 식각 물질로, 상기 마스크 패턴으로 노출된 콘택 영역을 소정 깊이 식각하는 단계 ; 및 상기 절연막을 식각하는 식각 물질 중 식각으로 노출되는 콘택면과의 식각 선택비가 양호한 제 2 식각 물질로, 나머지 콘택 영역을 식각하여 균일한 깊이의 다양한 콘택을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, according to the present invention, a method for manufacturing a semiconductor device having a contact of various sizes and forming a wiring of a predetermined region, comprising: forming an insulating film on a semiconductor substrate having a predetermined pattern formed thereon; Forming a mask pattern on the insulating film to form wiring of the predetermined region through a photo process; Etching a contact region exposed by the mask pattern to a first depth using a first etching material having a high etching speed with respect to a fine pattern among etching materials for etching the insulating layer; And a second etching material having a good etching selectivity with respect to a contact surface exposed through etching among the etching materials for etching the insulating layer, and etching the remaining contact regions to form various contacts having a uniform depth. .
[실시예]EXAMPLE
이하, 첨부된 도면을 참조로하여 본 발명의 제 1 실시예를 설명한다.Hereinafter, a first embodiment of the present invention will be described with reference to the accompanying drawings.
도 3A 내지 도 3C는 본 발명의 실시예에 따른 반도체 소자의 콘택의 제조 공정을 나타내는 공정 단면도로써, 반도체 기판(30) 상에 실리콘 산화막(SiO2)(31)이 형성되어 있고 그 상부에 서로 다른 크기의 콘택을 형성하기 위한 마스크 패턴(32)이 형성되어 있다. 도 1에 도시된 바와 같이 콘택 크기가 약 1 마이크로 이하에서는 마이크로 로딩 효과가 나타나게 된다. 따라서, 도 3A에 도시된 바와 같이 미세 콘택(a)과 미세 크기의 이상의 비교적 넓은 콘택(b)을 동시에 형성하고자 하는 경우, 식각 단계를 두 단계로 나누어 식각한다. 즉, 1차로 미세 패턴에 대해 식각 속도가 빠른 식각 물질을 사용하여 역 마이크로 로딩 효과를 유발한 다음, 2차로 콘택홀 형성시 노출되는 콘택면과의 식각 선택비가 양호하면서 비교적 넓은 패턴에 대해 식각 속도가 양호한 식각 물질로 남은 부분을 식각하여 콘택홀을 완성한다.3A to 3C are cross-sectional views illustrating a process for manufacturing a contact of a semiconductor device according to an exemplary embodiment of the present invention, in which a silicon oxide film (SiO 2 ) 31 is formed on a semiconductor substrate 30 and formed on top of each other. Mask patterns 32 for forming contacts of different sizes are formed. As shown in FIG. 1, when the contact size is about 1 micro or less, a micro loading effect appears. Therefore, when forming the micro contact (a) and the relatively wide contact (b) of the fine size or more as shown in Figure 3A at the same time, the etching step is etched by dividing into two steps. That is, by using an etching material having a high etching speed for the first fine pattern, the reverse micro loading effect is induced, and then the etching rate for the relatively wide pattern with good etching selectivity with the contact surface exposed when forming the second contact hole is good. Etch the remaining portion with a good etching material to complete the contact hole.
따라서, 도 1에서와 같이 미세 패턴에 대해 식각 속도가 빠른 CF4계통의 플라즈마 가스를 이용하여, 상기 실리콘 산화막(2l)을 소정 깊이 식각한다. 이 때, 1차 식각 깊이는 대체로 전체의 60∼80% 정도 한다. CF4계통의 가스는 불소에 비해 탄소의 함유량이 적기 때문에 플라즈마 내 불소의 라디칼 농도를 높혀 식각 진행 중 하부에 쌓이는 탄소계 폴리머의 양을 줄임으로써, 식각 속도는 콘택 내 이온 전류 밀도에 의존하게 되고 미세 콘택일수록 집속된 이온의 다단계 충돌에 의해 식각 속도가 커지는 경향을 보이게 된다. 따라서, CF4계통의 가스로 식각하는 경우 도 3B와 같이 미세 콘택(a)이 더 깊이 식각이 된다. 이 때, 식각 속도를 조절하기 위하여 소스 파워는 1500∼3000W, 바이어스 파워는 100W 이상으로 하여 식각 속도를 6000Å/분 이상되게 한다. 또한 압력이 증가할수록 식각 속도가 증가하므로, 공정 압력은 5∼15mTorr 정도로 유지하고, 플라즈마 상태를 안정화하기 위해 아르곤 가스를 5∼50% 정도 첨가한다. 또한, 미세 콘택 내부에서의 불균일한 식각으로 인해 콘택 하부의 가장자리에 존재할 수 있는 트렌치를 방지하기 위하여 산소 가스를 0∼50% 정도 첨가할 수 있다.Therefore, as shown in FIG. 1, the silicon oxide film 2l is etched to a predetermined depth by using a CF 4 system plasma gas having a high etching rate with respect to the fine pattern. At this time, the primary etching depth is approximately 60 to 80% of the total. Since the gas of CF 4 system has less carbon content than fluorine, the etching rate is dependent on the ion current density in the contact by increasing the radical concentration of fluorine in the plasma to reduce the amount of carbon-based polymer accumulated at the bottom during the etching process. As the microcontact becomes larger, the etching rate tends to increase due to the multi-stage collision of the focused ions. Therefore, when etching with CF 4 gas, the fine contact (a) is more deeply etched as shown in FIG. 3B. At this time, in order to adjust the etching speed, the source power is 1500 to 3000W and the bias power is 100W or more so that the etching speed is 6000 mW / min or more. In addition, since the etching rate increases as the pressure increases, the process pressure is maintained at about 5 to 15 mTorr, and about 5 to 50% of argon gas is added to stabilize the plasma state. In addition, oxygen gas may be added in an amount of about 0 to 50% in order to prevent trenches that may exist at the edge of the lower portion of the contact due to uneven etching inside the fine contact.
이와 같이, 1차로 CF4계통의 플라즈마를 이용하여 식각한 다음, 불소에 내해 탄소량이 많아 하부층인 폴리실리콘막과 식각 선택비가 좋은 CHF3, C2F6, C3F8또는 C4F8가스 등을 사용하여 나머지 부분을 식각해 냄으로써 도 3C와 같이 균일한 식각 깊이를 갖는 콘택홀을 형성한다. 이와 같이, 두 단계의 식각 방법으로 콘택을 형성하는 경우, 종래의 마이크로 로딩 효과를 고려한 과도 식각이 필요하지 않으므로 공정 시간을 단축할 수 있다.As such, the first etching is performed using a plasma of CF 4 system, and the fluorine-resistant polysilicon film and the etch selectivity of CHF 3 , C 2 F 6 , C 3 F 8, or C 4 F 8 which have a large amount of carbon in the fluorine The remaining portion is etched using gas or the like to form a contact hole having a uniform etching depth as shown in FIG. 3C. As such, when the contact is formed by the two-step etching method, the process time may be shortened because the excessive etching considering the conventional micro loading effect is not necessary.
이상에서 설명한 바와 같이, 본 발명은 다양한 크기의 콘택을 갖는 반도체 소자의 콘택 형성시 1차로 미세 패턴에서 식각 속도가 빠른 식각 물질을 사용하여 소정 부분 식각한 다음, 2차로 하부층과 식각 선택비가 양호한 식각 물질로 그 나머지를 식각함으로써 균일한 깊이로 식각된 콘택을 형성할 수 있다.As described above, according to the present invention, when forming a contact of a semiconductor device having various sizes of contacts, a predetermined partial etching is performed using an etching material having a high etching speed in a first fine pattern, and then etching is performed in a second lower layer and an etching selectivity with good etching selectivity. Etching the rest with the material can form an etched contact to a uniform depth.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.
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KR100437832B1 (en) * | 2001-12-28 | 2004-06-30 | 주식회사 하이닉스반도체 | method for forming metal line of semiconductor device |
KR100634267B1 (en) * | 2000-09-20 | 2006-10-16 | 삼성전자주식회사 | Method for forming of device isolation region in a semiconductor device |
JP2010245101A (en) * | 2009-04-01 | 2010-10-28 | Hitachi High-Technologies Corp | Dry etching method |
CN110970297A (en) * | 2018-09-29 | 2020-04-07 | 长鑫存储技术有限公司 | Compensation etching method and structure, semiconductor device and preparation method thereof |
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KR100843236B1 (en) | 2007-02-06 | 2008-07-03 | 삼성전자주식회사 | Method of forming fine patterns of semiconductor device using double patterning process |
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KR100634267B1 (en) * | 2000-09-20 | 2006-10-16 | 삼성전자주식회사 | Method for forming of device isolation region in a semiconductor device |
KR100437832B1 (en) * | 2001-12-28 | 2004-06-30 | 주식회사 하이닉스반도체 | method for forming metal line of semiconductor device |
JP2010245101A (en) * | 2009-04-01 | 2010-10-28 | Hitachi High-Technologies Corp | Dry etching method |
US8207066B2 (en) | 2009-04-01 | 2012-06-26 | Hitachi High-Technologies Corporation | Dry etching method |
CN110970297A (en) * | 2018-09-29 | 2020-04-07 | 长鑫存储技术有限公司 | Compensation etching method and structure, semiconductor device and preparation method thereof |
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