KR100223869B1 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
- Publication number
- KR100223869B1 KR100223869B1 KR1019960043855A KR19960043855A KR100223869B1 KR 100223869 B1 KR100223869 B1 KR 100223869B1 KR 1019960043855 A KR1019960043855 A KR 1019960043855A KR 19960043855 A KR19960043855 A KR 19960043855A KR 100223869 B1 KR100223869 B1 KR 100223869B1
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- South Korea
- Prior art keywords
- semiconductor device
- manufacturing
- film
- oxide film
- nitride film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 150000004767 nitrides Chemical class 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 abstract description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 5
- 229920000642 polymer Polymers 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000005347 demagnetization Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Inorganic Chemistry (AREA)
- Physics & Mathematics (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 고집적 소자에서 충분한 라인(Line) 영역을 확보하기 위한 반도체 소자의 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device for securing a sufficient line area in a highly integrated device.
이를 위한 본 발명의 반도체 소자의 제조 방법은 기판상에 차례로 산화막 및 질화막을 형성하는 단계, 상기 산화막 및 질화막을 CF4와 CHF3와 N2및 Ar 가스를 사용하여 소정 부위에만 남도록 선택적으로 식각하는 단계를 포함하여 이루어짐을 특징으로 한다.A method for manufacturing a semiconductor device of the present invention to achieve this the step, the oxide film and the nitride film to form an oxide film and a nitride film in order on a substrate by using CF 4 and CHF 3, and N 2, and Ar gas to leave only a predetermined portion for selectively etching The method comprising the steps of:
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 고집적 소자에서 충분한 라인(Line) 영역을 확보하기 위한 반도체 소자의 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device for securing a sufficient line area in a highly integrated device.
디바이스(Device)의 집적도가 커질수록 디자인 룰(Design Rule)이 작아짐에 따라 라인 혹은 스페이스(Space)의 영역 확보가 어렵게 되었다.As the degree of integration of a device increases, the design rule becomes smaller and it becomes difficult to secure a line or a space area.
이하 첨부된 도면을 참고하여 종래 기술에 따른 반도체 소자의 제조 방법을 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device according to the related art will be described with reference to the accompanying drawings.
도1a 내지 도1b는 종래 기술에 따른 절연막 식각을 나타낸 공정 단면도이다.1A to 1B are cross-sectional views illustrating a process of etching an insulating film according to the prior art.
도1a에서와 같이, 반도체 기판(11)상에 차례로 산화막(12)과, 질화막(13)과, 감광막(14)을 형성한 다음, 상기 감광막(14)을 라인 혹은 스페이스가 형성될 부위에만 남도록 선택적으로 노광 및 현상한다.The oxide film 12, the nitride film 13 and the photoresist film 14 are sequentially formed on the semiconductor substrate 11 as shown in FIG. 1A so that the photoresist film 14 is left only on a portion where a line or a space is to be formed. Selectively exposed and developed.
도1b에서와 같이, 상기 선택적으로 노광 및 현상된 감광막(14)을 마스크로 이용하여 차례로 상기 질화막(13)과 산화막(12)을 선택적으로 식각한다. 여기서 식각 방법은 CF4/CHF3/Ar 가스를 사용하는 RIE(Reactive Ion Etching) 및 MERIE(Magnetic Enhancement RIE) 장비를 이용하거나, CHF3/CH4/O2/Ar 가스를 사용하는 RIE 및 MERIE 장비를 이용한다. 이러한 방법의 첫째 방법에서는 CFX계열의 폴리머가 상기 시각된 산화막(12)과 질화막(13)의 측벽에 발생되어 상기 산화막(12)과 질화막(13) 측벽을 보호하므로 라인 혹은 스페이스의 크기를 조절하고, 둘째 방법에서는 CFX계열의 폴리머와 O2가스의 화학 반응을 유도하여 라인 혹은 스페이스의 크기를 조절한다.1B, the nitride film 13 and the oxide film 12 are selectively etched successively using the selectively exposed and developed photoresist film 14 as a mask. The etching method is CF 4 / CHF 3 / (Reactive Ion Etching) RIE using an Ar gas and MERIE (Magnetic Enhancement RIE) using the equipment, or, CHF 3 / CH 4 / O RIE and MERIE using the 2 / Ar gas Equipment. In the first method of this method, the CF X series polymer is generated on the side wall of the oxide film 12 and the nitride film 13 to protect the oxide film 12 and the side wall of the nitride film 13, In the second method, the chemical reaction of the CF X series polymer and O 2 gas is induced to adjust the size of the line or space.
종래 기술에 따른 반도체 소자의 제조 방법은 라인 혹은 스페이스를 형성하기 위해 절연막을 CHF3/CF4/Ar 가스를 이용하여 건식 식각을 할 때, CFX계열의 폴리머가 적게 발생되거나 화학 반응이 빠르게 되어 등방성 식각이 되므로 CD 바이어스(Critical Demension Bias)를 크게 하는데 한계가 있다는 문제점이 있었다.In the conventional method of fabricating a semiconductor device, when the insulating film is dry-etched using CHF 3 / CF 4 / Ar gas to form a line or a space, a small amount of the polymer of the CF x series is generated, There is a limitation in increasing CD bias (critical demagnetization bias) because of isotropic etching.
본 발명은 상기 문제점을 해결하기 위해 안출한 것으로, 라인 혹은 스페이스를 형성하기 위해 절연막을 CF4/CHF3/N2혹은 CHF3/CF4/N2/Ar 가스를 이용하여 건식 식각하므로 CD 바이어스를 크게 하는 반도체 소자의 제조 방법을 제공 하는데 그 목적이 있다.The present invention has been devised in order to solve the above problems, and it is an object of the present invention to dry etch an insulating film using CF 4 / CHF 3 / N 2 or CHF 3 / CF 4 / N 2 / Ar gas to form lines or spaces, And a method of manufacturing a semiconductor device.
도1a 내지 도1b는 종래 기술에 따른 절연막 식각을 나타낸 공정 단면도1A to 1B are cross-sectional views showing a process of etching an insulating film according to the related art
도2a 내지 도2b는 본 발명의 실시예에 따른 절연막 식각을 나타낸 공정단면도FIGS. 2A and 2B are cross-sectional views illustrating a process of etching an insulating film according to an embodiment of the present invention
* 도면의 주요부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS
31 : 반도체 기판 32 : 산화막31: semiconductor substrate 32: oxide film
33 : 질화막 34 : 감광막33: nitride film 34: photosensitive film
본 발명의 반도체 소자의 제조 방법은 기판상에 차례로 산화막 및 질화막을 형성하는 단계, 상기 산화막 및 질화막을 CF4와 CHF3와 N2및 Ar 가스를 사용하여 소정 부위에만 남도록 선택적으로 식각하는 단계를 포함하여 이루어짐을 특징으로 한다.A method for manufacturing a semiconductor device of the present invention is a step of forming an oxide film and a nitride film in order on a substrate, the oxide film and the nitride film using the CF 4 and CHF 3, and N 2, and Ar gas is a step of selectively etching to leave only a predetermined portion .
상기와 같은 본 발명에 따른 반도체 소자의 제조 방법의 바람직한 실시예를 첨부된 도면의 참조하여 상세히 설명하면 다음과 같다.Hereinafter, preferred embodiments of a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도2a 내지 도2b는 본 발명의 실시예에 따른 절연막 식각을 나타낸 공정 단면도이다.2A and 2B are cross-sectional views illustrating an etching process of an insulating layer according to an embodiment of the present invention.
도2a에서와 같이, 반도체 기판(31)상에 산화막(32)과, 질화막(33)과, 감광막(34)을 차례로 형성한 다음, 상기 감광막(34)을 라인 혹은 스페이스가 형성될 부위에만 남도록 선택적으로 노광 및 현상한다.2A, an oxide film 32, a nitride film 33, and a photoresist film 34 are sequentially formed on a semiconductor substrate 31, and then the photoresist film 34 is left only on a portion where a line or a space is to be formed. Selectively exposed and developed.
도2b에서와 같이, 상기 선택적으로 노광 및 현상된 감광막(34)을 마스크로 이용하여 차례로 상기 질화막(33)과 산화막(32)을 선택적으로 식각한다. 여기서 식각 방법은 CF4/CHF3/N2혹은 CF4/CHF3/N2/Ar 가스를 사용하는 RIE 및 MERIE 장비를 이용한다. 이때 N2가스는 100∼1000sccm의 유량을 가지며, 상기 N2가스가 플라즈마에서 해리되어 라디컬(Radical) 혹은 이온 형태로 되고, 상기 라디컬 혹은 이온형태의 N2가스에 의해 상기 산화막(32)과 질화막(33)을 이방성 식각하는데, (CFX)N의 폴리머가 상기 식각된 산화막(32)과 질화막(33)의 측벽에 다량으로 발생되어 상기 산화막(32)과 질화막(33) 측벽을 보호하므로 라인 혹은 스페이스의 크기를 조절한다.As shown in FIG. 2B, the nitride film 33 and the oxide film 32 are selectively etched successively using the selectively exposed and developed photoresist film 34 as a mask. Here, the etching method uses RIE and MERIE equipment using CF 4 / CHF 3 / N 2 or CF 4 / CHF 3 / N 2 / Ar gas. At this time, the N 2 gas has a flow rate of 100 to 1000 sccm, and the N 2 gas dissociates from the plasma to become a radical or an ion type, and the oxide film 32 is formed by N 2 gas of the radical or ion type. A polymer of (CF X ) N is generated in a large amount on the side walls of the etched oxide film 32 and the nitride film 33 to protect the side walls of the oxide film 32 and the nitride film 33 Adjust the size of lines or spaces.
상기 도2에서와 같이 (CFX)N의 폴리머가 다량으로 발생하고 화학 반응이 늦기 때문에 상기 산화막과 질화막을 이방성 식각하여 상기 산화막과 질화막의 하부 영역이 상부 영역보다 적게 식각되므로 충분한 라인 혹은 스페이스 영역을 확보한다.As shown in FIG. 2, since a large amount of (CF X ) N polymer is generated and the chemical reaction is delayed, the oxide film and the nitride film are anisotropically etched so that the lower region of the oxide film and the nitride film is less etched than the upper region, .
본 발명의 반도체 소자의 제조 방법은 절연막을 CF4/CHF3/N2혹은 CF4/CHF3/N2/Ar 가스로 건식 식각하여 큰 CD 바이어스를 가지므로 충분한 라인 또는 스페이스 영역을 확보하는 효과가 있다.The method of manufacturing a semiconductor device according to the present invention has a large CD bias by dry etching the insulating film with CF 4 / CHF 3 / N 2 or CF 4 / CHF 3 / N 2 / Ar gas, .
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960043855A KR100223869B1 (en) | 1996-10-04 | 1996-10-04 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960043855A KR100223869B1 (en) | 1996-10-04 | 1996-10-04 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19980025634A KR19980025634A (en) | 1998-07-15 |
| KR100223869B1 true KR100223869B1 (en) | 1999-10-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960043855A KR100223869B1 (en) | 1996-10-04 | 1996-10-04 | Manufacturing method of semiconductor device |
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| KR (1) | KR100223869B1 (en) |
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- 1996-10-04 KR KR1019960043855A patent/KR100223869B1/en not_active IP Right Cessation
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| Publication number | Publication date |
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| KR19980025634A (en) | 1998-07-15 |
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