KR100587039B1 - Manufacturing method for contact hole in semiconductor device - Google Patents

Manufacturing method for contact hole in semiconductor device Download PDF

Info

Publication number
KR100587039B1
KR100587039B1 KR1019990051280A KR19990051280A KR100587039B1 KR 100587039 B1 KR100587039 B1 KR 100587039B1 KR 1019990051280 A KR1019990051280 A KR 1019990051280A KR 19990051280 A KR19990051280 A KR 19990051280A KR 100587039 B1 KR100587039 B1 KR 100587039B1
Authority
KR
South Korea
Prior art keywords
contact hole
etching
semiconductor device
forming
etching process
Prior art date
Application number
KR1019990051280A
Other languages
Korean (ko)
Other versions
KR20010047180A (en
Inventor
윤한식
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1019990051280A priority Critical patent/KR100587039B1/en
Publication of KR20010047180A publication Critical patent/KR20010047180A/en
Application granted granted Critical
Publication of KR100587039B1 publication Critical patent/KR100587039B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Abstract

본 발명은 반도체 장치의 콘택홀 형성방법에 관한 것으로, 종래 콘택홀 형성방법은 상기한 바와 같이 종래 반도체 장치의 콘택홀 형성방법은 CF4와 CHF3의 유량비를 이용하여 선택비를 조절함으로써, 그 유량비를 조절하기가 용이하지 않아 하부막이 식각되는 문제점이 있었다. 이와 같은 문제점을 감안한 본 발명은 산화막의 상부에 포토레지스트 패턴을 형성하고, 그 포토레지스트 패턴을 식각마스크로 하는 건식식각공정으로 상기 산화막 하부의 하지층의 일부를 노출시키는 콘택홀을 형성하는 반도체 장치의 콘택홀 제조방법에 있어서, 상기 건식식각공정은 CHxFy, O2, Ar을 식각가스로 하는 식각공정으로 콘택홀을 형성하는 제1식각단계와; CxFy, O2, Ar을 식각가스로 하는 식각공정으로 상기 형성된 콘택홀과 하지층의 선택비를 높이며, 그 콘택홀의 측면 형상이 수직을 이루도록 하는 제2식각단계로 구성되어 1차적으로 CHxFy, O2, Ar을 식각가스로 사용하는 식각공정으로 콘택홀의 대부분을 형성한 후, 2차적으로 CxFy, O2, Ar을 사용하는 식각공정으로 하지막과의 선택비를 높임과 아울러 콘택홀의 형상이 수직으로 형성되도록 함으로써, 반도체 장치의 특성 열화를 방지하는 효과가 있다.The present invention relates to a method for forming a contact hole in a semiconductor device, and the method for forming a contact hole in a conventional semiconductor device, as described above, in the conventional method for forming a contact hole in a semiconductor device by adjusting the selectivity by using a flow rate ratio of CF 4 and CHF 3 . It was not easy to adjust the flow rate ratio there was a problem that the lower film is etched. In view of the above problems, the present invention provides a semiconductor device in which a photoresist pattern is formed on an oxide film, and a contact hole for exposing a part of the underlying layer under the oxide film is formed by a dry etching process using the photoresist pattern as an etching mask. In the contact hole manufacturing method of claim 1, wherein the dry etching process comprises a first etching step of forming a contact hole in the etching process using the etching gas CHxFy, O 2 , Ar; Etching process using CxFy, O 2 , Ar as an etching gas to increase the selectivity of the formed contact hole and the underlying layer, and consists of a second etching step to make the side shape of the contact hole perpendicular to the primary CHxFy, O After forming most of the contact hole in the etching process using 2 , Ar as an etching gas, the etching process using CxFy, O 2 , and Ar secondly increases the selectivity with the underlying film and the shape of the contact hole is vertical. By forming it, the deterioration of characteristics of the semiconductor device can be prevented.

Description

반도체 장치의 콘택홀 형성방법{MANUFACTURING METHOD FOR CONTACT HOLE IN SEMICONDUCTOR DEVICE}MANUFACTURING METHOD FOR CONTACT HOLE IN SEMICONDUCTOR DEVICE}

도1a 내지 도1c는 종래 반도체 장치의 콘택홀 제조공정 수순단면도.1A to 1C are cross-sectional views of a process for manufacturing a contact hole in a conventional semiconductor device.

도2a 내지 도2d는 본 발명 반도체 장치의 콘택홀 제조공정 수순단면도.2A to 2D are cross-sectional views of a process for manufacturing a contact hole in a semiconductor device of the present invention.

***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***

1:기판 2:질화막1: Substrate 2: Nitride

3:산화막 PR:포토레지스트3: oxide film PR: photoresist

본 발명은 반도체 장치의 콘택홀 형성방법에 관한 것으로, 특히 고밀도 플라즈마 소스를 사용하여 높은 포토레지스트 선택비, 고 해상도를 갖는 깊은 콘택홀을 형성하는 반도체 장치의 콘택홀 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device for forming a deep contact hole having a high photoresist selectivity and a high resolution using a high density plasma source.

일반적으로 반도체 메모리에서 커패시터의 높이가 높아짐에 따라 금속배선과 반도체 소자의 특정영역을 연결하기 위한 콘택홀의 깊이가 깊어지게 되며, 그 깊이가 더욱 깊어진 콘택홀을 형성하기 위해서 일반적인 콘택홀 형성공정을 사용하면 그 콘택홀이 원하는 패턴으로 형성되지 않을 수 있으며, 이와 같은 종래 반도체 장치의 콘택홀 형성방법을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.In general, as the height of a capacitor increases in a semiconductor memory, a contact hole for connecting a metal wiring and a specific region of a semiconductor device becomes deeper, and a general contact hole forming process is used to form a deeper contact hole. If not, the contact hole may not be formed in a desired pattern, which will be described in detail with reference to the accompanying drawings.

도1a 내지 도1c는 종래 반도체 메모리의 콘택홀 제조공정 수순단면도로서, 이에 도시한 바와 같이 반도체 소자가 형성된 기판(1)의 상부에 질화막(2)과 산화막(3)이 순차적으로 증착되어 있는 상태에서 상기 산화막(3)의 상부에 그 산화막(3)의 상부일부를 노출시키는 포토레지스트(PR) 패턴을 형성하는 단계(도1a)와; 상기 포토레지스트(PR) 패턴을 식각마스크로 하며, Ar/CxFy/CxHyFz 혼합가스를 식각가스로 사용하는 건식식각공정으로 상기 노출된 산화막(3)을 식각하여 콘택홀을 형성하는 단계(도1b)와; 상기 포토레지스트(PR) 패턴을 제거하는 단계(도1c)로 구성된다.1A to 1C are cross-sectional views of a process for manufacturing a contact hole in a conventional semiconductor memory, in which a nitride film 2 and an oxide film 3 are sequentially deposited on an upper portion of a substrate 1 on which a semiconductor device is formed. Forming a photoresist (PR) pattern on the oxide film 3, the upper portion of the oxide film 3 being exposed (FIG. 1A); Forming a contact hole by etching the exposed oxide layer 3 by a dry etching process using the photoresist (PR) pattern as an etching mask and using an Ar / CxFy / CxHyFz mixed gas as an etching gas (FIG. 1B). Wow; Removing the photoresist (PR) pattern consists of a step (Fig. 1c).

이하, 상기와 같이 구성된 종래 반도체 장치의 콘택홀 형성방법을 좀 더 상세 히 설명한다.Hereinafter, a method of forming a contact hole in a conventional semiconductor device configured as described above will be described in more detail.

먼저, 도1a에 도시한 바와 같이 기판(1)의 상부에 반도체 소자를 형성하고, 그 기판(1)의 상부에 산화막등의 절연막(도면 미도시)을 증착한 후, 커패시터 형성공정에서 식각방지막으로 사용되는 질화막(2)을 증착한다.First, as shown in FIG. 1A, a semiconductor device is formed on the substrate 1, an insulating film (not shown) such as an oxide film is deposited on the substrate 1, and then an etch stop layer is formed in the capacitor forming process. The nitride film 2 used as is deposited.

그 다음, 상기 질화막(2)의 상부전면에 산화막(3)을 증착하고, 그 산화막(3)의 상부전면에 포토레지스트(PR)를 도포하고 노광 및 현상하여 상기 산화막(3)의 상부일부를 노출시키는 패턴을 형성한다.Next, an oxide film 3 is deposited on the upper surface of the nitride film 2, and a photoresist PR is coated on the upper surface of the oxide film 3, and the light and the exposed light are developed to expose a portion of the upper portion of the oxide film 3. Form a pattern to expose.

그 다음, 도1b에 도시한 바와 같이 상기 형성한 포토레지스트 패턴을 식각마스크로 사용하는 식각공적으로 상기 노출된 산화막(3)을 식각하여 콘택홀을 형성한다.Next, as shown in FIG. 1B, the exposed oxide layer 3 is etched by using the formed photoresist pattern as an etching mask to form a contact hole.

이때 식각방법은 반응성 이온식각 또는 플라즈마를 이용하는 플라즈마 장치를 이용하여 식각을 행하며, CF4와 CHF3 두 가스의 유량비를 조절하여 선택비를 조절하여 식각을 실시한다. 이때 하부막인 질화막(2)과 산화막(3)의 선택비를 조절하기 힘들기 때문에 산화막(3)에 콘택홀을 형성할때 질화막(2)이 300Å이하로 식각되도록 조정하기가 용이하지 않다.At this time, the etching method is performed by using a plasma apparatus using reactive ion etching or plasma, and etching is performed by adjusting the selectivity by adjusting the flow rate ratio of the two gases CF 4 and CHF 3 . At this time, it is difficult to control the selectivity between the nitride film 2 and the oxide film 3, which are the lower films, so that the nitride film 2 is not easily etched at 300 kPa or less when the contact hole is formed in the oxide film 3.

그 다음, 도1c에 도시한 바와 같이 포토레지스트(PR) 패턴을 제거한다.Then, as shown in Fig. 1C, the photoresist (PR) pattern is removed.

이와 같은 식각공정으로 선택비가 7:1 이상인 경우 홀 프로파일(HOLE PROFILE)에 보잉(BOWING)이 발생하여 도면에 도시한 바와 같이 균일한 형상 또는 균일한 크기의 콘택홀을 형성할 수 없게 된다.When the selectivity is 7: 1 or more due to such an etching process, bowing occurs in the hole profile, so that a contact hole having a uniform shape or a uniform size cannot be formed as shown in the drawing.

상기한 바와 같이 종래 반도체 장치의 콘택홀 형성방법은 CF4와 CHF3의 유량비를 이용하여 선택비를 조절함으로써, 그 유량비를 조절하기가 용이하지 않아 하부막이 식각되는 문제점이 있었다.As described above, the conventional method for forming a contact hole in a semiconductor device has a problem that the lower layer is etched because it is not easy to adjust the flow rate ratio by adjusting the selectivity ratio using the flow rate ratios of CF 4 and CHF 3 .

이와 같은 문제점을 감안한 본 발명은 유량비의 조절을 용이하게 하여 콘택홀 형성시 하지막이 식각되는 것을 방지할 수 있는 반도체 장치의 콘택홀 제조방법을 제공함에 그 목적이 있다.In view of the above problems, an object of the present invention is to provide a method for manufacturing a contact hole in a semiconductor device that can easily control the flow rate ratio and prevent the underlying film from being etched when forming the contact hole.

상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 장치의 콘택홀 제조방법은 산화막의 상부에 포토레지스트 패턴을 형성하고, 그 포토레지스트 패턴을 식각마스크로 하는 건식식각공정으로 상기 산화막 하부의 하지층의 일부를 노출시키는 콘택홀을 형성하는 반도체 장치의 콘택홀 제조방법에 있어서, 상기 건식식각공정은 CHxFy, O2, Ar을 식각가스로 하되 02와 CHxFy의 유량비를 1:2 내지 1:5의 범위로 식각하여 콘택홀을 형성하는 제1식각단계와; CxFy, O2, Ar을 식각가스로 하되 02와 CxFy의 유량비를 1:2 내지 1:4의 범위로 하여 상기 형성된 콘택홀과 하지층의 선택비를 높여 상기 콘택홀의 측면 형상이 수직을 이루도록 하는 제2식각단계로 이루어진다.
이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.In the method of manufacturing a contact hole of a semiconductor device according to the present invention for achieving the above object, a photoresist pattern is formed on an oxide film, and the underlying layer under the oxide film is subjected to a dry etching process using the photoresist pattern as an etching mask. In the method for manufacturing a contact hole of a semiconductor device to form a contact hole for exposing a portion of the, the dry etching process using a CHxFy, O 2 , Ar as an etching gas, the ratio of the flow rate of 0 2 and CHxFy 1: 2 to 1: 5 A first etching step of forming a contact hole by etching in the range of; CxFy, O 2 , Ar as an etching gas, but the flow rate ratio of 0 2 and CxFy in the range of 1: 2 to 1: 4 to increase the selectivity of the formed contact hole and the underlying layer so that the side shape of the contact hole is vertical. The second etching step is performed.
If described in detail with reference to the accompanying drawings, the present invention as follows.

도2a 내지 도2d는 본 발명 반도체 장치의 콘택홀 제조공정 수순단면도로서, 이에 도시한 바와 같이 반도체 소자가 형성된 기판(1)의 상부에 질화막(2)과 산화막(3)이 순차적으로 증착된 상태에서, 상기 산화막(3)의 상부에 포토레지스트(PR)를 도포하고, 상기 산화막(3)의 상부일부를 노출시키는 패턴을 형 성하는 단계(도2a)와; 상기 포토레지스트(PR) 패턴을 식각마스크로 사용하며, CHxFy, O2, Ar혼합가스를 식각가스로 사용하는 식각공정으로 노출된 산화막(3)을 식각하여 1차적으로 콘택홀을 형성하는 단계(도2b)와; 상기 1차 식각공정 후, 상기 포토레지스트(PR) 패턴을 식각마스크로 사용하며 CxFy, O2, Ar을 식각가스로 사용하는 식각공정으로 콘택홀을 완성하는 단계(도2c)와; 상기 포토레지스트(PR) 패턴을 제거하는 단계(도2c)로 구성된다.2A through 2D are cross-sectional views of a process for manufacturing a contact hole in a semiconductor device according to an embodiment of the present invention, in which a nitride film 2 and an oxide film 3 are sequentially deposited on the substrate 1 on which a semiconductor device is formed. In which the photoresist (PR) is applied on the oxide film (3), and forming a pattern exposing a portion of the upper portion of the oxide film (FIG. 2A); Forming a contact hole primarily by etching the exposed oxide film 3 by an etching process using the photoresist (PR) pattern as an etching mask and using a mixture of CHxFy, O 2 , and Ar as an etching gas ( 2b); After the first etching process, using the photoresist (PR) pattern as an etching mask and completing the contact hole by an etching process using CxFy, O 2 , Ar as an etching gas (Fig. 2c); Removing the photoresist (PR) pattern consists of a step (Fig. 2c).

이하, 상기와 같은 본 발명 반도체 장치의 콘택홀 형성방법을 좀 더 상세히 설명한다.Hereinafter, a method of forming a contact hole in the semiconductor device of the present invention as described above will be described in more detail.

먼저, 도2a에 도시한 바와 같이 반도체 소자가 형성된 기판(1)의 상부에 질화막(2)을 증착하고, 그 질화막(2)의 상부에 산화막(3)을 증착한다.First, as illustrated in FIG. 2A, a nitride film 2 is deposited on the substrate 1 on which the semiconductor element is formed, and an oxide film 3 is deposited on the nitride film 2.

그 다음, 상기 산화막(3)의 상부에 포토레지스트(PR)를 도포하고, 노광 및 현상하여 상기 산화막(3)의 일부를 노출시키는 포토레지스트(PR) 패턴을 형성한다.Next, photoresist PR is applied on the oxide film 3, and the photoresist PR is exposed and developed to form a photoresist PR pattern that exposes a portion of the oxide film 3.

그 다음, 도2b에 도시한 바와 같이 상기 포토레지스트(PR) 패턴을 식각마스크로 사용하는 식각공정으로 노출된 산화막(3)을 CHxFy, O2, Ar혼합가스를 식각가스로 하여 식각한다. Next, as shown in FIG. 2B, the oxide film 3 exposed by the etching process using the photoresist PR pattern as an etching mask is etched using CHxFy, O 2 and Ar mixed gas as an etching gas.

이때, CHxFy가스는 식각의 주요 소스가스의 역할을 하며, O2는 플라즈마 내에서 식각보조가스로 작용하고, 가스 플로우의 증가로 식각가공정 및 부분적으로 콘택홀의 프로파일을 조절하는 기능을 한다. At this time, the CHxFy gas serves as the main source gas of etching, O 2 acts as an etching assistant gas in the plasma, and the function of the etching value process and partially the contact hole is controlled by the increase of the gas flow.

또한, Ar은 플라즈마 내에서 전체 가스를 잘 희석하여 안정한 플라즈마가 형 성되도록 하는 역할을 한다.In addition, Ar serves to dilute the entire gas in the plasma to form a stable plasma.

이와 같이 CHxFy, O2, Ar혼합가스를 사용하는 식각공정은 콘택홀의 대부분을 형성하며, 이후의 식각공정에서 그 콘택홀의 형상이 수직으로 형성되도록 하고 하지막과의 선택비를 높여 하지막의 손상을 방지하게 된다.As such, the etching process using CHxFy, O 2 , and Ar mixed gas forms most of the contact holes, and in subsequent etching processes, the contact holes are vertically formed and the selectivity with the underlying film is increased to prevent damage to the underlying film. Will be prevented.

상기 사용하는 CHxFy, O2, Ar의 유량은 각각 10~100sccm, 5~25sccm, 300~600sccm을 사용하며, 특히 02와 CHxFy의 유량비는 1:2 내지 1:5의 범위에서 사용한다.The flow rate of the used CHxFy, O 2 , Ar is used 10 ~ 100sccm, 5 ~ 25sccm, 300 ~ 600sccm, respectively, in particular the flow rate ratio of 0 2 and CHxFy is used in the range of 1: 2 to 1: 5.

그 다음, 도2c에 도시한 바와 같이 상기 포토레지스트(PR) 패턴을 식각마스크로 사용하며, 식각가스로 CxFy, O2, Ar가스를 식각가스로 사용하는 식각공정으로 상기 식각공정으로 형성된 콘택홀의 측면 프로파일을 수직이 되도록 식각한다. Next, as shown in FIG. 2C, the photoresist (PR) pattern is used as an etching mask, and an etching process using CxFy, O 2 , and Ar gas as an etching gas is performed. The side profile is etched to be vertical.

이와 같이 그 콘택홀의 프로파일은 CxFy가스의 유량에 따라 결정되며, 하지막과의 선택비를 높일 수 있게 된다.In this way, the profile of the contact hole is determined according to the flow rate of the CxFy gas, thereby increasing the selectivity with the underlying film.

이때의 CxFy가스의 유량은 5~50sccm, Ar은 300~600sccm, O2가스는 2~25sccm으로 제한하여 사용하며, O2가스와 CxFy의 비는 1:1 내지 1:4의 범위가 되도록 한다.At this time, the flow rate of CxFy gas is limited to 5 ~ 50sccm, Ar is 300 ~ 600sccm, O 2 gas is 2 ~ 25sccm, the ratio of O 2 gas and CxFy is in the range of 1: 1 to 1: 4. .

그 다음, 도2d에 도시한 바와 같이 상기 포토레지스트(PR) 패턴을 제거하여 콘택홀 제조를 완료하게 된다.Next, as shown in FIG. 2D, the photoresist (PR) pattern is removed to complete contact hole manufacturing.

상기한 바와 같이 본 발명은 콘택홀 형성시 1차적으로 CHxFy, O2, Ar을 식각 가스로 사용하는 식각공정으로 콘택홀의 대부분을 형성한 후, 2차적으로 CxFy, O2, Ar을 사용하는 식각공정으로 하지막과의 선택비를 높임과 아울러 콘택홀의 형상이 수직으로 형성되도록 함으로써, 반도체 장치의 특성 열화를 방지하는 효과가 있다.As described above, the present invention is an etching process using CHxFy, O 2 , Ar as an etching gas primarily when forming the contact hole, and after forming most of the contact holes, secondly etching using CxFy, O 2 , Ar. By increasing the selectivity with the underlying film and forming the contact holes vertically in the step, there is an effect of preventing the deterioration of the characteristics of the semiconductor device.

Claims (5)

산화막의 상부에 포토레지스트 패턴을 형성하고, 그 포토레지스트 패턴을 식각마스크로 하는 건식식각공정으로 상기 산화막 하부의 하지층의 일부를 노출시키는 콘택홀을 형성하는 반도체 장치의 콘택홀 제조방법에 있어서, 상기 건식식각공정은 CHxFy, O2, Ar을 식각가스로 하되 02와 CHxFy의 유량비를 1:2 내지 1:5의 범위로 식각하여 콘택홀을 형성하는 제1식각단계와; CxFy, O2, Ar을 식각가스로 하되 02와 CxFy의 유량비를 1:2 내지 1:4의 범위로 하여 상기 형성된 콘택홀과 하지층의 선택비를 높여 상기 콘택홀의 측면 형상이 수직을 이루도록 하는 제2식각단계로 이루어진 것을 특징으로 하는 반도체 장치의 콘택홀 형성방법.A method for manufacturing a contact hole in a semiconductor device, wherein a photoresist pattern is formed on an oxide film, and a contact hole for exposing a portion of the underlying layer under the oxide film is formed by a dry etching process using the photoresist pattern as an etching mask. The dry etching process may include a first etching step of forming a contact hole by etching CHxFy, O 2 and Ar as an etching gas but using a flow ratio of 0 2 and CHxFy in a range of 1: 2 to 1: 5; CxFy, O 2 , Ar as an etching gas, but the flow rate ratio of 0 2 and CxFy in the range of 1: 2 to 1: 4 to increase the selectivity of the formed contact hole and the underlying layer so that the side shape of the contact hole is vertical. And forming a second etching step. 제 1항에 있어서, 상기 제1식각단계에서 사용하는 CHxFy, O2, Ar의 유량은 각각 10~100sccm, 5~25sccm, 300~600sccm인 것을 특징으로 하는 반도체 장치의 콘택홀 형성방법.The method of claim 1, wherein the flow rates of CHxFy, O 2 , and Ar used in the first etching step are 10 to 100 sccm, 5 to 25 sccm, and 300 to 600 sccm, respectively. 삭제delete 제 1항에 있어서, 상기 제2식각단계에서 사용하는 CxFy, O2, Ar의 유량은 각 각 5~50sccm, 5~25sccm, 300~600sccm인 것을 특징으로 하는 반도체 장치의 콘택홀 형성방법.The method of claim 1, wherein the flow rates of CxFy, O 2 , and Ar used in the second etching step are 5 to 50 sccm, 5 to 25 sccm, and 300 to 600 sccm, respectively. 삭제delete
KR1019990051280A 1999-11-18 1999-11-18 Manufacturing method for contact hole in semiconductor device KR100587039B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019990051280A KR100587039B1 (en) 1999-11-18 1999-11-18 Manufacturing method for contact hole in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019990051280A KR100587039B1 (en) 1999-11-18 1999-11-18 Manufacturing method for contact hole in semiconductor device

Publications (2)

Publication Number Publication Date
KR20010047180A KR20010047180A (en) 2001-06-15
KR100587039B1 true KR100587039B1 (en) 2006-06-07

Family

ID=19620658

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019990051280A KR100587039B1 (en) 1999-11-18 1999-11-18 Manufacturing method for contact hole in semiconductor device

Country Status (1)

Country Link
KR (1) KR100587039B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100837538B1 (en) * 2006-12-27 2008-06-12 동부일렉트로닉스 주식회사 Method for forming metal interconnection of semiconductor device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100866124B1 (en) * 2002-12-03 2008-10-31 주식회사 하이닉스반도체 Method for forming capacitor of semiconductor device
KR100769149B1 (en) 2006-09-05 2007-10-22 동부일렉트로닉스 주식회사 Method for forming semiconductor device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0491432A (en) * 1990-08-02 1992-03-24 Sony Corp Magnetron rie apparatus
JPH0766185A (en) * 1993-08-27 1995-03-10 Nippondenso Co Ltd Fabrication of semiconductor device
KR0163536B1 (en) * 1995-10-25 1999-02-01 김광호 Method of forming contact hole in semiconductor device
KR19990046947A (en) * 1997-12-02 1999-07-05 구본준 Method for forming contact hole in semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0491432A (en) * 1990-08-02 1992-03-24 Sony Corp Magnetron rie apparatus
JPH0766185A (en) * 1993-08-27 1995-03-10 Nippondenso Co Ltd Fabrication of semiconductor device
KR0163536B1 (en) * 1995-10-25 1999-02-01 김광호 Method of forming contact hole in semiconductor device
KR19990046947A (en) * 1997-12-02 1999-07-05 구본준 Method for forming contact hole in semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100837538B1 (en) * 2006-12-27 2008-06-12 동부일렉트로닉스 주식회사 Method for forming metal interconnection of semiconductor device

Also Published As

Publication number Publication date
KR20010047180A (en) 2001-06-15

Similar Documents

Publication Publication Date Title
JP4034164B2 (en) Method for manufacturing fine pattern and method for manufacturing semiconductor device
KR100311487B1 (en) Method for etching of oxidation film
JP3316407B2 (en) Method for manufacturing semiconductor device
JPH1197414A (en) Plasma etching method for silicon-oxide based insulating film
KR100587039B1 (en) Manufacturing method for contact hole in semiconductor device
US6803307B1 (en) Method of avoiding enlargement of top critical dimension in contact holes using spacers
JP2007096214A (en) Manufacturing method for semiconductor device
KR100750081B1 (en) Process for selectively etching doped silicon dioxide over undoped silicon dioxide and silicon nitride
KR100373363B1 (en) Method of forming contact hole of semiconductor device
KR101016334B1 (en) Method of forming gate electrode in semiconductor device
KR19990065142A (en) Method for forming vertical profile pattern of material layer containing silicon
KR100256809B1 (en) Method for forming contact hole in semiconductor device
KR20010060984A (en) Manufacturing method for contact hole in semiconductor device
KR100317310B1 (en) Method for fabricating contact hole of semiconductor device
KR20020036255A (en) Method for fabricating fine contact hole of semiconductor device
KR930008841B1 (en) Contact hole forming method
KR100434312B1 (en) Method for making contact hole in semiconductor device
KR20030046932A (en) a method for forming contact hole of semiconductor device
KR100487415B1 (en) Method for fabricating contact hole in semiconductor device
KR100223869B1 (en) Manufacturing method of semiconductor device
KR100562269B1 (en) Method for fabriacting via of semiconductor device
KR0172856B1 (en) Fine patterning method
KR100223760B1 (en) Process for forming contact hole of semicondcutor device
JPH07135198A (en) Etching
KR100769149B1 (en) Method for forming semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20110429

Year of fee payment: 6

LAPS Lapse due to unpaid annual fee