KR101064755B1 - 다열 리드형 리드프레임 및 이를 이용한 반도체 패키지의 제조방법 - Google Patents
다열 리드형 리드프레임 및 이를 이용한 반도체 패키지의 제조방법 Download PDFInfo
- Publication number
- KR101064755B1 KR101064755B1 KR1020080132887A KR20080132887A KR101064755B1 KR 101064755 B1 KR101064755 B1 KR 101064755B1 KR 1020080132887 A KR1020080132887 A KR 1020080132887A KR 20080132887 A KR20080132887 A KR 20080132887A KR 101064755 B1 KR101064755 B1 KR 101064755B1
- Authority
- KR
- South Korea
- Prior art keywords
- pattern
- lead frame
- plating
- lead
- raw material
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000000034 method Methods 0.000 title claims description 77
- 238000004519 manufacturing process Methods 0.000 title claims description 44
- 238000007747 plating Methods 0.000 claims abstract description 128
- 230000001681 protective effect Effects 0.000 claims abstract description 48
- 239000000463 material Substances 0.000 claims abstract description 42
- 238000005530 etching Methods 0.000 claims abstract description 40
- 239000002994 raw material Substances 0.000 claims description 37
- 239000010410 layer Substances 0.000 claims description 24
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000004593 Epoxy Substances 0.000 claims description 5
- 239000000956 alloy Substances 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 229910052763 palladium Inorganic materials 0.000 claims description 5
- 229910052709 silver Inorganic materials 0.000 claims description 5
- 239000002356 single layer Substances 0.000 claims description 5
- 229910052718 tin Inorganic materials 0.000 claims description 5
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 238000000465 moulding Methods 0.000 claims description 4
- 238000000206 photolithography Methods 0.000 claims description 2
- 229910002058 ternary alloy Inorganic materials 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 5
- 230000007261 regionalization Effects 0.000 abstract description 4
- 230000008569 process Effects 0.000 description 61
- 239000000047 product Substances 0.000 description 9
- 239000011248 coating agent Substances 0.000 description 6
- 238000000576 coating method Methods 0.000 description 6
- 229910000510 noble metal Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 230000018109 developmental process Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910000881 Cu alloy Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000010970 precious metal Substances 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000640 Fe alloy Inorganic materials 0.000 description 1
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 229910002056 binary alloy Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
- H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01067—Holmium [Ho]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Electroplating Methods And Accessories (AREA)
Abstract
Description
Claims (18)
- 리드프레임 원소재에 도금패턴을 형성하는 1단계;상기 도금패턴 상에 보호패턴을 형성하되, 상기 리드프레임 원소재의 상면에 형성되는 상부 보호패턴의 폭(T1)은 도금 패턴의 폭(T2) 이상의 길이로 형성하는 2단계;상기 보호패턴을 마스크로 하여 미세패턴을 형성하는 3단계;를 포함하는 다열 리드형 리드프레임의 제조방법.
- 청구항 1에 있어서, 상기 1단계는,상기 리드프레임 원소재의 양면 또는 단면에 감광성 물질을 도포하고, 노광 및 현상하여 리드프레임 패턴을 형성하는 a) 단계;상기 리드프레임 패턴에 도금을 수행하는 b) 단계; 로 이루어지는 것을 특징으로 하는 다열 리드형 리드프레임의 제조방법.
- 청구항 1에 있어서, 상기 1단계는,상기 도금패턴을 Ni, Pd, Au, Sn, Ag, Co, Cu 중에 선택되는 1원 또는 2원, 3원의 합금층을 사용하여, 단층 또는 다층으로 형성하는 단계인 것을 특징으로 하는 다열 리드형 리드프레임의 제조방법.
- 청구항 2에 있어서,상기 1단계는,상기 도금 패턴을 형성한 후, 상기 감광성 물질을 박리하는 c) 단계를 더 포함하는 것을 특징으로 하는 다열 리드형 리드프레임의 제조방법.
- 청구항 1에 있어서, 상기 2단계는,도금패턴이 형성된 리드프레임 원소재의 양면 또는 단면에 감광성 물질을 도포하여 포토리소그라피법을 이용하는 단계인 것을 특징으로 하는 다열 리드형 리드프레임의 제조방법.
- 청구항 5에 있어서, 상기 2단계는,리드프레임 원소재의 양면에 감광성 물질을 도포하고,상기 리드프레임 원소재의 상면에는 패턴의 노광 및 현상을 수행하여 상부 보호패턴을 형성하며,하면에는 전면 노광을 실시하여 하부 보호패턴을 형성하는 것을 특징으로 하는 다열 리드형 리드프레임의 제조방법.
- 삭제
- 청구항 1에 있어서,상기 보호패턴을 상기 도금패턴의 상면과 측면부위를 감싸는 구조로 형성시키는 것을 특징으로 하는 다열 리드형 리드프레임의 제조방법.
- 청구항 1 또는 청구항 6에 있어서,상기 3단계는,상기 상부 보호패턴 부위 이외의 노출된 상기 리드프레임의 상면을 에칭하는 단계인 것을 특징으로 하는 다열 리드형 리드프레임의 제조방법.
- 청구항 8에 있어서,상기 3단계 이후에, 상기 보호패턴을 박리하는 단계를 더 포함하는 것을 특징으로 하는 다열 리드형 리드프레임의 제조방법.
- 리드프레임 원소재에 도금패턴을 형성하는 1단계;상기 도금패턴 상에 보호패턴을 형성하되, 상기 리드프레임 원소재의 상면에 형성되는 상부 보호패턴의 폭(T1)은 도금 패턴의 폭(T2) 이상의 길이로 형성하는 2단계;상기 보호패턴을 마스크로 하여 미세패턴을 형성하는 3단계;상기 보호패턴을 박리하고, 반도체칩을 실장, 와이어본딩, 에폭시 몰딩을 수행하고,백 에칭을 통해 반도체 패키지를 완성하는 4단계;를 포함하는 반도체 패키지의 제조방법.
- 삭제
- 리드프레임 원소재의 상면 또는 하면에 적어도 1 이상의 미세패턴이 형성되며, 상기 미세패턴이 형성되지 않는 부분의 어느 하나 이상에 도금패턴을 포함하여 리드프레임을 구성하되,상기 리드프레임의 상부패턴면의 폭(T3)이 도금패턴의 폭(T2) 이상으로 형성되는 것을 특징으로 하는 다열 리드형 리드프레임.
- 청구항 13에 있어서,상기 리드프레임 스트립의 외곽부는 노출된 구조를 갖는 것을 특징으로 하는 다열 리드형 리드 프레임.
- 삭제
- 청구항 13 또는 청구항 14에 있어서,상기 도금패턴은 Cu, Ni, Pd, Au, Sn, Ag, Co 중 어느 하나 또는 이들의 2원, 3원 합금을 이용하여 단층 또는 다층으로 형성하는 것을 특징으로 하는 다열 리드형 리드프레임.
- 리드프레임 원소재의 상면 또는 하면에 적어도 1 이상의 미세패턴이 형성되며, 상기 미세패턴이 형성되지 않는 부분의 어느 하나 이상에 도금패턴을 포함하여 리드프레임을 구성하되,상기 리드프레임의 상부패턴면의 폭(T3)이 도금패턴의 폭(T2) 이상으로 형성되는 다열 리드형 리드프레임에 반도체 칩과 와이어 본딩과 에폭시 몰딩을 포함하여 형성되는 반도체 패키지.
- 삭제
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020080132887A KR101064755B1 (ko) | 2008-12-24 | 2008-12-24 | 다열 리드형 리드프레임 및 이를 이용한 반도체 패키지의 제조방법 |
TW098144182A TWI408788B (zh) | 2008-12-24 | 2009-12-22 | 多列導線架結構及其半導體封裝與製造方法 |
PCT/KR2009/007724 WO2010074510A2 (en) | 2008-12-24 | 2009-12-23 | Structure for multi-row leadframe and semiconductor package thereof and manufacture method thereof |
JP2011543424A JP2012514326A (ja) | 2008-12-24 | 2009-12-23 | 多列リード型リードフレーム及びこれを用いた半導体パッケージの製造方法 |
CN200980152298.5A CN102265394B (zh) | 2008-12-24 | 2009-12-23 | 多行引线框架的结构及其半导体封装及制造方法 |
US13/142,172 US8956919B2 (en) | 2008-12-24 | 2009-12-23 | Structure for multi-row leadframe and semiconductor package thereof and manufacture method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020080132887A KR101064755B1 (ko) | 2008-12-24 | 2008-12-24 | 다열 리드형 리드프레임 및 이를 이용한 반도체 패키지의 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20100074449A KR20100074449A (ko) | 2010-07-02 |
KR101064755B1 true KR101064755B1 (ko) | 2011-09-15 |
Family
ID=42288304
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020080132887A KR101064755B1 (ko) | 2008-12-24 | 2008-12-24 | 다열 리드형 리드프레임 및 이를 이용한 반도체 패키지의 제조방법 |
Country Status (6)
Country | Link |
---|---|
US (1) | US8956919B2 (ko) |
JP (1) | JP2012514326A (ko) |
KR (1) | KR101064755B1 (ko) |
CN (1) | CN102265394B (ko) |
TW (1) | TWI408788B (ko) |
WO (1) | WO2010074510A2 (ko) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8420508B2 (en) * | 2010-03-17 | 2013-04-16 | Stats Chippac Ltd. | Integrated circuit packaging system with bump contact on package leads and method of manufacture thereof |
US8669654B2 (en) * | 2010-08-03 | 2014-03-11 | Stats Chippac Ltd. | Integrated circuit packaging system with die paddle and method of manufacture thereof |
US9029991B2 (en) * | 2010-11-16 | 2015-05-12 | Conexant Systems, Inc. | Semiconductor packages with reduced solder voiding |
CN102376672B (zh) * | 2011-11-30 | 2014-10-29 | 江苏长电科技股份有限公司 | 无基岛球栅阵列封装结构及其制造方法 |
US9257306B2 (en) | 2013-04-18 | 2016-02-09 | Dai Nippon Printing Co., Ltd. | Lead frame, method for manufacturing lead frame, semiconductor device, and method for manufacturing semiconductor device |
CN103413766B (zh) * | 2013-08-06 | 2016-08-10 | 江阴芯智联电子科技有限公司 | 先蚀后封芯片正装三维***级金属线路板结构及工艺方法 |
CN103456645B (zh) * | 2013-08-06 | 2016-06-01 | 江阴芯智联电子科技有限公司 | 先蚀后封三维***级芯片正装堆叠封装结构及工艺方法 |
CN103400771B (zh) * | 2013-08-06 | 2016-06-29 | 江阴芯智联电子科技有限公司 | 先蚀后封芯片倒装三维***级金属线路板结构及工艺方法 |
JP6555927B2 (ja) * | 2015-05-18 | 2019-08-07 | 大口マテリアル株式会社 | 半導体素子搭載用リードフレーム及び半導体装置の製造方法 |
JP6593841B2 (ja) * | 2016-03-16 | 2019-10-23 | 大口マテリアル株式会社 | Ledパッケージ並びに多列型led用リードフレーム及びその製造方法 |
JP6593842B2 (ja) * | 2016-03-16 | 2019-10-23 | 大口マテリアル株式会社 | Ledパッケージ並びに多列型led用リードフレーム及びその製造方法 |
US10141197B2 (en) * | 2016-03-30 | 2018-11-27 | Stmicroelectronics S.R.L. | Thermosonically bonded connection for flip chip packages |
CN106521583A (zh) * | 2016-11-22 | 2017-03-22 | 宁波康强电子股份有限公司 | 一种引线框架的电镀方法 |
JP6777365B2 (ja) * | 2016-12-09 | 2020-10-28 | 大口マテリアル株式会社 | リードフレーム |
US10134660B2 (en) | 2017-03-23 | 2018-11-20 | Nxp Usa, Inc. | Semiconductor device having corrugated leads and method for forming |
CN111640729B (zh) * | 2020-04-21 | 2023-08-18 | 江苏长电科技股份有限公司 | 一种易于大尺寸元件底部填充的转接板及其制造方法 |
CN111785701A (zh) * | 2020-07-24 | 2020-10-16 | 宁波康强电子股份有限公司 | 一种预电镀镍钯金引线框架及其制备方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05183083A (ja) * | 1991-12-28 | 1993-07-23 | Shinko Electric Ind Co Ltd | リードフレーム及びその製造法 |
JPH10237691A (ja) * | 1997-02-20 | 1998-09-08 | Samsung Aerospace Ind Ltd | 多層メッキリードフレーム |
KR20010001160A (ko) * | 1999-06-02 | 2001-01-05 | 윤종용 | 반도체 패키지 및 그 제조방법 |
US7053492B2 (en) | 2002-08-07 | 2006-05-30 | Sanyo Electric Co., Ltd. | Circuit device and method of manufacturing the same |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60130151A (ja) * | 1983-12-16 | 1985-07-11 | Toppan Printing Co Ltd | リ−ドフレ−ムの製造方法 |
JPH1197612A (ja) * | 1997-09-17 | 1999-04-09 | Toppan Printing Co Ltd | リードフレーム及びその製造方法 |
JP3639514B2 (ja) | 2000-09-04 | 2005-04-20 | 三洋電機株式会社 | 回路装置の製造方法 |
KR101021600B1 (ko) * | 2001-07-09 | 2011-03-17 | 스미토모 긴조쿠 고잔 가부시키가이샤 | 리드 프레임 및 그 제조방법 |
JP2006253399A (ja) * | 2005-03-10 | 2006-09-21 | Mitsui High Tec Inc | リードフレームの製造方法 |
JP3947750B2 (ja) | 2005-07-25 | 2007-07-25 | 株式会社三井ハイテック | 半導体装置の製造方法及び半導体装置 |
KR101089449B1 (ko) * | 2005-08-10 | 2011-12-07 | 가부시키가이샤 미츠이하이테크 | 반도체 장치 및 그 제조 방법 |
JP2007051336A (ja) * | 2005-08-18 | 2007-03-01 | Shinko Electric Ind Co Ltd | 金属板パターン及び回路基板の形成方法 |
US7501693B2 (en) * | 2006-11-17 | 2009-03-10 | Micrel, Inc. | LDO regulator with ground connection through package bottom |
US7807498B2 (en) * | 2007-07-31 | 2010-10-05 | Seiko Epson Corporation | Substrate, substrate fabrication, semiconductor device, and semiconductor device fabrication |
-
2008
- 2008-12-24 KR KR1020080132887A patent/KR101064755B1/ko active IP Right Grant
-
2009
- 2009-12-22 TW TW098144182A patent/TWI408788B/zh not_active IP Right Cessation
- 2009-12-23 US US13/142,172 patent/US8956919B2/en active Active
- 2009-12-23 WO PCT/KR2009/007724 patent/WO2010074510A2/en active Application Filing
- 2009-12-23 CN CN200980152298.5A patent/CN102265394B/zh not_active Expired - Fee Related
- 2009-12-23 JP JP2011543424A patent/JP2012514326A/ja active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05183083A (ja) * | 1991-12-28 | 1993-07-23 | Shinko Electric Ind Co Ltd | リードフレーム及びその製造法 |
JPH10237691A (ja) * | 1997-02-20 | 1998-09-08 | Samsung Aerospace Ind Ltd | 多層メッキリードフレーム |
KR20010001160A (ko) * | 1999-06-02 | 2001-01-05 | 윤종용 | 반도체 패키지 및 그 제조방법 |
US7053492B2 (en) | 2002-08-07 | 2006-05-30 | Sanyo Electric Co., Ltd. | Circuit device and method of manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
US8956919B2 (en) | 2015-02-17 |
WO2010074510A2 (en) | 2010-07-01 |
TWI408788B (zh) | 2013-09-11 |
CN102265394B (zh) | 2014-04-02 |
WO2010074510A3 (en) | 2010-09-10 |
JP2012514326A (ja) | 2012-06-21 |
US20120038036A1 (en) | 2012-02-16 |
KR20100074449A (ko) | 2010-07-02 |
TW201030919A (en) | 2010-08-16 |
CN102265394A (zh) | 2011-11-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR101064755B1 (ko) | 다열 리드형 리드프레임 및 이를 이용한 반도체 패키지의 제조방법 | |
JP4032063B2 (ja) | 半導体装置の製造方法 | |
KR101089449B1 (ko) | 반도체 장치 및 그 제조 방법 | |
KR100297464B1 (ko) | 수지봉지형반도체장치와그것에사용되는회로부재및수지봉지형반도체장치의제조방법 | |
US5882955A (en) | Leadframe for integrated circuit package and method of manufacturing the same | |
JP2007048978A (ja) | 半導体装置及びその製造方法 | |
JP4599399B2 (ja) | 化学的に向上させたパッケージシンギュレーション法 | |
JP2020053420A (ja) | リードフレーム及びリードフレームの製造方法 | |
JP2000133763A (ja) | 樹脂封止型半導体装置用の回路部材およびその製造方法 | |
JPH10335566A (ja) | 樹脂封止型半導体装置とそれに用いられる回路部材、および樹脂封止型半導体装置の製造方法 | |
JP2012049323A (ja) | リードフレーム及びこれを用いた半導体装置並びにその製造方法 | |
TW200901422A (en) | Pre-plated leadframe having enhanced encapsulation adhesion | |
JP6274553B2 (ja) | リードフレームおよびその製造方法、ならびに半導体装置およびその製造方法 | |
KR101036354B1 (ko) | 다열 리드프레임 및 반도체 칩 패키지 및 그 제조방법 | |
KR100975977B1 (ko) | 다열 리드형 리드프레임 및 그 제조방법 | |
KR101036351B1 (ko) | 반도체 패키지용 다열형 리드리스 프레임 및 그 제조방법 | |
JP2012164936A (ja) | 半導体装置の製造方法 | |
JPH0521695A (ja) | リードフレーム、その製造方法及びそのリードフレームを用いた電子制御装置の製造方法 | |
JP6460500B2 (ja) | リードフレームおよびその製造方法、ならびに半導体装置およびその製造方法 | |
KR100819799B1 (ko) | 다열리드형 반도체 패키지 제조 방법 | |
JP3569642B2 (ja) | 半導体装置用キャリア基板及びその製造方法及び半導体装置の製造方法 | |
JP2000332146A (ja) | 樹脂封止型半導体装置とそれに用いられる回路部材およびそれらの製造方法 | |
JP4176092B2 (ja) | 樹脂封止型半導体装置およびその製造方法 | |
JP3884552B2 (ja) | 半導体装置とそれに用いられる回路部材および半導体装置の製造方法 | |
KR101139971B1 (ko) | 능동소자 매립형 리드 프레임 및 반도체 패키지 및 그의 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
N231 | Notification of change of applicant | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20140805 Year of fee payment: 4 |
|
FPAY | Annual fee payment |
Payment date: 20150902 Year of fee payment: 5 |
|
FPAY | Annual fee payment |
Payment date: 20160902 Year of fee payment: 6 |
|
FPAY | Annual fee payment |
Payment date: 20170901 Year of fee payment: 7 |
|
FPAY | Annual fee payment |
Payment date: 20180903 Year of fee payment: 8 |
|
FPAY | Annual fee payment |
Payment date: 20190902 Year of fee payment: 9 |