KR100816924B1 - 반도체 집적회로장치 - Google Patents
반도체 집적회로장치 Download PDFInfo
- Publication number
- KR100816924B1 KR100816924B1 KR1020027006867A KR20027006867A KR100816924B1 KR 100816924 B1 KR100816924 B1 KR 100816924B1 KR 1020027006867 A KR1020027006867 A KR 1020027006867A KR 20027006867 A KR20027006867 A KR 20027006867A KR 100816924 B1 KR100816924 B1 KR 100816924B1
- Authority
- KR
- South Korea
- Prior art keywords
- memory cell
- nonvolatile memory
- delete delete
- circuit
- volatile
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 230000015654 memory Effects 0.000 claims abstract description 244
- 238000000034 method Methods 0.000 claims abstract description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 11
- 230000008569 process Effects 0.000 claims abstract description 8
- 238000009966 trimming Methods 0.000 claims abstract description 8
- 230000002950 deficient Effects 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 15
- 238000012937 correction Methods 0.000 claims description 10
- 230000000295 complement effect Effects 0.000 claims 1
- 230000007547 defect Effects 0.000 abstract description 32
- 238000012360 testing method Methods 0.000 abstract description 28
- 230000008439 repair process Effects 0.000 abstract description 18
- 229920005591 polysilicon Polymers 0.000 abstract description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052802 copper Inorganic materials 0.000 abstract description 4
- 239000010949 copper Substances 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 39
- 239000002784 hot electron Substances 0.000 description 9
- 230000006870 function Effects 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 8
- 238000005520 cutting process Methods 0.000 description 7
- 230000008859 change Effects 0.000 description 6
- 238000007689 inspection Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 230000004913 activation Effects 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000004044 response Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 238000003698 laser cutting Methods 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- C—CHEMISTRY; METALLURGY
- C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
- C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
- C04B28/00—Compositions of mortars, concrete or artificial stone, containing inorganic binders or the reaction product of an inorganic and an organic binder, e.g. polycarboxylate cements
- C04B28/02—Compositions of mortars, concrete or artificial stone, containing inorganic binders or the reaction product of an inorganic and an organic binder, e.g. polycarboxylate cements containing hydraulic cements other than calcium sulfates
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
- G11C29/789—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
- G11C29/848—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by adjacent switching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/22—Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
- H01L27/0211—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique adapted for requirements of temperature
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- C—CHEMISTRY; METALLURGY
- C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
- C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
- C04B2103/00—Function or property of ingredients for mortars, concrete or artificial stone
- C04B2103/0068—Ingredients with a function or property not provided for elsewhere in C04B2103/00
- C04B2103/0097—Anion- and far-infrared-emitting materials
-
- C—CHEMISTRY; METALLURGY
- C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
- C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
- C04B2111/00—Mortars, concrete or artificial stone or mixtures to prepare them, characterised by specific function, property or use
- C04B2111/00017—Aspects relating to the protection of the environment
-
- C—CHEMISTRY; METALLURGY
- C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
- C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
- C04B2111/00—Mortars, concrete or artificial stone or mixtures to prepare them, characterised by specific function, property or use
- C04B2111/00439—Physico-chemical properties of the materials not provided for elsewhere in C04B2111/00
- C04B2111/00456—Odorless cements
-
- C—CHEMISTRY; METALLURGY
- C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
- C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
- C04B2111/00—Mortars, concrete or artificial stone or mixtures to prepare them, characterised by specific function, property or use
- C04B2111/00474—Uses not provided for elsewhere in C04B2111/00
- C04B2111/00482—Coating or impregnation materials
- C04B2111/00517—Coating or impregnation materials for masonry
-
- C—CHEMISTRY; METALLURGY
- C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
- C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
- C04B2111/00—Mortars, concrete or artificial stone or mixtures to prepare them, characterised by specific function, property or use
- C04B2111/20—Resistance against chemical, physical or biological attack
- C04B2111/2092—Resistance against biological degradation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/02—Structural aspects of erasable programmable read-only memories
- G11C2216/10—Floating gate memory cells with a single polysilicon layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
- H01L2223/5444—Marks applied to semiconductor devices or parts containing identification or tracking information for electrical read out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/1016—Shape being a cuboid
- H01L2924/10162—Shape being a cuboid with a square active surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/50—Peripheral circuit region structures
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Nanotechnology (AREA)
- Ceramic Engineering (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Structural Engineering (AREA)
- Materials Engineering (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Mathematical Physics (AREA)
- Organic Chemistry (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
- Non-Volatile Memory (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
Claims (50)
- 삭제
- 삭제
- 삭제
- 삭제
- 삭제
- 삭제
- 삭제
- 삭제
- 삭제
- 삭제
- 삭제
- 삭제
- 삭제
- 삭제
- 삭제
- 삭제
- 삭제
- 삭제
- 삭제
- 삭제
- 삭제
- 삭제
- 삭제
- 삭제
- 삭제
- 삭제
- 휘발성 메모리셀들을 포함하는 휘발성 메모리셀 어레이와,상기 휘발성 메모리셀 어레이에 결함을 지닌 휘발성 메모리셀인 결함 메모리셀이 있는 경우에, 상기 결함 메모리셀을 치환하기 위한 휘발성 용장(冗長) 메모리셀들과,상기 결함 메모리셀에 의거하는 구제(救濟) 어드레스 정보를 기억하기 위한 불휘발성 메모리와,상기 불휘발성 메모리에 기억된 구제(救濟)어드레스정보에 의해, 상기 결함 메모리셀로부터의 출력을 상기 용장(冗長) 메모리셀들로부터의 출력으로 대체하는 구제(救濟) 디코더를 포함하며,상기 불휘발성 메모리는, 반도체 기판의 주면에 따라 설치된 제1 도전형의 제1 반도체영역 및 상기 반도체 기판의 상기 주면에 상기 제1 반도체영역에 인접하게 형성된 제2 도전형의 제2 반도체영역과, 상기 제1 및 제2 반도체영역과 불휘발성 메모리의 절연막을 통해서 배치된 플로팅 게이트를 가지며,상기 제2 도전형의 소스영역 및 상기 제2 도전형의 드레인영역은 상기 제1 반도체영역에 배치되고, 상기 제2 반도체영역과 상기 소스영역 및 상기 드레인영역중 최소한 하나에 소정의 전압을 인가함으로써, 데이터가 소거 혹은 기록 가능한 것을 특징으로 하는 반도체 집적회로장치.
- 제 27 항에 있어서,리드 프레임과 접속되어, 신호들을 입출력하기 위한 패드와,상기 휘발성 메모리셀 어레이 및 상기 휘발성 용장(冗長) 메모리셀들에 접속되며,제2 트랜지스터를 포함하고, 상기 패드에 접속되어 상기 신호들을 입출력하기 위한 입출력회로를 추가로 포함하며,상기 휘발성 메모리셀 어레이는 제1 트랜지스터를 포함하고,상기 제2 트랜지스터의 절연막은 상기 제1 트랜지스터의 절연막보다 더 두꺼운 반도체 집적회로장치.
- 제 28 항에 있어서,상기 불휘발성 메모리의 상기 절연막은, 상기 제1 트랜지스터의 상기 절연막의 막 두께보다도 더 두꺼운 막 두께를 가지며, 상기 제2 트랜지스터의 상기 절연막의 막 두께와 같은 막 두께를 가지는 것을 특징으로 하는 반도체 집적회로장치.
- 제 28 항에 있어서,상기 불휘발성 메모리의 상기 절연막의 막 두께와 상기 제1 트랜지스터의 상기 절연막의 막 두께와의 차는, 상기 불휘발성 메모리의 상기 절연막의 상기 막 두께와 상기 제2 트랜지스터의 상기 절연막의 상기 막 두께와의 차보다도 더 큰 것을 특징으로 하는 반도체 집적회로장치.
- 제 28 항에 있어서,상기 제1 트랜지스터의 게이트 길이는 상기 불휘발성 메모리의 게이트 길이보다도 더 짧은 것을 특징으로 하는 반도체 집적회로장치.
- 제 28 항에 있어서,상기 불휘발성 메모리는 상기 패드 및 상기 입출력회로가 배치된 영역에 배치된 것을 특징으로 하는 반도체 집적회로장치.
- 제 28 항에 있어서,상기 복수의 패드들은 상기 반도체 집적회로장치에 형성되며, 상기 복수의 패드들중 적어도 하나는 상기 신호들 및 상기 불휘발성 메모리의 기록 데이터를 제어하는 제어신호들을 선택적으로 입력 가능한 것을 특징으로 하는 반도체 집적회로장치.
- 휘발성 메모리셀들을 포함하는 휘발성 메모리셀 어레이와,상기 휘발성 메모리셀 어레이에 결함을 지닌 휘발성 메모리셀인 결함 메모리셀이 있는 경우에, 상기 결함 메모리셀을 치환하기 위한 휘발성 용장(冗長) 메모리셀들과,상기 결함 메모리셀에 의거하는 구제(救濟) 어드레스 정보를 기억하기 위한 불휘발성 메모리와,오류정정회로와,상기 불휘발성 메모리에 기억된 구제(救濟)어드레스정보에 의해, 상기 결함 메모리셀로부터의 출력을 용장(冗長) 메모리셀들로부터의 출력으로 대체하도록 제어하는 구제(救濟) 디코더를 포함하며,상기 불휘발성 메모리는 반도체 기판의 주면에 형성된 제1 도전형의 제1 반도체영역에 형성된 제1 소자와 상기 반도체 기판의 상기 주면에 형성된 제2 도전형의 제2 반도체영역에 형성된 제2소자를 포함하고,상기 제1 소자는 상기 제1 반도체영역에 형성된 소스영역 및 드레인영역 및 제1 절연막을 통해서 형성된 제1 게이트를 포함하며, 상기 제2 소자는 제2 절연막을 통해서 형성되며, 상기 제1 게이트와 접속된 제2 게이트를 포함하고,상기 오류정정회로는 상기 불휘발성 메모리와 상기 구제(救濟) 디코더에 접속되어, 상기 구제(救濟)어드레스정보에 체크비트를 붙임으로써, 상기 체크비트를 갖는 상기 구제(救濟)어드레스정보를 상기 불휘발성 메모리에 기억시키며, 상기 불휘발성 메모리에서 판독된 데이터에 대해서 오류정정처리를 행하여 상기 구제(救濟)디코더에 출력하는 것을 특징으로 하는 반도체 집적회로장치.
- 제 34 항에 있어서,상기 오류정정회로는 상기 구제(救濟)어드레스정보에 대해서 1비트의 오류까지 정정 가능한 것을 특징으로 하는 반도체 집적회로장치.
- 구제(救濟)어드레스정보 혹은 트리밍 정보를 기억하기 위한 불휘발성 메모리들과,상기 불휘발성 메모리셀들에 기억된 상기 구제(救濟)어드레스정보 또는 상기 트리밍정보를 디코드하는 디코더와,상기 디코더에 의해 제어되는 스위치 회로를 포함하고,상기 불휘발성 메모리들중 각각은 제1 및 제2 불휘발성 메모리셀들을 포함하며, 그 각각은 반도체 기판의 주면에 형성된 제1 도전형의 제1 반도체영역과, 상기 반도체 기판의 상기 주면에 형성된 제2 도전형의 제2 반도체영역과, 상기 제1 반도체영역에 형성된 상기 제2 도전형의 소스영역 및 드레인영역과 상기 제1 반도체영역과 상기 제2 반도체영역 사이에 절연막들을 각각 삽입함으로써 형성된 게이트 전극들을 포함하고,1비트 정보는 상기 제1 및 상기 제2 불휘발성 메모리셀들에 의해 기억되는 것을 특징으로 하는 반도체 집적회로장치.
- 제 36 항에 있어서,상기 제1 및 상기 제2 불휘발성 메모리셀들은 같은 정보를 기억하고, 상기 불휘발성 메모리셀들의 각각에서 출력된 데이터의 논리합을 출력함으로써, 상기 1비트 정보를 판독하는 것을 특징으로 하는 반도체 집적회로장치.
- 제 36 항에 있어서,상기 제1 불휘발성 메모리셀은 제1 신호를 기억하고, 상기 제2 불휘발성 메모리셀은 상기 제1 신호와는 상보의 관계에 있는 제2 신호를 기억하며,상기 1비트 정보는 상기 제1 불휘발성 메모리셀의 문턱치 전압과 상기 제2 불휘발성 메모리셀의 문턱치 전압과의 차를 검출함으로써 판독되는 것을 특징으로 하는 반도체 집적회로장치.
- 제 38 항에 있어서,상기 제1 불휘발성 메모리셀의 게이트 폭과 상기 제2 불휘발성 메모리셀의 게이트 폭이 서로 다르며, 상기 불휘발성 메모리들에 정보를 기록하기 전에 설정된 데이터가 출력될 수 있는 것을 특징으로 하는 반도체 집적회로장치.
- 제 34 항에 있어서,상기 제1 및 제2 반도체 영역들은 상기 반도체 기판의 상기 주면에 서로 인접하게 형성되는 반도체 집적회로장치.
- 제 36 항에 있어서,상기 제1 및 제2 반도체 영역들은 상기 반도체 기판의 상기 주면에 서로 인접하게 형성되는 반도체 집적회로장치.
- 휘발성 메모리셀들을 포함하는 휘발성 메모리셀 어레이와,상기 휘발성 메모리셀 어레이에서의 휘발성 결함 메모리셀들을 치환하기 위한 휘발성 용장(冗長) 메모리셀들과,상기 휘발성 메모리셀 어레이에서의 휘발성 결함 메모리셀들에 의거하는 구제(救濟) 어드레스 정보를 기억하기 위한 불휘발성 메모리와,상기 불휘발성 메모리 및 상기 휘발성 메모리셀 어레이와 상기 휘발성 용장(冗長) 메모리셀들의 출력들에 접속되어, 상기 휘발성 메모리셀 어레이에서의 휘발성 결함 메모리셀로부터의 출력을 상기 용장(冗長) 메모리셀들중 하나의 출력으로 대체하는 구제(救濟) 디코더를 포함하며,상기 불휘발성 메모리는 불휘발성 플로팅 게이트 트랜지스터들을 포함하며,그 각각은 상기 불휘발성 메모리가 형성되는 반도체 기판의 주면위에 서로 나란히 배치된 플로팅 게이트와 컨트롤 게이트를 갖는 반도체 집적회로장치.
- 제 42 항에 있어서,상기 플로팅 게이트와 상기 컨트롤 게이트는 다결정 실리콘의 동일한 층에 의해 제조되는 반도체 집적회로장치.
- 삭제
- 삭제
- 삭제
- 삭제
- 삭제
- 제1 불휘발성 메모리 셀 및 제2 불휘발성 메모리 셀을 포함하며,그 각각은 :제1 도전형의 제1 반도체 영역,제2 도전형의 제2 반도체 영역,상기 제1 반도체 영역상에 형성된 상기 제2 도전형의 소스 영역 및 드레인 영역과,상기 제1 및 제2 반도체 영역상에 형성된 게이트 전극,상기 게이트 전극 및 상기 제1 및 제2 반도체 영역들 사이에 형성된 절연막과,상기 제1 및 제2 불휘발성 메모리셀들의 기록 또는 판독을 위한 제어신호를 생성하는 제어회로를 포함하고,상기 제어회로는 상기 제1 불휘발성 메모리셀과 인접하여 배치되며,상기 제1 및 제2 불휘발성 메모리셀들에 상기 제어신호를 입력하기 위한 신호선이 상기 제어회로로부터 상기 제1 및 제2 불휘발성 메모리셀들로 연장되는 것을 특징으로 하는 반도체 집적회로장치.
- 제 49 항에 있어서,상기 제1 불휘발성 메모리셀과 상기 제2 불휘발성 메모리셀은 컨트롤 게이트를 공유하는 것을 특징으로 하는 반도체 집적회로장치.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000038167A JP4191355B2 (ja) | 2000-02-10 | 2000-02-10 | 半導体集積回路装置 |
JPJP-P-2000-00038167 | 2000-02-10 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020077023259A Division KR100817343B1 (ko) | 2000-02-10 | 2001-02-08 | 반도체 집적회로장치 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20020080340A KR20020080340A (ko) | 2002-10-23 |
KR100816924B1 true KR100816924B1 (ko) | 2008-03-26 |
Family
ID=18561945
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020077023259A KR100817343B1 (ko) | 2000-02-10 | 2001-02-08 | 반도체 집적회로장치 |
KR1020027006867A KR100816924B1 (ko) | 2000-02-10 | 2001-02-08 | 반도체 집적회로장치 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020077023259A KR100817343B1 (ko) | 2000-02-10 | 2001-02-08 | 반도체 집적회로장치 |
Country Status (9)
Country | Link |
---|---|
US (3) | US6611458B2 (ko) |
EP (1) | EP1262996B1 (ko) |
JP (1) | JP4191355B2 (ko) |
KR (2) | KR100817343B1 (ko) |
CN (2) | CN101916591B (ko) |
AU (1) | AU2001232248A1 (ko) |
DE (1) | DE60143643D1 (ko) |
TW (1) | TW506135B (ko) |
WO (1) | WO2001059789A1 (ko) |
Families Citing this family (52)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999029015A2 (en) * | 1997-11-28 | 1999-06-10 | Asea Brown Boveri Ab | Method and device for controlling the magnetic flux with an auxiliary winding in a hv ac machine |
US6829737B1 (en) * | 2000-08-30 | 2004-12-07 | Micron Technology, Inc. | Method and system for storing device test information on a semiconductor device using on-device logic for determination of test results |
JP4043703B2 (ja) * | 2000-09-04 | 2008-02-06 | 株式会社ルネサステクノロジ | 半導体装置、マイクロコンピュータ、及びフラッシュメモリ |
DE10120670B4 (de) * | 2001-04-27 | 2008-08-21 | Qimonda Ag | Verfahren zur Reparatur von Hardwarefehlern in Speicherbausteinen |
US6963103B2 (en) * | 2001-08-30 | 2005-11-08 | Micron Technology, Inc. | SRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators |
US7075829B2 (en) * | 2001-08-30 | 2006-07-11 | Micron Technology, Inc. | Programmable memory address and decode circuits with low tunnel barrier interpoly insulators |
US7135734B2 (en) * | 2001-08-30 | 2006-11-14 | Micron Technology, Inc. | Graded composition metal oxide tunnel barrier interpoly insulators |
US7476925B2 (en) * | 2001-08-30 | 2009-01-13 | Micron Technology, Inc. | Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interploy insulators |
US6754108B2 (en) * | 2001-08-30 | 2004-06-22 | Micron Technology, Inc. | DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators |
US7087954B2 (en) * | 2001-08-30 | 2006-08-08 | Micron Technology, Inc. | In service programmable logic arrays with low tunnel barrier interpoly insulators |
JP3821697B2 (ja) | 2001-12-07 | 2006-09-13 | エルピーダメモリ株式会社 | 半導体集積回路装置のベリファイ方法および半導体集積回路装置 |
US6943575B2 (en) * | 2002-07-29 | 2005-09-13 | Micron Technology, Inc. | Method, circuit and system for determining burn-in reliability from wafer level burn-in |
JP2004079138A (ja) * | 2002-08-22 | 2004-03-11 | Renesas Technology Corp | 不揮発性半導体記憶装置 |
EP1453062B1 (en) * | 2003-02-27 | 2006-06-28 | STMicroelectronics S.r.l. | Built-in testing methodology in flash memory |
JP4108519B2 (ja) * | 2003-03-31 | 2008-06-25 | エルピーダメモリ株式会社 | 制御回路、半導体記憶装置、及び制御方法 |
JP4314085B2 (ja) * | 2003-09-08 | 2009-08-12 | パナソニック株式会社 | 不揮発性半導体記憶装置 |
KR100586841B1 (ko) * | 2003-12-15 | 2006-06-07 | 삼성전자주식회사 | 가변 딜레이 제어 방법 및 회로 |
JP4130634B2 (ja) | 2004-01-20 | 2008-08-06 | 松下電器産業株式会社 | 半導体装置 |
JP4124743B2 (ja) | 2004-01-21 | 2008-07-23 | 株式会社ルネサステクノロジ | 相変化メモリ |
JP2005327337A (ja) * | 2004-05-12 | 2005-11-24 | Matsushita Electric Ind Co Ltd | 半導体記憶装置 |
KR100591764B1 (ko) * | 2004-05-18 | 2006-06-22 | 삼성전자주식회사 | 셀 어레이를 가로질러 배선된 신호라인을 갖는 반도체메모리 장치 |
US7102371B1 (en) * | 2004-05-19 | 2006-09-05 | National Semiconductor Corporation | Bilevel probe |
KR100634439B1 (ko) * | 2004-10-26 | 2006-10-16 | 삼성전자주식회사 | 퓨즈프리 회로, 퓨즈프리 반도체 집적회로 및 퓨즈프리불휘발성 메모리 장치, 그리고 퓨즈프리 방법 |
US7373573B2 (en) | 2005-06-06 | 2008-05-13 | International Business Machines Corporation | Apparatus and method for using a single bank of eFuses to successively store testing data from multiple stages of testing |
US7927948B2 (en) | 2005-07-20 | 2011-04-19 | Micron Technology, Inc. | Devices with nanocrystals and methods of formation |
US8110469B2 (en) | 2005-08-30 | 2012-02-07 | Micron Technology, Inc. | Graded dielectric layers |
JP2007172690A (ja) * | 2005-12-19 | 2007-07-05 | Fujitsu Ltd | メモリ冗長選択装置、記憶装置、情報処理装置およびメモリセルの冗長選択の方法 |
JP4764723B2 (ja) * | 2006-01-10 | 2011-09-07 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP4675813B2 (ja) | 2006-03-31 | 2011-04-27 | Okiセミコンダクタ株式会社 | 半導体記憶装置およびその製造方法 |
JP2008181634A (ja) * | 2006-12-26 | 2008-08-07 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
US8055982B2 (en) * | 2007-02-21 | 2011-11-08 | Sigmatel, Inc. | Error correction system and method |
KR100843243B1 (ko) * | 2007-04-18 | 2008-07-02 | 삼성전자주식회사 | 신호의 전송파워를 최적화한 반도체 메모리 장치 및 그파워 초기화 방법 |
KR100888885B1 (ko) * | 2007-04-19 | 2009-03-17 | 삼성전자주식회사 | 리드프레임 및 이를 갖는 반도체 장치 |
JP2008300575A (ja) | 2007-05-30 | 2008-12-11 | Oki Electric Ind Co Ltd | 半導体記憶装置およびその製造方法 |
JP2009070943A (ja) | 2007-09-12 | 2009-04-02 | Oki Semiconductor Co Ltd | 半導体記憶装置およびその製造方法 |
KR100933839B1 (ko) * | 2008-03-10 | 2009-12-24 | 주식회사 하이닉스반도체 | 불휘발성 메모리 소자 및 그 동작 방법 |
JP2009239161A (ja) * | 2008-03-28 | 2009-10-15 | Genusion Inc | 不揮発性半導体記憶装置及びその使用方法 |
KR100998945B1 (ko) * | 2008-09-05 | 2010-12-09 | 주식회사 하이닉스반도체 | 비휘발성 메모리 소자 제조 방법 |
DE102008063429B4 (de) * | 2008-12-31 | 2015-03-26 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Einstellen der Konfiguration eines Mehr-Gatetransistors durch Steuern einzelner Stege |
EP2708021B1 (en) | 2011-05-12 | 2019-07-10 | DePuy Synthes Products, Inc. | Image sensor with tolerance optimizing interconnects |
WO2014018948A2 (en) | 2012-07-26 | 2014-01-30 | Olive Medical Corporation | Camera system with minimal area monolithic cmos image sensor |
KR20150059754A (ko) * | 2012-09-04 | 2015-06-02 | 안트로제네시스 코포레이션 | 조직 생성 방법 |
KR102044827B1 (ko) * | 2012-10-17 | 2019-11-15 | 삼성전자주식회사 | 데이터 로딩 회로 및 이를 포함하는 반도체 메모리 장치 |
EP2967285B1 (en) | 2013-03-15 | 2023-08-16 | DePuy Synthes Products, Inc. | Image sensor synchronization without input clock and data transmission clock |
JP6419774B2 (ja) | 2013-03-15 | 2018-11-07 | デピュイ・シンセス・プロダクツ・インコーポレイテッド | 内視鏡適用における画像センサi/o及びコンダクタ数の最少化 |
US9270174B2 (en) * | 2013-05-12 | 2016-02-23 | Freescale Semiconductor, Inc. | Integrated circuit power management module |
CN104409104B (zh) * | 2014-10-30 | 2018-02-06 | 上海华虹宏力半导体制造有限公司 | 芯片存储单元扰码地址的验证方法 |
CN104616698A (zh) * | 2015-01-28 | 2015-05-13 | 山东华翼微电子技术股份有限公司 | 一种充分利用存储器冗余单元的方法 |
JP6097775B2 (ja) * | 2015-02-16 | 2017-03-15 | 力晶科技股▲ふん▼有限公司 | 半導体記憶装置及び半導体集積回路装置 |
US9343156B1 (en) * | 2015-06-25 | 2016-05-17 | Sandisk Technologies Inc. | Balancing programming speeds of memory cells in a 3D stacked memory |
JP7282749B2 (ja) * | 2018-04-19 | 2023-05-29 | ソニーセミコンダクタソリューションズ株式会社 | 不揮発性記憶回路 |
KR20210145413A (ko) * | 2020-05-25 | 2021-12-02 | 에스케이하이닉스 주식회사 | 메모리 장치 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61123100A (ja) | 1984-11-20 | 1986-06-10 | Fujitsu Ltd | 半導体記憶装置 |
US5089433A (en) | 1988-08-08 | 1992-02-18 | National Semiconductor Corporation | Bipolar field-effect electrically erasable programmable read only memory cell and method of manufacture |
US5163023A (en) | 1989-11-17 | 1992-11-10 | Inmos Limited | Memory circuit capable of replacing a faulty column with a spare column |
JPH05298898A (ja) * | 1992-04-14 | 1993-11-12 | Toshiba Corp | 不揮発性半導体記憶装置 |
Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60201599A (ja) | 1984-03-26 | 1985-10-12 | Hitachi Ltd | 半導体集積回路装置 |
EP0225960B1 (de) * | 1985-12-07 | 1991-03-20 | Deutsche ITT Industries GmbH | CMOS-Inverterkette |
US4794597A (en) * | 1986-03-28 | 1988-12-27 | Mitsubishi Denki Kabushiki Kaisha | Memory device equipped with a RAS circuit |
US5088433A (en) * | 1989-07-31 | 1992-02-18 | Masakazu Osawa | Wave-making resistance suppressing means in ship and ship provided therewith |
JPH03179780A (ja) * | 1989-12-07 | 1991-08-05 | Fujitsu Ltd | 半導体装置 |
KR920005798A (ko) * | 1990-04-18 | 1992-04-03 | 미타 가쓰시게 | 반도체 집적회로 |
JP3083547B2 (ja) | 1990-07-12 | 2000-09-04 | 株式会社日立製作所 | 半導体集積回路装置 |
JPH05114300A (ja) * | 1991-05-21 | 1993-05-07 | Citizen Watch Co Ltd | 半導体記憶装置 |
US5278439A (en) * | 1991-08-29 | 1994-01-11 | Ma Yueh Y | Self-aligned dual-bit split gate (DSG) flash EEPROM cell |
JPH05314789A (ja) | 1992-05-14 | 1993-11-26 | Fujitsu Ltd | 冗長アドレス記憶回路 |
JP2596695B2 (ja) | 1993-05-07 | 1997-04-02 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Eeprom |
JP3212421B2 (ja) | 1993-09-20 | 2001-09-25 | 富士通株式会社 | 不揮発性半導体記憶装置 |
US5466231A (en) * | 1993-11-04 | 1995-11-14 | Merocel Corporation | Laminated sponge device |
JPH07287994A (ja) | 1994-04-19 | 1995-10-31 | Mitsubishi Electric Corp | 半導体記憶装置及びその製造方法 |
KR0126101B1 (ko) * | 1994-07-07 | 1997-12-26 | 김주용 | 리페어 마스크 형성방법 |
KR0161399B1 (ko) * | 1995-03-13 | 1998-12-01 | 김광호 | 불휘발성 메모리장치 및 그 제조방법 |
US5765544A (en) * | 1995-06-05 | 1998-06-16 | Vigansky, Jr.; Charles E. | Flow-through humidifier for mobile home furnace |
US6166293A (en) * | 1996-07-18 | 2000-12-26 | The Salk Institute For Biological Studies | Method of increasing growth and yield in plants |
JPH10149694A (ja) * | 1996-11-19 | 1998-06-02 | Toshiba Microelectron Corp | 半導体メモリおよびデータ書換回路 |
US5949703A (en) * | 1996-12-26 | 1999-09-07 | Kabushiki Kaisha Toshiba | Semiconductor memory device in which data in programmable ROM can be apparently rewritten |
JP3519583B2 (ja) | 1997-09-19 | 2004-04-19 | 株式会社東芝 | 不揮発性半導体記憶装置およびその製造方法 |
US6005270A (en) * | 1997-11-10 | 1999-12-21 | Sony Corporation | Semiconductor nonvolatile memory device and method of production of same |
JPH11197652A (ja) | 1998-01-06 | 1999-07-27 | Sanden Corp | 浄水殺菌装置 |
JP2000123591A (ja) * | 1998-10-16 | 2000-04-28 | Fujitsu Ltd | 不揮発性半導体記憶装置 |
DE60043651D1 (de) * | 1999-02-01 | 2010-02-25 | Renesas Tech Corp | Integrierte halbleiterschaltung und nichtflüchtiges speicherelement |
-
2000
- 2000-02-10 JP JP2000038167A patent/JP4191355B2/ja not_active Expired - Lifetime
-
2001
- 2001-01-30 TW TW090101806A patent/TW506135B/zh not_active IP Right Cessation
- 2001-02-08 CN CN201010003815.7A patent/CN101916591B/zh not_active Expired - Lifetime
- 2001-02-08 AU AU2001232248A patent/AU2001232248A1/en not_active Abandoned
- 2001-02-08 KR KR1020077023259A patent/KR100817343B1/ko active IP Right Grant
- 2001-02-08 WO PCT/JP2001/000887 patent/WO2001059789A1/ja active Application Filing
- 2001-02-08 EP EP01904349A patent/EP1262996B1/en not_active Expired - Lifetime
- 2001-02-08 DE DE60143643T patent/DE60143643D1/de not_active Expired - Lifetime
- 2001-02-08 KR KR1020027006867A patent/KR100816924B1/ko active IP Right Grant
- 2001-02-08 CN CN01804803A patent/CN100590739C/zh not_active Expired - Lifetime
- 2001-02-12 US US09/780,393 patent/US6611458B2/en not_active Expired - Lifetime
-
2003
- 2003-06-25 US US10/602,684 patent/US6894944B2/en not_active Expired - Lifetime
-
2005
- 2005-03-07 US US11/072,309 patent/US7149113B2/en not_active Expired - Lifetime
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61123100A (ja) | 1984-11-20 | 1986-06-10 | Fujitsu Ltd | 半導体記憶装置 |
US5089433A (en) | 1988-08-08 | 1992-02-18 | National Semiconductor Corporation | Bipolar field-effect electrically erasable programmable read only memory cell and method of manufacture |
US5163023A (en) | 1989-11-17 | 1992-11-10 | Inmos Limited | Memory circuit capable of replacing a faulty column with a spare column |
JPH05298898A (ja) * | 1992-04-14 | 1993-11-12 | Toshiba Corp | 不揮発性半導体記憶装置 |
Also Published As
Publication number | Publication date |
---|---|
CN101916591A (zh) | 2010-12-15 |
EP1262996B1 (en) | 2010-12-15 |
JP4191355B2 (ja) | 2008-12-03 |
EP1262996A1 (en) | 2002-12-04 |
DE60143643D1 (de) | 2011-01-27 |
AU2001232248A1 (en) | 2001-08-20 |
US20050152186A1 (en) | 2005-07-14 |
KR20070108570A (ko) | 2007-11-12 |
TW506135B (en) | 2002-10-11 |
WO2001059789A1 (fr) | 2001-08-16 |
KR100817343B1 (ko) | 2008-03-27 |
US6894944B2 (en) | 2005-05-17 |
US6611458B2 (en) | 2003-08-26 |
US20010019499A1 (en) | 2001-09-06 |
CN1398407A (zh) | 2003-02-19 |
CN100590739C (zh) | 2010-02-17 |
CN101916591B (zh) | 2014-05-07 |
EP1262996A4 (en) | 2007-06-27 |
US7149113B2 (en) | 2006-12-12 |
JP2001229690A (ja) | 2001-08-24 |
KR20020080340A (ko) | 2002-10-23 |
US20040004879A1 (en) | 2004-01-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100816924B1 (ko) | 반도체 집적회로장치 | |
KR100789517B1 (ko) | 반도체 장치 | |
US5138427A (en) | Semiconductor device having a particular structure allowing for voltage stress test application | |
JP3236105B2 (ja) | 不揮発性半導体記憶装置及びその動作試験方法 | |
US6496413B2 (en) | Semiconductor memory device for effecting erasing operation in block unit | |
US6177830B1 (en) | High voltage charge pump using standard sub 0.35 micron CMOS process | |
US5847995A (en) | Nonvolatile semiconductor memory device having a plurality of blocks provided on a plurality of electrically isolated wells | |
JP4322809B2 (ja) | Mramの弱ビットを特定する方法及び回路 | |
US6208570B1 (en) | Redundancy test method for a semiconductor memory | |
JP2009277291A (ja) | 不揮発性半導体記憶装置 | |
US6741510B2 (en) | Semiconductor memory device capable of performing burn-in test at high speed | |
JP3821697B2 (ja) | 半導体集積回路装置のベリファイ方法および半導体集積回路装置 | |
JP4152422B2 (ja) | 半導体集積回路装置 | |
KR950000342B1 (ko) | 여분 셀 어레이를 갖는 소거 가능 프로그래머블 리드온리 메모리, 및 이 메모리의 스트레스 시험방법 | |
KR100434319B1 (ko) | 반도체 기억 소자의 리페어 회로 | |
JP2009004087A (ja) | 半導体集積回路装置 | |
JP3490034B2 (ja) | 半導体記憶装置 | |
JP2001273783A (ja) | 半導体記憶装置 | |
JPH07254299A (ja) | 記憶セルのトランジスタ用バイアス回路 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E902 | Notification of reason for refusal | ||
A107 | Divisional application of patent | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20130227 Year of fee payment: 6 |
|
FPAY | Annual fee payment |
Payment date: 20140220 Year of fee payment: 7 |
|
FPAY | Annual fee payment |
Payment date: 20150224 Year of fee payment: 8 |
|
FPAY | Annual fee payment |
Payment date: 20160219 Year of fee payment: 9 |
|
FPAY | Annual fee payment |
Payment date: 20170221 Year of fee payment: 10 |
|
FPAY | Annual fee payment |
Payment date: 20180302 Year of fee payment: 11 |