KR100651115B1 - 반도체 장치 및 그 제조 방법 - Google Patents
반도체 장치 및 그 제조 방법 Download PDFInfo
- Publication number
- KR100651115B1 KR100651115B1 KR1020050091979A KR20050091979A KR100651115B1 KR 100651115 B1 KR100651115 B1 KR 100651115B1 KR 1020050091979 A KR1020050091979 A KR 1020050091979A KR 20050091979 A KR20050091979 A KR 20050091979A KR 100651115 B1 KR100651115 B1 KR 100651115B1
- Authority
- KR
- South Korea
- Prior art keywords
- insulating film
- semiconductor substrate
- hole
- electrode pad
- semiconductor device
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 244
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims description 52
- 239000000758 substrate Substances 0.000 claims abstract description 171
- 238000005530 etching Methods 0.000 claims description 39
- 238000004070 electrodeposition Methods 0.000 claims description 35
- 239000011810 insulating material Substances 0.000 claims description 19
- 229910010272 inorganic material Inorganic materials 0.000 claims description 13
- 239000011147 inorganic material Substances 0.000 claims description 13
- 238000007639 printing Methods 0.000 claims description 12
- 239000011368 organic material Substances 0.000 claims description 8
- 239000004642 Polyimide Substances 0.000 claims description 6
- 229920001721 polyimide Polymers 0.000 claims description 6
- 239000004593 Epoxy Substances 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- 230000000694 effects Effects 0.000 claims description 3
- 238000003384 imaging method Methods 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims description 2
- 230000003014 reinforcing effect Effects 0.000 claims 3
- 239000012790 adhesive layer Substances 0.000 claims 1
- 239000004020 conductor Substances 0.000 abstract description 19
- 239000010410 layer Substances 0.000 description 42
- 239000002184 metal Substances 0.000 description 27
- 229910052751 metal Inorganic materials 0.000 description 27
- 238000005229 chemical vapour deposition Methods 0.000 description 15
- 230000001681 protective effect Effects 0.000 description 12
- 238000001312 dry etching Methods 0.000 description 10
- 239000000853 adhesive Substances 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 8
- 239000010949 copper Substances 0.000 description 7
- 230000001070 adhesive effect Effects 0.000 description 6
- 239000011521 glass Substances 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 238000009713 electroplating Methods 0.000 description 5
- 238000009413 insulation Methods 0.000 description 5
- 239000007788 liquid Substances 0.000 description 5
- 238000007747 plating Methods 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000002787 reinforcement Effects 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 238000000059 patterning Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000002244 precipitate Substances 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02377—Fan-in arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05023—Disposition the whole internal layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14618—Containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
Claims (13)
- 반도체 기판의 제1 면에 무기 재료로 이루어지는 제1 절연막을 개재하여 형성된 전극 패드를 갖고, 상기 전극 패드와 상기 반도체 기판의 제2 면에 존재하는 외부 접속용 단자를 접속하는 관통 전극을 갖는 반도체 장치의 제조 방법으로서,제1 면에 상기 제1 절연막과 상기 전극 패드가 형성된 상기 반도체 기판에 대하여, 그 제2 면에 무기 재료로 이루어지는 제2 절연막을 형성하고, 상기 전극 패드의 바로 아래에서 상기 제2 절연막을 개구하는 제1 스텝과,상기 제2 절연막을 마스크로 하여, 상기 반도체 기판에 제1 절연막에 도달하는 관통 구멍을, 제2 절연막의 개구연(opening edge)보다 그 관통 구멍을 후퇴시키도록 형성하는 제2 스텝과,상기 관통 구멍의 내벽에 유기 재료로 이루어지는 제3 절연막을 형성하는 제3 스텝과,상기 제2 절연막을 마스크로 하여, 상기 제1 절연막을 에칭하고, 상기 전극 패드 이면을 상기 반도체 기판의 제2 면측에 노출시키는 제4 스텝과,상기 관통 구멍 내에서 상기 관통 전극으로 됨과 함께, 상기 전극 패드와 상기 외부 접속용 단자를 접속하는 도전부를 형성하는 제5 스텝을 포함하는 반도체 장치의 제조 방법.
- 제1항에 있어서,상기 제2 스텝에서는, 제2 절연막을 마스크로 하여 반도체 기판을 이방성 에칭하고, 또한, 반도체 기판을 등방성 에칭함으로써, 상기 관통 구멍을 제2 절연막의 개구연보다 후퇴시키도록 형성하는 반도체 장치의 제조 방법.
- 제1항에 있어서,상기 제2 스텝에서는, 제2 절연막을 마스크로 하여 반도체 기판을 웨트 에칭(wet etching)함으로써, 상기 관통 구멍을 제2 절연막의 개구연보다 후퇴시키도록 형성하는 반도체 장치의 제조 방법.
- 제1항에 있어서,상기 제2 절연막은, 상기 제2 스텝에서의 반도체 기판의 에칭 시에 대하여, 마스크 효과가 있는 에칭 선택비를 갖는 반도체 장치의 제조 방법.
- 제1항에 있어서,상기 제3 스텝에서는, 반도체 기판을 음극으로 하는 전착에 의해 상기 제3 절연막을 형성하는 반도체 장치의 제조 방법.
- 제1항에 있어서,상기 제3 스텝에서는, 인쇄법에 의해 유기 절연 재료를 상기 관통 구멍에 매립하고, 또한, 제2 절연막을 마스크로 하여 이방성 에칭을 행함으로써 상기 제3 절 연막을 형성하는 반도체 장치의 제조 방법.
- 제6항에 있어서,상기 제3 스텝에서는, 진공 인쇄법에 의해 유기 절연 재료를 상기 관통 구멍에 매립하는 반도체 장치의 제조 방법.
- 제5항에 있어서,상기 제3 절연막이 폴리이미드 혹은 에폭시인 반도체 장치의 제조 방법.
- 제6항에 있어서,상기 제3 절연막이 폴리이미드 혹은 에폭시인 반도체 장치의 제조 방법.
- 반도체 기판의 제1 면에 무기 재료로 이루어지는 제1 절연막을 개재하여 형성된 전극 패드와,상기 전극 패드와 상기 반도체 기판의 제2 면에 존재하는 외부 접속용 단자를 접속하는 관통 전극을 포함하고,제1 면에 상기 제1 절연막과 상기 전극 패드가 형성된 상기 반도체 기판에 대하여, 상기 전극 패드의 바로 아래에, 상기 반도체 기판에 관통 구멍이 형성되어 있고, 상기 반도체 기판의 제2 면에는 제2 절연막이 형성되어 있으며, 상기 관통 구멍의 내벽에는 제3 절연막이 형성되어 있는 것과 함께,상기 제2 절연막의 개구연과 상기 제3 절연막의 내주면은, 반도체 기판의 제2 면측에서 봐서 일치하도록 형성되는 반도체 장치.
- 제10항의 반도체 장치를 복수개 적층하여 이루어지는 반도체 장치.
- 제10항에 있어서,상기 반도체 기판의 파손을 방지하기 위한 보강판이, 상기 반도체 기판의 제1 면측에 접착층을 개재하여 접합되어 있는 반도체 장치.
- 제11항에 있어서,상기 반도체 장치는, 상기 보강판이 광 투과성 부재이고, 상기 반도체 기판과 상기 보강판 사이에는 CCD 센서가 배치된 고체 촬상 소자인 반도체 장치.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004291863A JP4246132B2 (ja) | 2004-10-04 | 2004-10-04 | 半導体装置およびその製造方法 |
JPJP-P-2004-00291863 | 2004-10-04 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20060051915A KR20060051915A (ko) | 2006-05-19 |
KR100651115B1 true KR100651115B1 (ko) | 2006-12-01 |
Family
ID=36124743
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020050091979A KR100651115B1 (ko) | 2004-10-04 | 2005-09-30 | 반도체 장치 및 그 제조 방법 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7365440B2 (ko) |
JP (1) | JP4246132B2 (ko) |
KR (1) | KR100651115B1 (ko) |
TW (1) | TWI297206B (ko) |
Families Citing this family (61)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8084866B2 (en) * | 2003-12-10 | 2011-12-27 | Micron Technology, Inc. | Microelectronic devices and methods for filling vias in microelectronic devices |
US20050247894A1 (en) | 2004-05-05 | 2005-11-10 | Watkins Charles M | Systems and methods for forming apertures in microfeature workpieces |
US7232754B2 (en) | 2004-06-29 | 2007-06-19 | Micron Technology, Inc. | Microelectronic devices and methods for forming interconnects in microelectronic devices |
SG120200A1 (en) | 2004-08-27 | 2006-03-28 | Micron Technology Inc | Slanted vias for electrical circuits on circuit boards and other substrates |
US7300857B2 (en) | 2004-09-02 | 2007-11-27 | Micron Technology, Inc. | Through-wafer interconnects for photoimager and memory wafers |
US8278738B2 (en) * | 2005-02-17 | 2012-10-02 | Sharp Kabushiki Kaisha | Method of producing semiconductor device and semiconductor device |
JP4097660B2 (ja) * | 2005-04-06 | 2008-06-11 | シャープ株式会社 | 半導体装置 |
US7795134B2 (en) | 2005-06-28 | 2010-09-14 | Micron Technology, Inc. | Conductive interconnect structures and formation methods using supercritical fluids |
US7262134B2 (en) | 2005-09-01 | 2007-08-28 | Micron Technology, Inc. | Microfeature workpieces and methods for forming interconnects in microfeature workpieces |
US7863187B2 (en) | 2005-09-01 | 2011-01-04 | Micron Technology, Inc. | Microfeature workpieces and methods for forming interconnects in microfeature workpieces |
TWI311357B (en) * | 2006-01-05 | 2009-06-21 | Advanced Semiconductor Eng | Wafer-level chip packaging process and chip package structure |
US7749899B2 (en) | 2006-06-01 | 2010-07-06 | Micron Technology, Inc. | Microelectronic workpieces and methods and systems for forming interconnects in microelectronic workpieces |
US7629249B2 (en) | 2006-08-28 | 2009-12-08 | Micron Technology, Inc. | Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods |
US7902643B2 (en) | 2006-08-31 | 2011-03-08 | Micron Technology, Inc. | Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods |
JP2008103387A (ja) * | 2006-10-17 | 2008-05-01 | Murata Mfg Co Ltd | 半導体装置 |
US7791199B2 (en) | 2006-11-22 | 2010-09-07 | Tessera, Inc. | Packaged semiconductor chips |
US8569876B2 (en) | 2006-11-22 | 2013-10-29 | Tessera, Inc. | Packaged semiconductor chips with array |
JP4403424B2 (ja) * | 2006-11-30 | 2010-01-27 | ソニー株式会社 | 固体撮像装置 |
US7598163B2 (en) * | 2007-02-15 | 2009-10-06 | John Callahan | Post-seed deposition process |
JP5584474B2 (ja) * | 2007-03-05 | 2014-09-03 | インヴェンサス・コーポレイション | 貫通ビアによって前面接点に接続された後面接点を有するチップ |
US8445325B2 (en) | 2007-05-04 | 2013-05-21 | Stats Chippac, Ltd. | Package-in-package using through-hole via die on saw streets |
US7829998B2 (en) | 2007-05-04 | 2010-11-09 | Stats Chippac, Ltd. | Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer |
US7723159B2 (en) * | 2007-05-04 | 2010-05-25 | Stats Chippac, Ltd. | Package-on-package using through-hole via die on saw streets |
JPWO2008153082A1 (ja) * | 2007-06-12 | 2010-08-26 | 住友ベークライト株式会社 | 樹脂組成物、埋め込み材、絶縁層および半導体装置 |
JP2010535427A (ja) | 2007-07-31 | 2010-11-18 | テッセラ,インコーポレイテッド | 貫通シリコンビアを使用する半導体実装プロセス |
SG150410A1 (en) | 2007-08-31 | 2009-03-30 | Micron Technology Inc | Partitioned through-layer via and associated systems and methods |
JP5311609B2 (ja) * | 2007-10-30 | 2013-10-09 | 新光電気工業株式会社 | シリコンインターポーザの製造方法およびシリコンインターポーザと、これを用いた半導体装置用パッケージおよび半導体装置 |
JP5197219B2 (ja) * | 2007-11-22 | 2013-05-15 | パナソニック株式会社 | 半導体装置およびその製造方法 |
US7884015B2 (en) * | 2007-12-06 | 2011-02-08 | Micron Technology, Inc. | Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods |
JP2009283503A (ja) * | 2008-05-19 | 2009-12-03 | Panasonic Corp | 半導体装置及びその製造方法 |
JP2010010324A (ja) * | 2008-06-26 | 2010-01-14 | Toshiba Corp | 半導体装置及び半導体装置の製造方法 |
JP5262350B2 (ja) * | 2008-06-27 | 2013-08-14 | Jsr株式会社 | 絶縁性被膜を有する構造体及びその製造方法並びに電子部品 |
JP2010040862A (ja) * | 2008-08-06 | 2010-02-18 | Fujikura Ltd | 半導体装置 |
WO2010058503A1 (ja) * | 2008-11-21 | 2010-05-27 | パナソニック株式会社 | 半導体装置およびその製造方法 |
JP5596919B2 (ja) * | 2008-11-26 | 2014-09-24 | キヤノン株式会社 | 半導体装置の製造方法 |
JP2010129952A (ja) * | 2008-12-01 | 2010-06-10 | Nippon Telegr & Teleph Corp <Ntt> | 貫通電極配線の製造方法 |
US8759949B2 (en) * | 2009-04-30 | 2014-06-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer backside structures having copper pillars |
KR101026489B1 (ko) * | 2009-08-10 | 2011-04-01 | 주식회사 하이닉스반도체 | 반도체 패키지 및 이의 제조 방법 |
US8716130B2 (en) * | 2010-07-01 | 2014-05-06 | Tokyo Electron Limited | Method of manufacturing semiconductor device |
US8269316B2 (en) * | 2010-07-07 | 2012-09-18 | Victory Gain Group Corporation | Silicon based substrate and manufacturing method thereof |
CN102339810B (zh) * | 2010-07-20 | 2015-07-22 | 因厄费博斯由勒有限责任公司 | 硅基基板及其制作方法 |
US8796135B2 (en) | 2010-07-23 | 2014-08-05 | Tessera, Inc. | Microelectronic elements with rear contacts connected with via first or via middle structures |
US8791575B2 (en) | 2010-07-23 | 2014-07-29 | Tessera, Inc. | Microelectronic elements having metallic pads overlying vias |
US9640437B2 (en) | 2010-07-23 | 2017-05-02 | Tessera, Inc. | Methods of forming semiconductor elements using micro-abrasive particle stream |
US8847380B2 (en) | 2010-09-17 | 2014-09-30 | Tessera, Inc. | Staged via formation from both sides of chip |
US8610259B2 (en) | 2010-09-17 | 2013-12-17 | Tessera, Inc. | Multi-function and shielded 3D interconnects |
US8637968B2 (en) | 2010-12-02 | 2014-01-28 | Tessera, Inc. | Stacked microelectronic assembly having interposer connecting active chips |
US8587126B2 (en) | 2010-12-02 | 2013-11-19 | Tessera, Inc. | Stacked microelectronic assembly with TSVs formed in stages with plural active chips |
US8736066B2 (en) | 2010-12-02 | 2014-05-27 | Tessera, Inc. | Stacked microelectronic assemby with TSVS formed in stages and carrier above chip |
KR101732975B1 (ko) | 2010-12-03 | 2017-05-08 | 삼성전자주식회사 | 반도체 장치의 제조 방법 |
US8610264B2 (en) * | 2010-12-08 | 2013-12-17 | Tessera, Inc. | Compliant interconnects in wafers |
JP5357241B2 (ja) | 2011-08-10 | 2013-12-04 | 新光電気工業株式会社 | 半導体装置及び半導体装置の製造方法 |
JP5385471B2 (ja) * | 2011-08-10 | 2014-01-08 | 新光電気工業株式会社 | 半導体装置の製造方法 |
WO2013062590A1 (en) * | 2011-10-28 | 2013-05-02 | Intel Corporation | 3d interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach |
JP6099192B2 (ja) * | 2012-12-13 | 2017-03-22 | 国立研究開発法人産業技術総合研究所 | 積層lsiチップ |
KR102031908B1 (ko) | 2013-02-06 | 2019-10-14 | 삼성전자주식회사 | 관통 전극을 갖는 반도체 소자 및 그 형성 방법 |
JP6235785B2 (ja) * | 2013-03-18 | 2017-11-22 | 日本電子材料株式会社 | プローブカード用ガイド板およびプローブカード用ガイド板の製造方法 |
KR102142366B1 (ko) | 2013-11-14 | 2020-08-07 | 삼성전자 주식회사 | 반도체 집적 회로 소자 및 그 제조 방법, 반도체 패키지 |
TWI645483B (zh) * | 2017-06-30 | 2018-12-21 | 同泰電子科技股份有限公司 | 適於形成包括通孔的基板結構的製作方法 |
CN109634458B (zh) * | 2018-12-04 | 2022-04-15 | 业成科技(成都)有限公司 | 触控面板及其制造方法 |
TWI726375B (zh) * | 2019-08-01 | 2021-05-01 | 睿明科技股份有限公司 | 基板形成通孔的製作方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3186941B2 (ja) | 1995-02-07 | 2001-07-11 | シャープ株式会社 | 半導体チップおよびマルチチップ半導体モジュール |
US6620731B1 (en) * | 1997-12-18 | 2003-09-16 | Micron Technology, Inc. | Method for fabricating semiconductor components and interconnects with contacts on opposing sides |
JP3597754B2 (ja) | 2000-04-24 | 2004-12-08 | Necエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
TW552694B (en) | 2001-08-31 | 2003-09-11 | Hitachi Chemical Co Ltd | Wiring substrate, semiconductor device and the manufacturing method thereof |
JP2003289073A (ja) * | 2002-01-22 | 2003-10-10 | Canon Inc | 半導体装置および半導体装置の製造方法 |
TW558823B (en) | 2002-04-10 | 2003-10-21 | Via Tech Inc | Through-hole process of integrated circuit substrate |
JP4212293B2 (ja) | 2002-04-15 | 2009-01-21 | 三洋電機株式会社 | 半導体装置の製造方法 |
TW530344B (en) | 2002-05-10 | 2003-05-01 | Walsin Advanced Electronics | Conductive ball for electrical connection and applications thereof |
TWI229435B (en) * | 2002-06-18 | 2005-03-11 | Sanyo Electric Co | Manufacture of semiconductor device |
TW569416B (en) | 2002-12-19 | 2004-01-01 | Via Tech Inc | High density multi-chip module structure and manufacturing method thereof |
-
2004
- 2004-10-04 JP JP2004291863A patent/JP4246132B2/ja active Active
-
2005
- 2005-09-28 US US11/236,806 patent/US7365440B2/en active Active
- 2005-09-30 KR KR1020050091979A patent/KR100651115B1/ko active IP Right Grant
- 2005-10-04 TW TW094134687A patent/TWI297206B/zh active
Also Published As
Publication number | Publication date |
---|---|
US7365440B2 (en) | 2008-04-29 |
KR20060051915A (ko) | 2006-05-19 |
US20060071347A1 (en) | 2006-04-06 |
JP2006108328A (ja) | 2006-04-20 |
JP4246132B2 (ja) | 2009-04-02 |
TW200627616A (en) | 2006-08-01 |
TWI297206B (en) | 2008-05-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100651115B1 (ko) | 반도체 장치 및 그 제조 방법 | |
KR100653294B1 (ko) | 반도체 장치 및 그 제조 방법 | |
US8174090B2 (en) | Packaging structure | |
US7180149B2 (en) | Semiconductor package with through-hole | |
KR100938970B1 (ko) | 반도체 장치 및 그 제조 방법 | |
US8541820B2 (en) | Semiconductor device including through-electrode | |
US9318459B2 (en) | Through via package | |
US7808064B2 (en) | Semiconductor package including through-hole electrode and light-transmitting substrate | |
US8546900B2 (en) | 3D integration microelectronic assembly for integrated circuit devices | |
TWI387075B (zh) | 半導體封裝以及攝影機模組 | |
US20160276385A1 (en) | Semiconductor device and method of manufacturing the same | |
US7919348B2 (en) | Methods for protecting imaging elements of photoimagers during back side processing | |
US9520322B2 (en) | Semiconductor device and method for manufacturing same | |
US20090059055A1 (en) | Optical device and method for fabricating the same | |
US9966400B2 (en) | Photosensitive module and method for forming the same | |
US8610284B2 (en) | Semiconductor device and electronic device | |
JP5101157B2 (ja) | 半導体装置の製造方法 | |
JP2003007909A (ja) | 半導体装置の製造方法とそれによる半導体装置およびこれを用いた電子機器 | |
JP4425235B2 (ja) | 半導体装置及びその製造方法 | |
JP4334397B2 (ja) | 半導体装置及びその製造方法 | |
JP4764710B2 (ja) | 半導体装置とその製造方法 | |
JP2005072489A (ja) | 半導体装置の製造方法および半導体装置 | |
JP4443549B2 (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20121114 Year of fee payment: 7 |
|
FPAY | Annual fee payment |
Payment date: 20131031 Year of fee payment: 8 |
|
FPAY | Annual fee payment |
Payment date: 20141106 Year of fee payment: 9 |
|
FPAY | Annual fee payment |
Payment date: 20151106 Year of fee payment: 10 |
|
FPAY | Annual fee payment |
Payment date: 20161107 Year of fee payment: 11 |
|
FPAY | Annual fee payment |
Payment date: 20171108 Year of fee payment: 12 |
|
FPAY | Annual fee payment |
Payment date: 20181107 Year of fee payment: 13 |
|
FPAY | Annual fee payment |
Payment date: 20191114 Year of fee payment: 14 |