KR100527080B1 - 박막 트랜지스터 어레이 기판의 제조방법 - Google Patents
박막 트랜지스터 어레이 기판의 제조방법 Download PDFInfo
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- KR100527080B1 KR100527080B1 KR10-1999-0031420A KR19990031420A KR100527080B1 KR 100527080 B1 KR100527080 B1 KR 100527080B1 KR 19990031420 A KR19990031420 A KR 19990031420A KR 100527080 B1 KR100527080 B1 KR 100527080B1
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- 239000000758 substrate Substances 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title abstract description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 55
- 239000004065 semiconductor Substances 0.000 claims abstract description 33
- 239000002184 metal Substances 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 30
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 23
- 238000000151 deposition Methods 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 15
- 230000001681 protective effect Effects 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims abstract description 7
- 238000002161 passivation Methods 0.000 claims abstract description 5
- 238000003860 storage Methods 0.000 claims description 13
- 239000011368 organic material Substances 0.000 claims description 3
- 239000000049 pigment Substances 0.000 claims description 3
- 239000011347 resin Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- 239000010408 film Substances 0.000 abstract description 62
- 239000010409 thin film Substances 0.000 abstract description 11
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 description 9
- 239000011521 glass Substances 0.000 description 7
- 230000003071 parasitic effect Effects 0.000 description 6
- 230000006866 deterioration Effects 0.000 description 4
- 230000002411 adverse Effects 0.000 description 1
- 238000009125 cardiac resynchronization therapy Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
Claims (6)
- 투명성 절연 기판 상에 게이트 라인을 형성하는 단계;상기 게이트 라인을 덮도록, 상기 투명성 절연 기판 상에 게이트 절연막을 증착하는 단계;상기 게이트 라인 상부의 게이트 절연막 상에 반도체층을 형성하는 단계;상기 결과물의 상부에 제1두께로 제1감광막을 도포하는 단계;상기 제1감광막을 게이트 라인을 마스크로 하여 백 노광하고, 상기 백 노광된 제1감광막을 현상하여 상기 반도체층 상에 제1감광막 패턴을 형성하는 단계;상기 결과물 상에 도핑된비정질실리콘층과 금속막을 차례로 증착하는 단계;상기 금속막 상에 제1두께보다 작은 제2두께로 제2감광막을 도포하는 단계;상기 제2감광막을 노광 및 현상하여, 소오스 및 드레인 전극을 정의하는 제2감광막 패턴을 형성하는 단계;상기 제1 및 제2감광막 패턴을 마스크로해서 금속막과 도핑된 비정질실리콘층을 식각하여, 소오스 및 드레인 전극과 오믹층을 형성하는 단계;상기 제1 및 제2감광막 패턴을 제거하는 단계;상기 결과물의 상부에 보호막을 증착하는 단계; 및상기 보호막 상에 소오스 전극과 콘택되는 화소전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 박막 트랜지스터 어레이 기판의 제조방법.
- 제 1 항에 있어서, 상기 제1감광막은 내열성의 유기물, 안료, 염료 또는 레진인 것을 특징으로 하는 박막 트랜지스터 어레이 기판의 제조방법.
- 제 1 항에 있어서, 상기 제1감광막은 1∼3㎛ 두께로 도포하고, 상기 제2감광막은 0.1∼1.5㎛ 두께로 도포하는 것을 특징으로 하는 박막 트랜지스터 어레이 기판의 제조방법.
- 투명성 절연 기판 상에 게이트 라인과 스토리지 라인 및 게이트 패드를 형성하는 단계;상기 라인들 및 패드를 덮도록 상기 투명성 절연 기판의 전면 상에 게이트 절연막을 증착하는 단계;상기 게이트 라인 상부의 게이트 절연막 상에 반도체층을 형성하는 단계;상기 결과물의 상부에 제1두께로 제1감광막을 도포하는 단계;상기 제1감광막을 게이트 라인과 스토리지 라인 및 게이트 패드를 마스크로해서 백 노광하고, 상기 백 노광된 제1감광막을 현상하여 상기 게이트 라인 상부의 반도체층과 스토리지 라인 및 게이트 패드 상부의 게이트 절연막 상에 제1감광막 패턴을 형성하는 단계;상기 결과물 상에 도핑된비정질실리콘층과 금속막을 차례로 증착하는 단계;상기 금속막 상에 제1두께보다 작은 제2두께로 제2감광막을 도포하는 단계;상기 제2감광막을 노광 및 현상하여 소오스 및 드레인 전극을 정의하고, 그리고, 데이터 패드를 정의하는 제2감광막 패턴을 형성하는 단계;상기 제1 및 제2감광막 패턴을 마스크로해서, 금속막과 도핑된 비정질실리콘층을 식각하여, 오믹층 및 소오스/드레인 전극과 데이터 패드를 형성하는 단계;상기 제1 및 제2감광막 패턴을 제거하는 단계;상기 결과물의 상부에 보호막을 증착하는 단계; 및상기 보호막 상에 소오스 전극과 콘택되는 화소전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 박막 트랜지스터 어레이 기판의 제조방법.
- 제 4 항에 있어서, 상기 제1감광막은 내열성의 유기물, 안료, 염료 또는 레진인 것을 특징으로 하는 박막 트랜지스터 어레이 기판의 제조방법.
- 제 4 항에 있어서, 상기 제1감광막은 1∼3㎛ 두께로 도포하고, 상기 제2감광막은 0.1∼1.5㎛ 두께로 도포하는 것을 특징으로 하는 박막 트랜지스터 어레이 기판의 제조방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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KR10-1999-0031420A KR100527080B1 (ko) | 1999-07-30 | 1999-07-30 | 박막 트랜지스터 어레이 기판의 제조방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR10-1999-0031420A KR100527080B1 (ko) | 1999-07-30 | 1999-07-30 | 박막 트랜지스터 어레이 기판의 제조방법 |
Publications (2)
Publication Number | Publication Date |
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KR20010011857A KR20010011857A (ko) | 2001-02-15 |
KR100527080B1 true KR100527080B1 (ko) | 2005-11-09 |
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KR10-1999-0031420A KR100527080B1 (ko) | 1999-07-30 | 1999-07-30 | 박막 트랜지스터 어레이 기판의 제조방법 |
Country Status (1)
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KR (1) | KR100527080B1 (ko) |
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1999
- 1999-07-30 KR KR10-1999-0031420A patent/KR100527080B1/ko not_active IP Right Cessation
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KR20010011857A (ko) | 2001-02-15 |
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