KR20030000483A - Fabricating method for semiconductor device - Google Patents

Fabricating method for semiconductor device Download PDF

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Publication number
KR20030000483A
KR20030000483A KR1020010036277A KR20010036277A KR20030000483A KR 20030000483 A KR20030000483 A KR 20030000483A KR 1020010036277 A KR1020010036277 A KR 1020010036277A KR 20010036277 A KR20010036277 A KR 20010036277A KR 20030000483 A KR20030000483 A KR 20030000483A
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South Korea
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layer
forming
via contact
insulating film
metal
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KR1020010036277A
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Korean (ko)
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홍은석
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주식회사 하이닉스반도체
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Publication of KR20030000483A publication Critical patent/KR20030000483A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02131—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being halogen doped silicon oxides, e.g. FSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A fabrication method of a semiconductor device is provided to prevent losses of a first planarized insulating layer due to a misalignment and to reduce a dielectric constant by forming an air-gap between metal interconnections. CONSTITUTION: After forming a first planarized insulating layer(52) on a substrate(51), a first adhesive layer(53), a first metal film(54) and a first interlayer dielectric(55) are sequentially formed. A via contact hole is formed by selectively etching the first interlayer dielectric. A via contact plug is formed by filling the via contact hole, After forming a second interlayer dielectric(60) on the resultant structure, an air-gap(59) is formed between the first metal lines. After forming a second planarized insulating layer(61) on the resultant structure, the via contact plug is exposed by polishing the second planarized insulating layer(61).

Description

반도체소자의 제조방법{Fabricating method for semiconductor device}Fabrication method for semiconductor device

본 발명은 반도체소자의 제조방법에 관한 것으로서, 보다 상세하게 다층 금속배선을 형성하는 공정에서 금속배선 간에 에어-갭(air-gap)을 형성시켜 금속배선 간의 유전률을 감소시키고, 자기정렬콘택 방법에 의해 금속배선과 비아콘택 간의 중첩 여유도를 확보하는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to form an air-gap between metal wirings in a process of forming multilayer metal wirings, thereby reducing the dielectric constant between metal wirings and providing a self-aligned contact method. The present invention relates to a method for manufacturing a semiconductor device to secure the overlap margin between metal wiring and via contact.

일반적으로, 소자간이나 소자와 외부회로 사이를 전기적으로 접속시키기 위한 반도체소자의 배선은, 배선을 위한 소정의 콘택홀 및 비아콘택홀을 배선재료로 매립하여 배선층을 형성하고, 후속 공정을 거쳐 이루어지며 낮은 저항을 필요로 하는 곳에는 금속배선을 사용한다.In general, the wiring of a semiconductor device for electrically connecting between devices or between an element and an external circuit is formed by filling a predetermined contact hole and via contact hole for wiring with a wiring material to form a wiring layer, followed by a subsequent step. Metal wires are used where low resistance is required.

상기 금속배선은 알루미늄(Al)에 소량의 실리콘이나 구리가 포함되거나 실리콘과 구리가 모두 포함되어 비저항이 낮으면서 가공성이 우수한 알루미늄합금을 배선재료로 하여 물리기상증착(physical vapor deposition, 이하 PVD 라함)방법의 스퍼터링으로 상기의 콘택홀 및 비아콘택홀을 매립하는 방법으로 형성된다.The metal wiring includes a small amount of silicon or copper in aluminum (Al), or both silicon and copper, and has a low resistivity and has excellent workability and uses an aluminum alloy as a wiring material for physical vapor deposition (hereinafter referred to as PVD). It is formed by the method of filling the contact hole and the via contact hole by the sputtering method.

근래에는 반도체소자의 초고집적화에 따라 금속배선 콘택의 크기는 작아지고, 단차비는 높아져서 스퍼터링에 의한 금속배선의 층덮힘이 불량하게 되어 신뢰성을 얻기가 어려워졌다.In recent years, as the ultra-high integration of semiconductor devices increases, the size of the metal interconnection contact is reduced, and the step ratio is increased, resulting in poor layer coverage of the metal interconnection due to sputtering, making it difficult to obtain reliability.

이하, 첨부된 도면을 참고로 하여 종래기술에 대하여 살펴보기로 한다.Hereinafter, the prior art will be described with reference to the accompanying drawings.

도 1a 내지 도 1f 는 종래기술의 제1실시예에 따른 반도체소자의 제조방법을 도시한 단면도이다.1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the prior art.

먼저, 워드라인 및 비트라인 등의 하부구조물이 구비되어 있는 반도체기판(11) 상부에 제1층간절연막(12)을 형성한다. 상기 제1층간절연막(12)은 고밀도 플라즈마-화학기상증착(high density plasma-chemical vapor deposition, 이하 HDP-CVD)방법에 의한 SiO2, FSG(fluorinated silica glass) 또는 PSG(phospho silicate glass)를 사용하거나, SOG(spin on glass)계열의 FOX(flowable oxide)를 코팅한 후 어닐(anneal)처리한다.First, a first interlayer insulating film 12 is formed on the semiconductor substrate 11 having lower structures such as word lines and bit lines. The first interlayer dielectric layer 12 may be formed of SiO 2 , fluorinated silica glass (PSG), or phospho silicate glass (PSG) by high density plasma-chemical vapor deposition (HDP-CVD). Alternatively, an SOG (spin on glass) FOX (flowable oxide) is coated and then annealed.

그 다음, 상기 제1층간절연막(12) 상부에 제1접착층(13), 제1금속층(14) 및 제1반사방지막(15)을 순차적으로 형성한다. 이때, 상기 제1접착층(13)과 제1반사방지막(15)은 Ti/TiN막으로 형성되고, 상기 제1금속층(14)은 알루미늄층으로 형성된다.Next, a first adhesive layer 13, a first metal layer 14, and a first antireflection film 15 are sequentially formed on the first interlayer insulating film 12. In this case, the first adhesive layer 13 and the first antireflection film 15 are formed of a Ti / TiN film, and the first metal layer 14 is formed of an aluminum layer.

다음, 상기 제1반사방지막(15) 상부에 제1금속배선으로 예정되는 부분을 보호하는 제1감광막패턴(16)을 형성한다. (도 1a 참조)Next, a first photoresist layer pattern 16 is formed on the first anti-reflection layer 15 to protect a portion of the first anti-reflection layer 15. (See Figure 1A)

그 다음, 상기 제1감광막패턴(16)을 식각마스크로 상기 제1반사방지막(15), 제1금속층(14) 및 제1접착층(13)을 식각하여 제1반사방지막(15)패턴, 제1금속배선 및 제1접착층(13)패턴을 형성한다.Next, the first anti-reflection film 15, the first metal layer 14, and the first adhesive layer 13 are etched using the first photoresist pattern 16 as an etch mask, and the first anti-reflection film 15 pattern, The first metal wiring and the first adhesive layer 13 pattern are formed.

다음, 상기 제1감광막패턴(16)을 제거한다. (도 1b 참조)Next, the first photoresist pattern 16 is removed. (See FIG. 1B)

그 다음, 전체표면 상부에 평탄화절연막(17)을 형성하고, 화학적 기계적 연마(chemical mechanical polishing, 이하 CMP 라 함)공정으로 평탄화시킨다.Next, a planarization insulating film 17 is formed over the entire surface and planarized by a chemical mechanical polishing (hereinafter referred to as CMP) process.

다음, 상기 평탄화절연막(17) 상부에 제2층간절연막(18)을 형성한다. 이때, 상기 평탄화절연막(17)은 PE-CVD(plasma-enhanced chemical vapor deposition) 계열의 산화막을 사용하고, 상기 제2층간절연막(18)은 상기 제1층간절연막(12)과 같은 종류의 절연막을 사용한다. (도 1c 참조)Next, a second interlayer insulating film 18 is formed on the planarization insulating film 17. In this case, the planarization insulating layer 17 uses a plasma-enhanced chemical vapor deposition (PE-CVD) -based oxide layer, and the second interlayer insulating layer 18 is formed of an insulating film of the same type as the first interlayer insulating layer 12. use. (See Figure 1C)

그 다음, 상기 제2층간절연막(18) 상부에 비아콘택으로 예정되는 부분을 노출시키는 제2감광막패턴(19)을 형성한다. (도 1d 참조)Next, a second photoresist layer pattern 19 is formed on the second interlayer insulating layer 18 to expose a portion to be via contact. (See FIG. 1D)

다음, 상기 제2감광막패턴(19)을 식각마스크로 상기 제2층간절연막(18)과 평탄화절연막(17)을 식각하여 비아콘택홀(20)을 형성한다.Next, the via contact hole 20 is formed by etching the second interlayer insulating layer 18 and the planarization insulating layer 17 using the second photoresist pattern 19 as an etch mask.

그 다음, 상기 제2감광막패턴(19)을 제거한다. (도 1e 참조)Next, the second photoresist pattern 19 is removed. (See Figure 1E)

다음, 전체표면 상부에 텅스텐층을 형성한 후 CMP공정으로 상기 텅스텐층을 제거하여 상기 비아콘택홀(20)을 매립하는 비아콘택플러그(21)를 형성한다.Next, after the tungsten layer is formed on the entire surface, the tungsten layer is removed by the CMP process to form the via contact plug 21 filling the via contact hole 20.

그 다음, 전체표면 상부에 제2접착층, 제2금속층 및 제2반사방지막을 순차적으로 형성한다.Next, a second adhesive layer, a second metal layer and a second antireflection film are sequentially formed on the entire surface.

그 후, 제2금속배선 마스크를 식각마스크로 상기 제2반사방지막, 제2금속층 및 제2접착층을 식각하여 제2반사방지막패턴(24), 제2금속배선(23) 및 제2접착층패턴(22)을 형성한다. (도 1f 참조)Thereafter, the second antireflection film, the second metal layer, and the second adhesive layer are etched using the second metal wiring mask as an etch mask to form a second antireflection film pattern 24, a second metal wiring 23, and a second adhesive layer pattern ( 22). (See Figure 1f)

도 2 는 종래기술의 제1실시예에 따른 문제점을 도시한 단면도로서, 도 1d의 공정에서 미스얼라인먼트(misalignment)가 발생하는 경우 제1금속배선 상부의 제2층간절연막(18)과 평탄화절연막(17) 이외에도 ⓧ부분과 같이 상기 제1금속배선 측부의 평탄화절연막(17) 및 제1층간절연막(12)까지 제거되는 문제점이 있다. 또한, 상기 평탄화절연막(17)은 유전상수가 2.7 ∼ 4.2로 유전상수가 1인 에어-갭보다 커서 금속배선 간에 유전율을 증가시키는 문제점이 있다.FIG. 2 is a cross-sectional view illustrating a problem in accordance with a first embodiment of the prior art, in which a misalignment occurs in the process of FIG. 1D, and the second interlayer insulating film 18 and the planarization insulating film on the first metal wiring. In addition, the planarization insulating film 17 and the first interlayer insulating film 12 in the side portion of the first metal wiring side may be removed as shown in FIG. In addition, the planarization insulating layer 17 has a dielectric constant of 2.7 to 4.2, which is larger than the air-gap having a dielectric constant of 1, thereby increasing the dielectric constant between metal wirings.

도 3a 내지 도 3f 는 종래기술의 제2실시예에 따른 반도체소자의 제조방법을 도시하는 공정 단면도이다.3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the prior art.

먼저, 워드라인 및 비트라인 등의 하부구조물이 구비되어 있는 반도체기판(31) 상부에 제1평탄화절연막(32)을 형성한다.First, a first planarization insulating layer 32 is formed on the semiconductor substrate 31 having lower structures such as word lines and bit lines.

다음, 상기 제1평탄화절연막(32) 상부에 제1접착층(33), 제1금속층(34) 및 제1반사방지막(35)을 순차적으로 형성한다.Next, a first adhesive layer 33, a first metal layer 34, and a first antireflection film 35 are sequentially formed on the first planarization insulating layer 32.

그 다음, 상기 제1반사방지막(35) 상부에 제1금속배선으로 예정되는 부분을 보호하는 제1감광막패턴(36)을 형성한다. (도 3a 참조)Next, a first photoresist layer pattern 36 is formed on the first anti-reflective layer 35 to protect a portion of the first anti-reflective layer 35. (See Figure 3A)

다음, 상기 제1감광막패턴(36)을 식각마스크로 상기 제1반사방지막(35), 제1금속층(34) 및 제1접착층(33)을 식각하여 제1반사방지막(35)패턴, 제1금속배선 및 제1접착층(33)패턴을 형성한다.Next, the first anti-reflection film 35, the first metal layer 34, and the first adhesive layer 33 are etched using the first photoresist pattern 36 as an etch mask, and the first anti-reflection film 35 pattern and the first The metal wiring and the first adhesive layer 33 pattern are formed.

그 다음, 상기 제1감광막패턴(36)을 제거한다. (도 3b 참조)Next, the first photoresist pattern 36 is removed. (See Figure 3b)

다음, 전체표면 상부에 층간절연막(38)을 형성한다. 이때, 상기 층간절연막(38)은 매립특성이 열악하여 제1금속배선 간에 에어-갭(37)을 형성한다.Next, an interlayer insulating film 38 is formed over the entire surface. At this time, the interlayer insulating film 38 has poor buried characteristics to form an air gap 37 between the first metal wires.

그 다음, 전체표면 상부에 제2평탄화절연막(39)을 형성한다. (도 3c 참조)Next, a second planarization insulating film 39 is formed over the entire surface. (See Figure 3c)

다음, 상기 제2평탄화절연막(39) 상부에 비아콘택으로 예정되는 부분을 노출시키는 제2감광막패턴(40)을 형성한다. (도 3d 참조)Next, a second photoresist layer pattern 40 is formed on the second planarization insulating layer 39 to expose a portion of the via contact. (See FIG. 3D)

그 다음, 상기 제2감광막패턴(40)을 식각마스크로 상기 제2평탄화절연막(39)과 층간절연막(38)을 식각하여 비아콘택홀(41)을 형성한다.Next, the via contact hole 41 is formed by etching the second planarization insulating layer 39 and the interlayer insulating layer 38 using the second photoresist pattern 40 as an etch mask.

다음, 상기 제2감광막패턴(40)을 제거한다. (도 3e 참조)Next, the second photoresist pattern 40 is removed. (See Figure 3E)

다음, 전체표면 상부에 텅스텐층을 형성한 후 CMP공정으로 상기 텅스텐층을 제거하여 상기 비아콘택홀(41)을 매립하는 비아콘택플러그(42)를 형성한다.Next, after forming the tungsten layer on the entire surface, the tungsten layer is removed by a CMP process to form a via contact plug 42 filling the via contact hole 41.

그 다음, 전체표면 상부에 제2접착층, 제2금속층 및 제2반사방지막을 순차적으로 형성한다.Next, a second adhesive layer, a second metal layer and a second antireflection film are sequentially formed on the entire surface.

그 후, 제2금속배선 마스크를 식각마스크로 상기 제2반사방지막, 제2금속층 및 제2접착층을 식각하여 제2반사방지막패턴(45), 제2금속배선(44) 및 제2접착층패턴(43)을 형성한다. (도 3f 참조)Thereafter, the second anti-reflection film, the second metal layer, and the second adhesive layer are etched using the second metal wiring mask as an etch mask to etch the second anti-reflection film pattern 45, the second metal wiring 44, and the second adhesive layer pattern ( 43). (See Figure 3f)

도 4 는 종래기술의 제2실시예에 따른 문제점을 도시한 단면도로서, 도 3d 의 공정에서 미스얼라인먼트가 발생한 경우 ⓨ부분과 같이 에어-갭(37)을 노출시키는 동시에 층간절연막(38) 및 제1평탄화절연막(32)까지 제거되서 비아콘택플러그(42) 형성 후 소자 간에 브리지(bridge)를 유발시키는 문제점이 발생하게 된다. 또한, 평탄화절연막과 비아콘택플러그 형성 시 CMP공정을 각각 실시해야 하므로 공정이 복잡하고, 비용이 증가한다. 그리고, 금속배선 간에 에어-갭(37)을 형성하여 유전율을 줄일 수 있지만, 반사방지막에 의해 층간 유전 상수가 증가하여 RC 지연을 유발하는 문제점이 있다.FIG. 4 is a cross-sectional view showing a problem according to a second embodiment of the prior art, in the case of a misalignment occurring in the process of FIG. 3d, exposing the air-gap 37 as in FIG. Since even the first planarization insulating layer 32 is removed, a problem occurs that causes a bridge between devices after the via contact plug 42 is formed. In addition, since the CMP process must be performed when forming the planarization insulating film and the via contact plug, the process is complicated and the cost increases. In addition, although the dielectric constant can be reduced by forming the air gaps 37 between the metal lines, there is a problem that the interlayer dielectric constant is increased by the anti-reflection film to cause the RC delay.

본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 반도체기판 상부에 평탄화절연막을 형성하고, 접착층, 금속층 및 제1층간절연막을 형성하고, 비아콘택플러그를 형성한 다음, 제1금속배선을 형성한 후 제2층간절연막을 형성하여 상기 제1금속배선 간에 에어-갭을 형성한 후 제2금속배선을 형성함으로써 금속배선 간에 유전율을 감소시키고, 미스얼라인먼트 발생 시에도 하부절연막이 불필요하게 식각되는 것을 방지하여 그에 따른 소자의 동작 특성 및 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, the planarization insulating film is formed on the semiconductor substrate, the adhesive layer, the metal layer and the first interlayer insulating film are formed, the via contact plug is formed, and then the first metal wiring is formed. After forming a second interlayer insulating film to form an air gap between the first metal wirings, and then forming a second metal wiring, the dielectric constant is reduced between the metal wirings, and the lower insulating film is unnecessarily etched even when misalignment occurs. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can prevent and thereby improve the operation characteristics and reliability of the device.

도 1a 내지 도 1f 는 종래기술의 제1실시예에 따른 반도체소자의 제조방법을 도시하는 공정 단면도.1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the prior art.

도 2 는 종래기술의 제1실시예에 따른 문제점을 도시한 단면도.2 is a cross-sectional view showing a problem according to the first embodiment of the prior art;

도 3a 내지 도 3f 는 종래기술의 제2실시예에 따른 반도체소자의 제조방법을 도시하는 공정 단면도.3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the prior art.

도 4 는 종래기술의 제2실시예에 따른 문제점을 도시한 단면도.4 is a sectional view showing a problem according to a second embodiment of the prior art;

도 5a 내지 도 5f 는 본 발명에 따른 반도체소자의 제조방법을 도시하는 공정 단면도.5A to 5F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

< 도면의 주요부분에 대한 부호 설명 ><Explanation of Signs of Major Parts of Drawings>

11, 31, 51 : 반도체기판 12, 55 : 제1층간절연막11, 31, 51: semiconductor substrate 12, 55: first interlayer insulating film

13, 33, 53 : 제1접착층 14, 34, 54 : 제1금속층13, 33, 53: first adhesive layer 14, 34, 54: first metal layer

15, 35 : 제1반사방지막 16, 36, 56 : 제1감광막패턴15, 35: first antireflection film 16, 36, 56: first photosensitive film pattern

17 : 평탄화절연막 18, 60 : 제2층간절연막17: planarization insulating film 18, 60: second interlayer insulating film

19, 40, 58 : 제2감광막패턴 20, 41 : 비아콘택홀19, 40, 58: second photoresist pattern 20, 41: via contact hole

21, 42, 57 : 비아 콘택 플러그 22, 43, 62 : 제2접착층패턴21, 42, 57: via contact plug 22, 43, 62: second adhesive layer pattern

23, 44, 63 : 제2금속배선 24, 45 : 제2반사방지막패턴23, 44, 63: second metal wiring 24, 45: second antireflection film pattern

32, 52 : 제1평탄화절연막 37, 59 : 에어-갭32, 52: first planarization insulating film 37, 59: air-gap

38 : 층간절연막 39, 61 : 제2평탄화절연막38: interlayer insulating film 39, 61: second planarization insulating film

64 : 반사방지막패턴64: antireflection film pattern

이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 제조방법은,In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention,

소정의 하부구조물이 구비되는 반도체기판 상부에 제1평탄화절연막을 형성하는 공정과,Forming a first planarization insulating film on the semiconductor substrate provided with a predetermined lower structure;

상기 제1평탄화절연막 상부에 제1접착층, 제1금속층 및 제1층간절연막을 형성하는 공정과,Forming a first adhesive layer, a first metal layer, and a first interlayer insulating film on the first planarization insulating film;

비아콘택마스크를 식각마스크로 상기 제1층간절연막을 식각하여 비아콘택홀을 형성하는 공정과,Forming a via contact hole by etching the first interlayer insulating layer using a via contact mask as an etch mask;

상기 비아콘택홀을 매립하는 비아콘택플러그를 형성하는 공정과,Forming a via contact plug to fill the via contact hole;

상기 제1층간절연막을 소정 두께 전면식각하여 상기 비아콘택플러그를 노출시키는 공정과,Exposing the via contact plug by etching the entire surface of the first interlayer insulating layer by a predetermined thickness;

제1금속배선 마스크를 식각마스크로 상기 제1층간절연막을 식각하여 제1층간절연막패턴을 형성하고, 상기 제1층간절연막패턴을 식각마스크로 상기 제1금속층 및 제1접착층을 식각하여 제1금속배선 및 제1접착층패턴을 형성하는 공정과,The first interlayer dielectric layer is etched using the first metal wiring mask as an etch mask to form a first interlayer dielectric layer pattern, and the first metal layer and the first adhesive layer are etched using the first interlayer dielectric layer pattern as an etch mask. Forming a wiring and a first adhesive layer pattern;

전체표면 상부에 제2층간절연막을 형성하여 상기 제1금속배선 간에 에어-갭을 형성하는 공정과,Forming an air gap between the first metal wires by forming a second interlayer insulating film over the entire surface;

전체표면 상부에 제2평탄화절연막을 형성한 후 화학적 기계적 연마공정을 실시하여 상기 비아콘택플러그를 노출시키는 공정을 포함하는 것을 특징으로 한다.And forming a second planarization insulating layer on the entire surface, and then performing a chemical mechanical polishing process to expose the via contact plug.

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 5a 내지 도 5f 는 본 발명에 따른 반도체소자의 제조방법을 도시하는 공정 단면도이다.5A to 5F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

먼저, 반도체기판(51) 상부에 제1평탄화절연막(52)을 형성한다.First, a first planarization insulating film 52 is formed on the semiconductor substrate 51.

다음, 상기 제1평탄화절연막(52) 상부에 제1접착층(53), 제1금속층(54) 및 제1층간절연막(55)을 순차적으로 형성한다. 이때, 상기 제1접착층(53)은 Ti/TiN막으로형성하고, 상기 제1금속층(54)은 알루미늄층으로 형성하며, 상기 제1층간절연막(55)은 PE-CVD계열의 산화막을 12000 ∼ 14000Å 두께로 형성한다. 한편, 종래기술과는 달리 상기 제1금속층(54) 상부에 반사방지막을 형성하지 않는다. 이는 후속 제1금속배선 형성 시 상기 제1층간절연막(55)이 식각마스크로 사용되기 때문이다.Next, a first adhesive layer 53, a first metal layer 54, and a first interlayer insulating layer 55 are sequentially formed on the first planarization insulating layer 52. In this case, the first adhesive layer 53 is formed of a Ti / TiN film, the first metal layer 54 is formed of an aluminum layer, and the first interlayer insulating layer 55 is formed of an oxide film of PE-CVD series. It is formed to a thickness of 14000Å. On the other hand, unlike the prior art, an anti-reflection film is not formed on the first metal layer 54. This is because the first interlayer insulating layer 55 is used as an etching mask in the subsequent formation of the first metal wiring.

그 다음, 상기 제1층간절연막(55) 상부에 비아콘택으로 예정되는 부분을 노출시키는 제1감광막패턴(56)을 형성한다. (도 5a 참조)Next, a first photoresist pattern 56 is formed on the first interlayer insulating layer 55 to expose a portion that is intended to be a via contact. (See Figure 5A)

다음, 상기 제1감광막패턴(56)을 식각마스크로 상기 제1층간절연막(55)을 소정 두께 식각하여 비아콘택홀(도시안됨)을 형성한다.Next, the first interlayer insulating layer 55 is etched by a predetermined thickness using the first photoresist layer pattern 56 to form a via contact hole (not shown).

그 다음, 상기 제1감광막패턴(56)을 제거한다.Next, the first photoresist pattern 56 is removed.

다음, 전체표면 상부에 텅스텐층을 형성한다.Next, a tungsten layer is formed on the entire surface.

그 다음, SF6와 Ar 가스를 활성화시킨 플라즈마를 이용하여 상기 텅스텐층을 전면식각하여 상기 비아콘택홀을 매립하는 비아콘택플러그(57)를 형성한다.Subsequently, the tungsten layer is etched entirely using plasma activated with SF 6 and Ar gas to form a via contact plug 57 filling the via contact hole.

다음, CxFy, CHFz및 Ar 가스를 활성화시킨 플라즈마를 이용하여 상기 제1층간절연막(55)의 8000 ∼ 10000Å 두께를 전면식각하여 상기 비아콘택플러그(57)를 노출시킨다. (도 5b 참조)Next, the via contact plug 57 is exposed by etching the entire surface of the first interlayer insulating layer 55 8000 to 10000 Å thick using plasma activated with C x F y , CHF z and Ar gases. (See Figure 5b)

그 다음, 상기 구조 상부에 제1금속배선으로 예정되는 부분을 보호하는 제2감광막패턴(58)을 형성한다. 이때, 상기 비아콘택플러그(57)와 제1금속배선 간에 미스얼라인먼트가 발생하는 경우, 자기정렬(self align)에 의해 하부층이 손상되지 않는다. (도 5c 참조)Next, a second photoresist pattern 58 is formed on the structure to protect a portion intended as the first metal wiring. At this time, if a misalignment occurs between the via contact plug 57 and the first metal wiring, the lower layer is not damaged by self alignment. (See Figure 5c)

다음, 상기 제2감광막패턴(58)을 식각마스크로 상기 제1층간절연막(55), 제1금속층(54) 및 제1접착층(53)을 식각하여 제1금속배선과 제1접착층패턴을 형성한다. 이때, 상기 제1층간절연막(55)은 CxFy, CHFz및 Ar 가스를 활성화시킨 플라즈마로 식각하여 제1층간절연막패턴을 형성한 다음, 상기 제1층간절연막패턴을 식각마스크로 상기 제1금속층(54)과 제1접착층(53)을 Cl2, BCl2및 N2를 활성화시킨 플라즈마를 이용하여 상기 비아콘택플러그(57)에 선택적으로 식각한다.Next, the first interlayer insulating layer 55, the first metal layer 54, and the first adhesive layer 53 are etched using the second photoresist pattern 58 as an etch mask to form a first metal wiring and a first adhesive layer pattern. do. In this case, the first interlayer dielectric layer 55 is etched with plasma activated C x F y , CHF z and Ar gas to form a first interlayer dielectric layer pattern, and then the first interlayer dielectric layer pattern is etched using the etching mask. The first metal layer 54 and the first adhesive layer 53 are selectively etched into the via contact plug 57 by using a plasma in which Cl 2 , BCl 2 and N 2 are activated.

그 다음, 상기 제2감광막패턴(58)을 제거한다. (도 5d 참조)Next, the second photoresist pattern 58 is removed. (See FIG. 5D)

다음, 전체표면 상부에 PE-CVD계열의 산화막으로 제2층간절연막(60)을 형성하여 제1금속배선 간에 에어-갭(59)을 형성한다. 이때, 상기 에어-갭(59)은 상기 제1층간절연막(55)에 의해 높이를 증가시킬 수 있다.Next, the second interlayer insulating film 60 is formed of an oxide film of PE-CVD series on the entire surface to form an air-gap 59 between the first metal wirings. In this case, the air gap 59 may increase in height by the first interlayer insulating layer 55.

그 다음, 전체표면 상부에 제2평탄화절연막(61)을 형성한 후 상기 제2평탄화절연막(61)을 CMP공정으로 제거하여 상기 비아콘택플러그(57)를 노출시킨다. 상기 제2평탄화절연막(61)은 HDP-CVD에 의한 SiO2, FSG 또는 PSG를 사용하거나, SOG계열의 FOX(Flowable oxide)를 코팅한 후 어닐(anneal)처리한다. (도 5e 참조)Next, the second planarization insulating layer 61 is formed on the entire surface, and the second planarization insulating layer 61 is removed by a CMP process to expose the via contact plugs 57. The second planarization insulating layer 61 may be annealed by using SiO 2 , FSG, or PSG by HDP-CVD, or coating SOG-based FOX (Flowable oxide). (See Figure 5E)

다음, 전체표면 상부에 제2접착층, 제2금속층 및 반사방지막을 순차적으로 형성한다.Next, a second adhesive layer, a second metal layer and an antireflection film are sequentially formed on the entire surface.

그 후, 제2금속배선 마스크를 식각마스크로 상기 반사방지막, 제2금속층 및 제2접착층을 식각하여 반사방지막패턴(64), 제2금속배선(63) 및 제2접착층패턴(62)을 형성한다. (도 5f 참조)Thereafter, the anti-reflection film, the second metal layer and the second adhesive layer are etched using the second metal wiring mask as an etch mask to form the anti-reflection film pattern 64, the second metal wiring 63, and the second adhesive layer pattern 62. do. (See Figure 5f)

이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 제조방법은, 반도체기판 상부에 제1평탄화절연막을 형성하고, 상기 제1평탄화절연막 상부에 접착층, 금속층 및 제1층간절연막을 형성한 다음, 비아콘택 마스크를 식각마스크로 상기 제1층간절연막을 식각하여 비아콘택홀을 형성한 후 상기 비아콘택홀을 매립하는 비아콘택플러그를 형성하고, 상기 제1층간절연막을 소정 두께 전면식각하여 상기 비아콘택플러그를 노출시킨 다음, 제1금속배선 마스크를 식각마스크로 이용하여 상기 제1층간절연막, 금속층 및 접착층을 식각하여 제1금속배선을 형성한 후, 전체표면상부에 제2층간절연막을 형성하여 에어-갭(air-gap)을 형성하고, 상기 제2층간절연막 상부에 제2평탄화절연막을 형성한 다음, 상기 제2평탄화절연막을 화학적 기계적 연마(chemical mechanical polishing)방법으로 제거하여 상기 비아콘택플러그를 노출시킨 후 상기 비아콘택플러그에 접속되는 제2금속배선을 형성함으로써 제1금속배선 형성 시 미스얼라인먼트(misalignment)가 발생해도 제1평탄화절연막이 손실되는 것을 방지할 수 있고, 비아콘택플러그를 전면식각공정에 의해 형성하여 비용을 줄일 수 있으며, 금속배선 및 층간에 유전율을 감소시켜 소자의 동작 특성 및 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, a first planarization insulating film is formed on a semiconductor substrate, an adhesive layer, a metal layer, and a first interlayer insulating film are formed on the first flattening insulating film, and then via contact is made. The via contact plug is formed by etching the first interlayer insulating layer using an mask as an etch mask, and then forming a via contact plug to fill the via contact hole, and etching the entire surface of the first interlayer insulating layer by a predetermined thickness. After exposure, the first interlayer insulating layer, the metal layer, and the adhesive layer are etched using the first metal wiring mask as an etching mask to form a first metal wiring, and then a second interlayer insulating layer is formed on the entire surface to form an air gap. an air-gap, a second planarization insulating layer formed on the second interlayer insulating layer, and then chemical mechanical polishing of the second planarization insulating layer. l The first planarization insulating film is lost even when misalignment occurs when the first metal wiring is formed by forming a second metal wiring connected to the via contact plug by exposing the via contact plug by removing the method by polishing. It can be prevented, the via contact plug can be formed by the front etching process to reduce the cost, there is an advantage that can improve the operating characteristics and reliability of the device by reducing the dielectric constant between the metal wiring and interlayer.

Claims (6)

소정의 하부구조물이 구비되는 반도체기판 상부에 제1평탄화절연막을 형성하는 공정과,Forming a first planarization insulating film on the semiconductor substrate provided with a predetermined lower structure; 상기 제1평탄화절연막 상부에 제1접착층, 제1금속층 및 제1층간절연막을 형성하는 공정과,Forming a first adhesive layer, a first metal layer, and a first interlayer insulating film on the first planarization insulating film; 비아콘택마스크를 식각마스크로 상기 제1층간절연막을 식각하여 비아콘택홀을 형성하는 공정과,Forming a via contact hole by etching the first interlayer insulating layer using a via contact mask as an etch mask; 상기 비아콘택홀을 매립하는 비아콘택플러그를 형성하는 공정과,Forming a via contact plug to fill the via contact hole; 상기 제1층간절연막을 소정 두께 전면식각하여 상기 비아콘택플러그를 노출시키는 공정과,Exposing the via contact plug by etching the entire surface of the first interlayer insulating layer by a predetermined thickness; 제1금속배선 마스크를 식각마스크로 상기 제1층간절연막을 식각하여 제1층간절연막패턴을 형성하고, 상기 제1층간절연막패턴을 식각마스크로 상기 제1금속층 및 제1접착층을 식각하여 제1금속배선 및 제1접착층패턴을 형성하는 공정과,The first interlayer dielectric layer is etched using the first metal wiring mask as an etch mask to form a first interlayer dielectric layer pattern, and the first metal layer and the first adhesive layer are etched using the first interlayer dielectric layer pattern as an etch mask. Forming a wiring and a first adhesive layer pattern; 전체표면 상부에 제2층간절연막을 형성하여 상기 제1금속배선 간에 에어-갭을 형성하는 공정과,Forming an air gap between the first metal wires by forming a second interlayer insulating film over the entire surface; 전체표면 상부에 제2평탄화절연막을 형성한 후 화학적 기계적 연마공정을 실시하여 상기 비아콘택플러그를 노출시키는 공정을 포함하는 반도체소자의 제조방법.And forming a second planarization insulating layer over the entire surface, and then performing a chemical mechanical polishing process to expose the via contact plug. 제 1 항에 있어서,The method of claim 1, 상기 제1층간절연막과 제2층간절연막은 PE-CVD계열의 산화막인 것을 특징으로 하는 반도체소자의 제조방법.And said first interlayer insulating film and said second interlayer insulating film are oxide films of PE-CVD series. 제 1 항에 있어서,The method of claim 1, 상기 제1평탄화절연막과 제2평탄화절연막은 HDP-CVD 계열의 SiO2, FSG 또는 PSG을 사용하거나, FOX(Flowable oxide)를 형성한 후 어닐링하여 사용하는 것을 특징으로 하는 반도체소자의 제조방법.The first planarization insulating film and the second planarization insulating film are manufactured using an HDP-CVD-based SiO 2 , FSG, or PSG, or after forming an oxide of FOX (Flowable oxide) is used for manufacturing a semiconductor device. 제 1 항에 있어서,The method of claim 1, 상기 제1층간절연막은 12000 ∼ 14000Å 두께로 형성되는 것을 특징으로 하는 반도체소자의 제조방법.The first interlayer dielectric film is formed to a thickness of 12000 ~ 14000 Å. 제 1 항에 있어서,The method of claim 1, 상기 제1층간절연막은 8000 ∼ 10000Å 두께 전면식각하는 것을 특징으로 하는 반도체소자의 제조방법.And the first interlayer dielectric film is etched from 8000 to 10000 Å in thickness. 제 1 항에 있어서,The method of claim 1, 상기 제1금속층과 제1접착층은 Cl2, BCl2및 N2가스를 활성화시킨 플라즈마를 이용하여 식각하는 것을 특징으로 하는 반도체소자의 제조방법.The first metal layer and the first adhesive layer is a semiconductor device manufacturing method, characterized in that the etching using a plasma activated by the Cl 2 , BCl 2 and N 2 gas.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100713715B1 (en) * 2006-08-23 2007-05-02 임관빈 A cutting machine sandwich panel
US7361452B2 (en) 2003-02-04 2008-04-22 Dongbu Electronics Co., Ltd. Methods for forming a metal line in a semiconductor manufacturing process
KR100829603B1 (en) 2006-11-23 2008-05-14 삼성전자주식회사 Method of manufacturing a semiconductor device having an air-gap

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7361452B2 (en) 2003-02-04 2008-04-22 Dongbu Electronics Co., Ltd. Methods for forming a metal line in a semiconductor manufacturing process
KR100713715B1 (en) * 2006-08-23 2007-05-02 임관빈 A cutting machine sandwich panel
KR100829603B1 (en) 2006-11-23 2008-05-14 삼성전자주식회사 Method of manufacturing a semiconductor device having an air-gap

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