KR100378343B1 - Backside recess electrode type solar cell - Google Patents
Backside recess electrode type solar cell Download PDFInfo
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- KR100378343B1 KR100378343B1 KR1019960000303A KR19960000303A KR100378343B1 KR 100378343 B1 KR100378343 B1 KR 100378343B1 KR 1019960000303 A KR1019960000303 A KR 1019960000303A KR 19960000303 A KR19960000303 A KR 19960000303A KR 100378343 B1 KR100378343 B1 KR 100378343B1
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- 239000000758 substrate Substances 0.000 claims abstract description 40
- 239000004065 semiconductor Substances 0.000 claims abstract description 39
- 229910052751 metal Inorganic materials 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 8
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910052763 palladium Inorganic materials 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 239000000969 carrier Substances 0.000 abstract description 4
- 230000005684 electric field Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 10
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 3
- 229910052725 zinc Inorganic materials 0.000 description 3
- 239000011701 zinc Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 235000008331 Pinus X rigitaeda Nutrition 0.000 description 1
- 235000011613 Pinus brutia Nutrition 0.000 description 1
- 241000018646 Pinus brutia Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
Description
본 발명은 후면 함몰전극형 태양전지에 관한 것으로서, 보다 상세하기로는 반도체 기판 후면에만 전극을 형성하는 후면전극형 태양전지에 있어서, 전극을 반도체 기판 후면내로 깊게 파여진 홈에 형성함으로써 캐리아의 수집확률을 높임과 동시에 효과적인 후면전계를 형성시킬 수 있는 후면 함몰전극형 태양전지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a back recessed electrode type solar cell, and more particularly, to a back electrode type solar cell in which electrodes are formed only on a back side of a semiconductor substrate, wherein the electrodes are collected in a groove deeply dug into the back side of the semiconductor substrate. The present invention relates to a back recessed electrode type solar cell capable of increasing the probability and forming an effective backside field.
태양전지의 효율에 영향을 미치는 중요한 요소에는 단락회로 전류밀도, 개방회로전압, 충실도 등이 있다.Important factors affecting the efficiency of solar cells include short circuit current density, open circuit voltage, and fidelity.
태양전지의 변환효율을 향상시키기 위해서는 일반적으로 개방회로전압(VOC)을 높여야 한다. VOC는 하기식 (1)로 나타낼 수 있다.In order to improve the conversion efficiency of solar cells, open circuit voltage (V OC ) should generally be increased. V OC can be represented by the following formula (1).
여기에서 n은 전자의 농도, k는 볼츠만 상수(=1.38×10-23joule/K), T는 절대온도(K), q는 전하량(=1.602×10-19coulomb), JSC단락회로 전류밀도, JO는 다크(dark) 포화전류밀도이다.Where n is the electron concentration, k is the Boltzmann constant (= 1.38 × 10 -23 joule / K), T is the absolute temperature (K), q is the charge (= 1.602 × 10 -19 coulomb), and J SC short-circuit current Density, J O is the dark saturation current density.
상기식 (1)에서 알 수 있는 바와 같이, 태양전지에서의 중요한 요소인 개방회로전압(VOC)을 높이기 위해서는 JO를 줄여야 하며, JO는 하기식 (2)로 나타낼 수 있다.As can be seen in Equation (1), in order to increase the open circuit voltage (V OC ) which is an important factor in the solar cell, J O must be reduced, and J O can be represented by the following equation (2).
여기서, Jofs는 전면전류, Jobs는 후면전류, Joe는 에미터(emitter)전류, Job는 기저전류, Jofg는 전면홈전류이다.Here, J ofs is the front current, J obs is the rear current, J oe is the emitter (emitter) current, J ob is the base current, J ofg is the front groove current.
그런데 Jobs가 JO에서 가장 큰 비중을 차지하므로 JO를 줄이기 위해서는 Jobs값을 감소시켜야만 한다.However, because the J obs accounted for the largest share in J O J O and to reduce the sikyeoyaman reduce J obs value.
태양전지의 다른 중요한 요소인 충실도(fill factor, 이하 FF)는 하기식 (3)으로 표현된다.Fidelity (fill factor, FF), another important factor of solar cells, is represented by the following equation (3).
여기서, VOC= VOC/(kT/q)로 25℃에서 kT/q=0.026mV이며 증가된 VOC는 충실도를 향상시킨다. 향상된 VOC와 FF는 전체변환효율()을 향상시킨다.Here, V OC = V OC / (kT / q), kT / q = 0.026mV at 25 ° C. and increased V OC improves fidelity. Improved V OC and FF are the Improve).
여기서, Pin는 입사된 빛에너지의 양이다.Where P in is the amount of incident light energy.
상기식 (4)에서 알 수 있는 바와 같이 VOC와 FF가 증가하면는 증가한다.As can be seen from Equation (4), when V OC and FF increase Increases.
상기 단락회로 전류밀도에 영향을 미치는 요인으로는 반도체 기판 표면에서의 입사광의 반사율, 전지에서의 내부 양자 효율 등이 있다. 단락회로 전류밀도를 증가시키기 위해서는 반도체 기판 표면에서의 입사광의 반사율을 감소시켜야 하는데, 이를 위한 노력으로서 반도체 기판 표면을 텍스처링하거나 전극의 표면적을 줄이고자 많은 연구가 진행되어 왔다.Factors affecting the short circuit current density include reflectance of incident light on the surface of the semiconductor substrate, internal quantum efficiency in the battery, and the like. In order to increase the short-circuit current density, it is necessary to reduce the reflectance of incident light on the surface of the semiconductor substrate. As an effort for this, much research has been conducted to texturize the surface of the semiconductor substrate or reduce the surface area of the electrode.
반도체 기판 표면을 텍스처링하는 방법은 기판 표면에서의 입사광의 반사를 감소시킬 뿐만 아니라 스넬법칙에 따라 입사광이 반도체 기판 내부로 들어가는 부수적인 효과를 얻을 수 있는 방법이다.The method of texturing the surface of a semiconductor substrate is a method that not only reduces the reflection of incident light on the surface of the substrate but also obtains an incidental effect of entering incident light into the semiconductor substrate according to Snell's law.
전극의 표면적을 줄이기 위한 방법으로서 기존의 스크린 프린팅형 전극대신 함몰전극형 전극을 사용하는 방법이 있다. 전극을 반도체 기판 내부로 깊게 파인 홈에 형성함으로써 전극에서의 반사로 인한 입사광의 손실을 줄일 수 있었다. 그러나 이러한 함몰전극이 반도체 기판의 전면에 형성되므로 이 전면전극에 의한 입사광의 반사율이 2∼3％정도나 된다.As a method for reducing the surface area of an electrode, there is a method of using a recessed electrode type electrode instead of a conventional screen printing electrode. The loss of incident light due to reflection at the electrode can be reduced by forming the electrode in the groove deeply dug into the semiconductor substrate. However, since the recessed electrode is formed on the entire surface of the semiconductor substrate, the reflectance of the incident light by the front electrode is about 2 to 3%.
이러한 문제점을 해결하기 위하여 전극을 모두 반도체 기판 후면에 형성하는 후면전극형 태양전지가 개발되었으며, 이러한 전지의 예가 제1도에 도시되어 있다.In order to solve this problem, a back-electrode type solar cell in which all electrodes are formed on a back surface of a semiconductor substrate has been developed, and an example of such a battery is shown in FIG. 1.
제1A도는 p형 반도체 기판 (1) 후면 전체에 후면전극 (4)가 형성되어 있는 텍스처링된 블랙 태양전지를 나타낸 도면이고, 제1B도는 반도체 기판 (1) 후면에 p+부스바아 (6)과 n+부스바아 (7)이 형성되어 있는 포인트 콘택트 태양전지를 도시한 도면이다. 제1B도에서 화살표는 입사광의 방향을 나타내며, (2)는 n+층, (3)은 p+층, (5)는 산화막을 나타낸다.FIG. 1A shows a textured black solar cell having the back electrode 4 formed on the entire back surface of the p-type semiconductor substrate 1, and FIG. 1B shows p + busbars 6 and the back surface of the semiconductor substrate 1; It is a figure which shows the point contact solar cell in which n + busbar 7 is formed. In Fig. 1B, the arrow indicates the direction of incident light, (2) indicates an n + layer, (3) indicates a p + layer, and (5) indicates an oxide film.
그러나, 상기 후면전극형 태양전지는 반도체 기판 후면에 전극을 형성함으로써 전극에서의 반사로 인한 입사광의 손실을 줄일 수는 있었지만, 다음과 같은 문제점을 가지고 있다.However, the back electrode type solar cell has been able to reduce the loss of incident light due to reflection from the electrode by forming an electrode on the back of the semiconductor substrate, but has the following problems.
첫째, 반도체 기판 후면에 전극을 형성하기 위해서는 고가의 진공증착설비가필요할 뿐만 아니라, 여러단계의 사진식각공정을 거쳐야 한다. 사진식각공정은 복잡하며 생산성이 낮은 공정이기 때문에 전지 제조원가를 상승시키는 문제가 있다.First, in order to form the electrode on the back of the semiconductor substrate, not only an expensive vacuum deposition apparatus is required, but also a plurality of photolithography processes are required. Since the photolithography process is complicated and has low productivity, there is a problem of increasing battery manufacturing costs.
둘째, 전극이 반도체 기판 후면에 형성되어 있어서 캐리아들의 이동거리가 길어지게 되므로 캐리아들의 수집확률이 낮아진다. 특히 금속을 반도체 기판 후면 전체에 증착시켜 전극을 형성하는 경우, 금속과 반도체 기판과의 접촉면적이 증가하여 캐리아들의 수명이 감소되므로 전지의 개방전압 및 단락회로 전류밀도가 감소되는 문제점을 가지고 있다.Second, since the electrodes are formed on the rear surface of the semiconductor substrate, the moving distance of the carriers is increased, so that the collection probability of the carriers is lowered. In particular, when the electrode is formed by depositing metal on the entire back surface of the semiconductor substrate, the contact area between the metal and the semiconductor substrate is increased, and thus the life of the carriers is reduced, thereby reducing the open voltage and short circuit current density of the battery. .
그러므로 본 발명의 목적은 상기 문제점을 해결하여 반도체 기판 후면내로 깊게 파여진 홈에 전극을 형성함으로써 캐리아의 수집확률을 높임과 동시에, 효과적인 후면전계를 형성시킬 수 있는 후면 함몰전극형 태양전지를 제공하는 것이다.Therefore, an object of the present invention is to solve the above problems by providing an electrode in the groove deeply dug into the back of the semiconductor substrate to increase the probability of collecting the carrier, and at the same time to provide a back-side electrode electrode solar cell that can form an effective rear field. It is.
상기 목적을 달성하기 위하여 본 발명에서는 피라미드 구조가 형성되어 있는 반도체 기판 전면에는 산화막이 형성되어 있고, 평탄화된 구조를 갖는 반도체 기판 후면내의 하나이상의 홈에 p+층과 n+층이 교대로 형성되어 있고, 상기 p+층과 n+층 상부에 전도성 금속으로 이루어진 후면전극이 형성되어 있는 것을 특징으로 하는 후면 함몰전극형 태양전지가 제공된다.In order to achieve the above object, in the present invention, an oxide film is formed on the front surface of the semiconductor substrate on which the pyramid structure is formed, and p + and n + layers are alternately formed in one or more grooves in the back surface of the semiconductor substrate having the planarized structure. In addition, a back recessed electrode solar cell is provided, wherein a back electrode made of a conductive metal is formed on the p + layer and the n + layer.
본 발명에서는 상기 반도체 기판 전면의 산화막 하부에 n+층을 더 형성시킴으로써 전면전계를 형성할 수 있다.In the present invention, the front electric field may be formed by further forming an n + layer under the oxide film on the entire surface of the semiconductor substrate.
상기 전극은 니켈, 아연, 구리, 티타늄, 팔라듐 및 은중에 선택된 적어도 하나의 물질을 이용하여 선택적 도금이 가능한 무전해 도금방법 또는 전기 도금방법으로 형성시킨다. 그 중에서도 특히 니켈/아연, 니켈/구리/아연 또는 티타늄/팔라듐/은을 순차적으로 형성함으로써 전극을 제조하는 것이 바람직하다.The electrode is formed by an electroless plating method or an electroplating method capable of selective plating using at least one material selected from nickel, zinc, copper, titanium, palladium and silver. Especially, it is preferable to manufacture an electrode by forming nickel / zinc, nickel / copper / zinc, or titanium / palladium / silver sequentially.
상기 반도체 기판의 홈은 레이저, 다이아몬드 펜을 이용하여 형성시키거나 화학적 에칭방법, 건식 에칭방법을 이용하여 형성시킨다. 이 때 홈의 깊이는 5∼100μm, 폭이 5∼40μm이다.The groove of the semiconductor substrate is formed using a laser, a diamond pen, or a chemical etching method or a dry etching method. At this time, the grooves have a depth of 5 to 100 µm and a width of 5 to 40 µm.
이하, 본 발명에 따른 후면 함몰전극형 태양전지를 제2A도를 참조하여 설명하기로 한다.Hereinafter, a back recessed electrode solar cell according to the present invention will be described with reference to FIG. 2A.
피라미드 구조가 형성되어 있는 p형 반도체 기판 (1)의 전면에는 n+층 (2)와 산화막 (5)가 순차적으로 형성되어 있고, 반도체 기판 (1) 후면내로 깊게 파인 하나이상의 홈에 p+층 (3)과 n+층 (2)가 교대로 형성되어 있다. 이 p+층 (3)과 n+층 (2) 상부에는 전도성 금속으로 이루어진 후면전극 (4)가 형성되어 있다. 이 때 반도체 기판 (1) 후면에서 홈이 형성되지 않은 영역은 산화막 (5)를 이용하여 비활성화시킨다.The front surface of the p-type semiconductor substrate (1) with a pyramidal texture is formed in n + layer 2 and the oxide film 5 that is formed sequentially, and the semiconductor substrate 1. p + layer on a pine least one groove deep into the rear (3) and n + layer (2) are alternately formed. On the p + layer 3 and the n + layer 2, a back electrode 4 made of a conductive metal is formed. At this time, the region in which the groove is not formed on the rear surface of the semiconductor substrate 1 is deactivated by using the oxide film 5.
본 발명에 따르면, 상기 반도체 기판 전면의 산화막 하부에 형성된 n+층은 없어도 무방하지만, 전면 전계의 형성면에서 고려해 볼 때 이 층을 형성하는 것이 보다 바람직하다.According to the present invention, the n + layer formed on the lower portion of the oxide film on the entire surface of the semiconductor substrate may be omitted, but it is more preferable to form this layer in consideration of the formation of the front electric field.
상기 후면전극 (4)의 하부에 형성되어 있는 p+층 (3)은 반도체 기판과 전극의 접촉저항 및 캐리아의 재결합으로 인한 손실을 감소시키기 위하여 보론을 도핑하여 형성시키며, n+층 (2)는 pn접합을 형성시키기 위하여 인을 도핑함으로써 형성한다.The p + layer 3 formed under the back electrode 4 is formed by doping boron in order to reduce the loss caused by the contact resistance of the semiconductor substrate and the electrode and the recombination of the carrier, and the n + layer 2 ) Is formed by doping phosphorus to form a pn junction.
본 발명에서는 산화막의 두께, 재질 등과 같은 막특성을 적절히 조절함으로써 산화막이 절연막 역할과 반사방지막 역할을 동시에 수행할 수 있다. 또한 산화막 상부에 반사방지막을 더 형성시킴으로써 반도체 기판 표면에서의 입사광의 반사를 최소화시킬 수 있다.In the present invention, the oxide film may serve as an insulating film and an anti-reflection film at the same time by appropriately adjusting the film properties such as the thickness, material, etc. of the oxide film. In addition, by further forming an anti-reflection film on the oxide film, it is possible to minimize the reflection of incident light on the surface of the semiconductor substrate.
한편, 제2B도에서 알 수 있는 바와 같이, 전지에서의 직렬저항을 감소시키기 위하여 p+층 (3)이 형성되어 있는 양극홈과 n+층 (2)가 형성되어 있는 음극홈이 서로 맞물리게 형성되어 있다.On the other hand, as can be seen in Figure 2B, in order to reduce the series resistance in the battery, the anode groove in which the p + layer 3 is formed and the cathode groove in which the n + layer 2 are formed are engaged with each other. It is.
본 발명에 따른 태양전지는 반도체 기판 후면내로 깊게 파여진 홈에 전극을 형성하므로 종래의 후면 전극형 태양전지보다 전극으로 수집되기 위한 캐리아 이동거리가 짧아짐으로써 캐리아의 수집효율이 증대되며, 효과적인 후면전계가 형성된다. 따라서 캐리아의 수명이 짧은 반도체 기판도 사용할 수 있다.The solar cell according to the present invention forms an electrode in a groove deeply dug into the back of the semiconductor substrate, so that the carry distance for collecting the electrode is shorter than that of the conventional back electrode type solar cell, thereby increasing the collecting efficiency of the carry and effectively The back field is formed. Therefore, a semiconductor substrate with a short lifetime of the carrier can also be used.
제1A도는 종래의 후면전극형 태양전지중에서 텍스처링된 블랙 태양전지(textured black solar cell)를, 제1B도는 포인트 콘택트 태양전지(point contact solar cell)를 나타내고,FIG. 1A shows a textured black solar cell in a conventional back-electrode type solar cell, FIG. 1B shows a point contact solar cell,
제2A도는 본 발명의 후면 함몰전극형 태양전지를 나타내고,2A shows a back recessed electrode type solar cell of the present invention,
제2B도는 본 발명의 후면 함몰전극형 태양전지에서 후면전극의 모양을 나타낸 도면이다.Figure 2B is a view showing the shape of the back electrode in the back recessed electrode solar cell of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
1. p형 반도체 기판 2. n+층1. p-type semiconductor substrate 2. n + layer
3. p+층 4. 후면전극3. p + layer 4. back electrode
5. 산화막 6. p+부스바아(busbar)5. Oxide 6. p + busbar
7. n+부스비아7. n + busvia
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| KR1019960000303A KR100378343B1 (en) | 1996-01-09 | 1996-01-09 | Backside recess electrode type solar cell |
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| KR1019960000303A KR100378343B1 (en) | 1996-01-09 | 1996-01-09 | Backside recess electrode type solar cell |
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| KR970060538A KR970060538A (en) | 1997-08-12 |
| KR100378343B1 true KR100378343B1 (en) | 2003-07-18 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2466342A (en) * | 2008-11-12 | 2010-06-23 | Silicon Cpv Plc | Photovoltaic solar cells |
| DE102010026289A1 (en) * | 2010-07-06 | 2012-01-12 | Sameday Media Gmbh | Solar cell has solar cell layer having several n-doped regions and p-doped regions which are alternately arranged such that successive p-doped and n-doped regions are separated and spaced from each other by intrinsic region |
| WO2013089879A2 (en) | 2011-09-30 | 2013-06-20 | Sunpower Corporation | Solar cell with doped groove regions separated by ridges |
| KR101549555B1 (en) * | 2009-01-30 | 2015-09-04 | 엘지전자 주식회사 | Semiconductor layer doping method Back contact solar cell by using the same method and Manufacturing method thereof |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100852700B1 (en) * | 2002-04-03 | 2008-08-19 | 삼성에스디아이 주식회사 | High efficient solar cell and fabrication method thereof |
| KR100863951B1 (en) * | 2002-05-29 | 2008-10-16 | 삼성에스디아이 주식회사 | Solar cell and fabrication method thereof |
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1996
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2466342A (en) * | 2008-11-12 | 2010-06-23 | Silicon Cpv Plc | Photovoltaic solar cells |
| WO2010055346A3 (en) * | 2008-11-12 | 2011-03-31 | Silicon Cpv Plc | Deep grooved rear contact photovoltaic solar cells |
| GB2466342B (en) * | 2008-11-12 | 2013-07-17 | Silicon Cpv Plc | Photovoltaic solar cells |
| US8889462B2 (en) | 2008-11-12 | 2014-11-18 | Silicon Cpv Plc | Photovoltaic solar cells |
| KR101561682B1 (en) | 2008-11-12 | 2015-10-20 | 실리콘 씨피브이 피엘씨 | Deep grooved rear contact photovoltaic solar cells |
| KR101549555B1 (en) * | 2009-01-30 | 2015-09-04 | 엘지전자 주식회사 | Semiconductor layer doping method Back contact solar cell by using the same method and Manufacturing method thereof |
| DE102010026289A1 (en) * | 2010-07-06 | 2012-01-12 | Sameday Media Gmbh | Solar cell has solar cell layer having several n-doped regions and p-doped regions which are alternately arranged such that successive p-doped and n-doped regions are separated and spaced from each other by intrinsic region |
| DE102010026289B4 (en) * | 2010-07-06 | 2014-10-30 | Sameday Media Gmbh | Solar cell and process |
| WO2013089879A2 (en) | 2011-09-30 | 2013-06-20 | Sunpower Corporation | Solar cell with doped groove regions separated by ridges |
| CN103999230A (en) * | 2011-09-30 | 2014-08-20 | 太阳能公司 | Solar cell with doped groove regions separated by ridges |
| EP2761671A4 (en) * | 2011-09-30 | 2015-02-25 | Sunpower Corp | Solar cell with doped groove regions separated by ridges |
| US9559228B2 (en) | 2011-09-30 | 2017-01-31 | Sunpower Corporation | Solar cell with doped groove regions separated by ridges |
Also Published As
| Publication number | Publication date |
|---|---|
| KR970060538A (en) | 1997-08-12 |
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