KR100317310B1 - Method for fabricating contact hole of semiconductor device - Google Patents

Method for fabricating contact hole of semiconductor device Download PDF

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KR100317310B1
KR100317310B1 KR1019970050953A KR19970050953A KR100317310B1 KR 100317310 B1 KR100317310 B1 KR 100317310B1 KR 1019970050953 A KR1019970050953 A KR 1019970050953A KR 19970050953 A KR19970050953 A KR 19970050953A KR 100317310 B1 KR100317310 B1 KR 100317310B1
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contact hole
forming
semiconductor device
chf
flow rate
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KR19990030642A (en
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김동석
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김영환
현대반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for forming a contact hole in a semiconductor device is provided to increase etch rate and to easily obtain fine contact hole by using high density plasma etching at low pressure. CONSTITUTION: An interlayer dielectric(22) is formed on a silicon substrate(21). After forming a photoresist pattern on the interlayer dielectric(22), a contact hole(24) is formed by selectively etching the interlayer dielectric(22) using the photoresist pattern as a mask and high density plasma etching using mixed gases of C4F8 and CHF3. At this time, the flow rate of the CHF3 gas is 30-100 sccm, and the flow rate of the C4F8 is 3-40 sccm.

Description

반도체 소자의 콘택홀 형성방법{METHOD FOR FABRICATING CONTACT HOLE OF SEMICONDUCTOR DEVICE}Method for forming contact hole in semiconductor device {METHOD FOR FABRICATING CONTACT HOLE OF SEMICONDUCTOR DEVICE}

본 발명은 반도체 소자의 제조방법에 관한 것으로 특히, 고밀도 집적소자 및 다층배선에 적당한 반도체 소자의 콘택홀 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device suitable for high density integrated devices and multilayer wiring.

이하, 첨부된 도면을 참조하여 종래의 반도체 소자의 콘택홀 형성방법을 설명하면 다음과 같다.Hereinafter, a method for forming a contact hole in a conventional semiconductor device will be described with reference to the accompanying drawings.

도 1a 내지 도 1c는 종래의 반도체 소자의 콘택홀 형성방법을 나타낸 공정단면도이다.1A to 1C are cross-sectional views illustrating a method of forming a contact hole in a conventional semiconductor device.

도 1a에 도시한 바와같이 실리콘 기판(11)상에 ILD(Inter Layer Dielectric)층(12)을 형성한 후, 평탄화공정을 실시한다.As shown in FIG. 1A, an ILD (Inter Layer Dielectric) layer 12 is formed on the silicon substrate 11, and then a planarization process is performed.

이어, 상기 ILD층(12)상에 포토레지스트(Photo Resist)(13)를 도포한 후, 노광 및 현상공정으로 상기 포토레지스트(13)를 패터닝(Patterning)한다.Subsequently, after the photoresist 13 is applied onto the ILD layer 12, the photoresist 13 is patterned by an exposure and development process.

도 1b에 도시한 바와같이 상기 패터닝된 포토레지스트(13)를 마스크로 이용하여 Ar, CF4, CHF3의 혼합 가스를 이용한 플라즈마로 상기 실리콘 기판(11)의 표면이 소정부분 노출되도록 상기 ILD층(12)을 선택적으로 식각하여 콘택홀(Contact Hole)(14)을 형성한다.As shown in FIG. 1B, the patterned photoresist 13 is used as a mask so that a predetermined portion of the surface of the silicon substrate 11 is exposed by a plasma using a mixed gas of Ar, CF 4 , and CHF 3 . (12) is selectively etched to form a contact hole (14).

여기서 상기 식각반응은 RIE(Reactive Ion Etching), 플라즈마(Plasma) 등의 플라즈마 방식을 이용한 장치에서 진해되어지며, 사용되는 화학 가스는 Ar, CF4, CHF3의 혼합 가스를 사용한다.Here, the etching reaction is carried out in a device using a plasma method such as reactive ion etching (RIE), plasma (Plasma), the chemical gas used is a mixture of Ar, CF 4 , CHF 3 .

한편, 상기 Ar 가스는 플라즈마 안정화 및 스퍼터닝(Sputtering) 효과를 나타내는 역할로써 작용하고, 반응에 직접 참여하지는 않는다.On the other hand, the Ar gas acts as a role of showing plasma stabilization and sputtering effects, and does not directly participate in the reaction.

따라서 주요 식각 반응은 CF4와 CHF3에 의해서 일어나게 되고, 식각시 상기 실리콘 기판(11)의 물질인 반도체(Si)와의 선택비는 이 두가지 가스의 비(Ratio)에 의해서 결정된다.Therefore, the main etching reaction is caused by CF 4 and CHF 3 , and the selectivity with respect to the semiconductor (Si), which is a material of the silicon substrate 11, is determined by the ratio of the two gases during etching.

일반적으로 사용 가스의 유량은 Ar 가스의 경우 200 ~ 1000sccm 범위의 유량을 사용하고, CF4와 CHF3가스는 20 ~ 100sccm 범위의 유량을 사용하고, 상기 CF4와 CHF3가스의 유량비는 선택비에 의해서 결정되어지며, 대략 0.9 ~ 1.5의 값을 적용한다.In general, the flow rate of the used gas is a flow rate in the range of 200 ~ 1000sccm for Ar gas, the CF 4 and CHF 3 gas uses a flow rate in the range of 20 ~ 100sccm, the flow rate ratio of the CF 4 and CHF 3 gas is a selection ratio Is determined by a value of approximately 0.9 to 1.5.

그리고 RF 파워(Power)의 범위는 소자 구조에 따라서 800 ~ 1500W의 수준을 사용한다.RF power ranges from 800W to 1500W depending on the device structure.

도 1c에 도시한 바와같이 상기 콘택홀(14)을 형성한 후, 상기 포토레지스트(13)를 제거한다.After the contact hole 14 is formed as shown in FIG. 1C, the photoresist 13 is removed.

그러나 이와 같은 종래의 반도체 소자의 콘택홀 형성방법에 있어서 다음과 같은 문제점이 있었다.However, the conventional method of forming a contact hole in a semiconductor device has the following problems.

첫째, CF4와 CHF3그리고 Ar의 유량비를 이용하여 기판에 대한 선택비를 조절하는데 그 값에 한계가 있기 때문에 콘택홀을 형성하기 위해 식각시 기판이 손실된다.First, the substrate is lost during etching to form a contact hole because there is a limit in controlling the selectivity for the substrate by using a flow ratio of CF 4 , CHF 3 and Ar.

둘째, CF4와 CHF3그리고 Ar를 사용한 플라즈마 식각장치는 애노드(Anode)와 캐소우드(Cathode)간의 큰 전압차로 아칭(Arching)이 발생하고, 플라즈마 균일성이 떨어진다.Second, in the plasma etching apparatus using CF 4 , CHF 3 and Ar, arching occurs due to a large voltage difference between the anode and the cathode, and the plasma uniformity is poor.

셋째, 화학가스(CF4, CHF3, Ar) 및 식각장치의 경우 마이크로로딩 효과(Microloading Effect)가 발생하여 미세한 크기의 홀을 형성하기가 어렵다.Third, in the case of chemical gases (CF 4 , CHF 3 , Ar) and an etching apparatus, a microloading effect occurs, and thus it is difficult to form holes having a fine size.

본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로 고밀도 플라즈마 소스인 TCP(Transformer Coupled Plasma)를 사용하여 CHF3와 C4F8을 적용함으로써 고밀도 집적소자 및 다층배선에 필요한 반도체 소자의 콘택홀 형성방법을 제공하는데 그 목적이 있다.The present invention has been made in order to solve the above problems, by applying CHF 3 and C 4 F 8 using a high density plasma source TCP (Transformer Coupled Plasma) to contact holes of semiconductor devices required for high-density integrated devices and multilayer wiring The purpose is to provide a formation method.

도 1a 내지 도 1c는 종래의 반도체 소자의 콘택홀 형성방법을 나타낸 공정단면도1A through 1C are cross-sectional views illustrating a method of forming a contact hole in a conventional semiconductor device.

도 2a 내지 도 2c는 본 발명에 의한 반도체 소자의 콘택홀 형성방법을 나타낸 공정단면도2A through 2C are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device according to the present invention.

도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings

21 : 실리콘 기판 22 : ILD층21 silicon substrate 22 ILD layer

23 : 포토레지스트 24 : 콘택홀23: photoresist 24: contact hole

상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 콘택홀 형성방법은 기판상에 절연막을 형성하는 단계와, 상기 절연막상에 선택적으로 마스크층을 형성하는 단계와, 그리고 상기 마스크층을 마스크로 이용하여 고밀도 플라즈마 장비에서 CxFy와 CHF3의 혼합가스로 상기 절연막을 선택적으로 식각하여 콘택홀을 형성하는 단계를 포함하여 형성함을 특징으로 한다.A method of forming a contact hole in a semiconductor device according to the present invention for achieving the above object comprises the steps of forming an insulating film on a substrate, selectively forming a mask layer on the insulating film, and masking the mask layer Forming a contact hole by selectively etching the insulating film with a mixed gas of CxFy and CHF 3 in a high-density plasma equipment using a.

이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 콘택홀 형성방법을 상세히 설명하면 다음과 같다.Hereinafter, a method of forming a contact hole in a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

본 발명은 먼저, 장치 측면에서 고밀도 플라즈마 소스(Plasma Source)중의 하나인 TCP(Transformer Coupled Plasma)를 이용한다.The present invention first uses a Transformer Coupled Plasma (TCP), which is one of the high density plasma sources in terms of apparatus.

즉, 고밀도 플라즈마이므로 높은 식각 속도(7000Å/min 이상)를 가지고 있어 공정 시간을 단축할 수가 있다. 또한 저압 공정이 가능하여 가스 선택에 있어 폭이 넓으므로 선택비가 높은 가스들을 사용할 수 있다.That is, since it is a high-density plasma, it has a high etching rate (7000 mW / min or more) and can shorten a process time. In addition, the low pressure process allows a wider range of gas selection, allowing the use of high selectivity gases.

그리고 바이어스 파워(Bias Power)를 독립적으로 조정이 가능하고 실제 웨이퍼에 인가되는 셀프바이어스(Selfbias) 경우 기존 장치들에 비해 양호한 값인 -100V 이하의 수준을 나타낸다.In addition, the bias power can be adjusted independently, and the self-bias applied to the actual wafer shows a level of -100V or less, which is better than the existing devices.

두 번째로 가스 측면에서 CHF3와 C4F8혼합가스를 사용하여 반도체 기판에 대한 선택비를 더욱 향상시키도록 하였다.Secondly, CHF 3 and C 4 F 8 mixed gases were used to improve the selectivity to the semiconductor substrate.

상기 C4F8가스의 경우 전자들과의 충돌에 의해서 작은 분자인 CF2, CF 등의 형태로 분해가 되고, 이러한 형태로 산화막과의 반응에 참여하게 된다.The C 4 F 8 gas is decomposed into small molecules such as CF 2 and CF by collision with electrons, and participates in the reaction with the oxide film in this form.

분해 과정에서 떨어져 나온 자유 불소 원자들의 많은 부분이 식각 장치내의 전극에 흡착되어 소모되므로 드러나게 되면 반도체 기판 표면에 폴리머가 발생하여 반도체 기판을 보호하는 역할을 한다.A large portion of the free fluorine atoms released during the decomposition process is adsorbed and consumed by the electrodes in the etching apparatus, and when exposed, polymers are generated on the surface of the semiconductor substrate to protect the semiconductor substrate.

그리고 상기 폴리머는 이후의 세정 단계에서 쉽게 제거가 된다.The polymer is then easily removed in subsequent cleaning steps.

도 2a 내지 도 2c는 본 발명에 의한 반도체 소자의 콘택홀 형성방법을 나타낸 공정단면도이다.2A to 2C are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device according to the present invention.

도 2a에 도시한 바와같이 실리콘 기판(21)상에 ILD(Inter Layer Dielectric)층(22)을 형성한 후, 평탄화공정을 실시한다.As shown in FIG. 2A, an ILD (Inter Layer Dielectric) layer 22 is formed on the silicon substrate 21, and then a planarization process is performed.

이어, 상기 ILD층(22)상에 포토레지스트(Photo Resist)(23)를 도포한 후, 노광 및 현상공정으로 상기 포토레지스트(23)를 패터닝(Patterning)한다.Subsequently, after the photoresist 23 is applied onto the ILD layer 22, the photoresist 23 is patterned by an exposure and development process.

도 2b에 도시한 바와같이 상기 패터닝된 포토레지스트(23)를 마스크로 이용하여 상기 실리콘 기판(21)의 표면이 소정부분 노출되도록 상기 ILD층(22)을 선택적으로 식각하여 콘택홀(Contact Hole)(24)을 형성한다.As shown in FIG. 2B, the ILD layer 22 is selectively etched using the patterned photoresist 23 as a mask to expose a predetermined portion of the surface of the silicon substrate 21 to form a contact hole. To form (24).

여기서 식각반응은 고밀도 플라즈마(플라즈마가 10E12/cm3이상)중의 하나인TCP 방식을 이용한 장치에서 진행되어지며, 사용 가스는 CHF3와 C4F8의 혼합 가스를 사용한다.The etching reaction is carried out in a device using a TCP method, one of the high-density plasma (plasma is 10E12 / cm 3 or more), the gas used is a mixture of CHF 3 and C 4 F 8 .

상기 C4F8은 식각반응중 폴리머(Polymer) 생성에 직접적인 영향을 주는 가스로서 작용하며, 주요 식각 반응은 CHF3에 의해서 일어나게 되며 C4F8없이도 가능하다.The C 4 F 8 acts as a gas that directly affects polymer formation during the etching reaction, and the main etching reaction is caused by CHF 3 and can be performed without C 4 F 8 .

그리고 사용 가스 유량은 CHF3가스의 경우 20 ~ 60sccm 범위의 유량을 사용하고, C4H8가스는 3 ~ 20sccm 범위의 유량을 사용한다.The gas flow rate is used in the range of 20 to 60 sccm for the CHF 3 gas, and the flow rate of 3 to 20 sccm for the C 4 H 8 gas.

한편, 상기 두 가스의 유량비 CHF3/C4F8는 8 ~ 12의 값을 적용하고, RF 파워의범위는 구조에 따라서 상부전극(Top Electrode)의 경우 800 ~ 1500W의 수준을 사용하며, 하부전극(Bottom Electrode)에는 1000 ~ 2000W 의 수준을 사용한다.On the other hand, the flow rate ratio of the two gases CHF 3 / C 4 F 8 is applied to the value of 8 ~ 12, the RF power range of 800 ~ 1500W in the case of the top electrode (Top Electrode) depending on the structure, the lower The electrode (Bottom Electrode) uses a level of 1000 ~ 2000W.

또한 압력은 1mT ~ 20mT를 사용한다.Also, the pressure is 1mT ~ 20mT.

도 2c에 도시한 바와같이 상기 콘택홀(24)을 형성한 후, 상기 포토레지스트(23)를 제거한다.After the contact hole 24 is formed as shown in FIG. 2C, the photoresist 23 is removed.

이상에서 설명한 바와같이 본 발명에 의한 반도체 소자의 콘택홀 형성방법에 있어서 다음과 같은 효과가 있다.As described above, the contact hole forming method of the semiconductor device according to the present invention has the following effects.

첫째, 식각시 기판에 대한 선택비가 우수하여 미세한 홀 및 종횡비(Aspect Ratio)가 홀에서도 공정 적용이 가능하다.First, since the selectivity with respect to the substrate during the etching is excellent, it is possible to apply the process even in the minute hole and aspect ratio (hole).

둘째, 저압에서 고밀도 플라즈마로 식각함으로써 식각률이 높고, 반응 챔버(Chamber) 구조가 간단하며, 플라즈마를 넓고 균일하게 형성할 수 있고, 대구경화에 적용할 수 있다.Second, by etching with a high-density plasma at low pressure, the etching rate is high, the reaction chamber (Chamber) structure is simple, the plasma can be formed wide and uniform, and can be applied to large diameters.

Claims (4)

기판상에 절연막을 형성하는 단계;Forming an insulating film on the substrate; 상기 절연막상에 선택적으로 마스크층을 형성하는 단계;Selectively forming a mask layer on the insulating film; 상기 마스크층을 마스크로 이용하여 고밀도 플라즈마 장비에서 C4F8과 CHF3의 혼합가스로 상기 절연막을 선택적으로 식각하여 콘택홀을 형성하는 단계를 포함하여 형성함을 특징으로 하는 반도체 소자의 콘택홀 형성방법.And forming a contact hole by selectively etching the insulating layer with a mixed gas of C 4 F 8 and CHF 3 in a high density plasma apparatus using the mask layer as a mask. Formation method. 제 1 항에 있어서, 상기 CHF3가스는 30~100sccm 범위의 유량을 사용하고, 상기 C4F8가스는 3~40sccm 범위의 유량을 사용함을 특징으로 하는 반도체 소자의 콘택홀 형성방법.The method of claim 1, wherein the CHF 3 gas uses a flow rate in the range of 30 to 100 sccm, and the C 4 F 8 gas uses a flow rate in the range of 3 to 40 sccm. 제 1 항에 있어서, 상기 CHF3과 C4F8의 유량비는 8~12임을 특징으로 하는 반도체 소자의 콘택홀 형성방법.The method of claim 1, wherein the flow rate ratio between the CHF 3 and the C 4 F 8 is 8 to 12. 9. 제 1 항에 있어서, 상기 고밀도 플라즈마 장비를 사용할 때 RF 파워는 상부전극은 800 ~ 2000W를 적용하고, 하부전극은 1000 ~ 2000W를 적용하며, 압력은 1mT ~ 20mT를 사용하는 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.The semiconductor device according to claim 1, wherein the RF power is applied to the upper electrode 800 to 2000W, the lower electrode 1000 to 2000W, and the pressure is 1mT ~ 20mT when using the high-density plasma equipment. Contact hole formation method.
KR1019970050953A 1997-10-02 1997-10-02 Method for fabricating contact hole of semiconductor device KR100317310B1 (en)

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Publication number Priority date Publication date Assignee Title
KR102502993B1 (en) 2022-04-02 2023-02-23 박병화 Semiconductor device socket hole perforation system

Citations (1)

* Cited by examiner, † Cited by third party
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JPH04106922A (en) * 1990-08-27 1992-04-08 Hitachi Ltd Dry etching method

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04106922A (en) * 1990-08-27 1992-04-08 Hitachi Ltd Dry etching method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102502993B1 (en) 2022-04-02 2023-02-23 박병화 Semiconductor device socket hole perforation system

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