KR100769149B1 - Method for forming semiconductor device - Google Patents
Method for forming semiconductor device Download PDFInfo
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- KR100769149B1 KR100769149B1 KR1020060085121A KR20060085121A KR100769149B1 KR 100769149 B1 KR100769149 B1 KR 100769149B1 KR 1020060085121 A KR1020060085121 A KR 1020060085121A KR 20060085121 A KR20060085121 A KR 20060085121A KR 100769149 B1 KR100769149 B1 KR 100769149B1
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- gas
- contact hole
- nitrogen
- semiconductor device
- insulating layer
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- 238000000034 method Methods 0.000 title claims abstract description 46
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 239000007789 gas Substances 0.000 claims abstract description 45
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 31
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 19
- 229920000642 polymer Polymers 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 8
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 claims abstract description 4
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910002091 carbon monoxide Inorganic materials 0.000 claims abstract description 4
- 229910001882 dioxygen Inorganic materials 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims abstract description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 13
- 238000000059 patterning Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 239000006227 byproduct Substances 0.000 abstract description 10
- 229910001873 dinitrogen Inorganic materials 0.000 abstract description 5
- 239000000203 mixture Substances 0.000 abstract 1
- 239000011229 interlayer Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000010410 layer Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 239000005368 silicate glass Substances 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- -1 Boro Phosphor Chemical compound 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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Abstract
Description
도 1은 종래 기술에 따른 절연막에 형성된 컨택 홀의 단면을 SEM을 통해 촬영한 이미지.1 is a cross-sectional image of a contact hole formed in the insulating film according to the prior art taken by SEM.
도 2a는 본 발명에 따른 반도체 소자 형성 방법을 설명하기 위한 단면도.2A is a cross-sectional view illustrating a method of forming a semiconductor device in accordance with the present invention.
도 2b는 본 발명에 따른 반도체 형성방법에 따라 형성된 컨택 홀의 단면을 SEM을 통해 촬영한 이미지.Figure 2b is an image taken with a cross section of the contact hole formed in accordance with the semiconductor forming method according to the present invention.
*** 도면의 주요 부분에 대한 부호의 설명 ****** Explanation of symbols for the main parts of the drawing ***
200 : 실리콘 기판 202 : 층간 절연막200
204 : 포토 레지스트 패턴204 photoresist pattern
본 발명은 반도체 소자 형성방법에 관한 것으로, 특히, 패터닝된 포토 레지스트 패턴을 마스크로 이용하고, 질소계 가스를 이용하는 식각공정을 수행하여 절연막을 소정의 깊이까지 식각하여 원하는 컨택 홀을 형성시킬 수 있도록 하는 반도체 소자 형성방법에 관한 것이다.The present invention relates to a method of forming a semiconductor device, and in particular, by using a patterned photoresist pattern as a mask, and performing an etching process using a nitrogen-based gas to etch the insulating film to a predetermined depth to form a desired contact hole It relates to a method for forming a semiconductor device.
도 1은 종래 기술에 따른 절연막에 형성된 컨택 홀의 단면을 SEM을 통해 촬 영한 이미지이다.1 is a cross-sectional view of a contact hole formed in an insulating film according to the prior art by SEM.
도 1에서 보는 바와 같이, 컨택 홀 공정을 포함하는 반도체 소자 형성방법에서 소정의 반도체 회로 소자들을 포함하는 실리콘 기판 상부에 층간 절연막을 형성하고, 형성된 층간 절연막 상부에 ArF용 포토 레지스트를 형성하여 패터닝하며, 패터닝된 ArF용 포토 레지스트를 마스크로 이용하여 절연막을 실리콘 기판의 금속 배선이 보이도록 식각공정을 수행하여 컨택 홀을 형성한다.As shown in FIG. 1, in the method of forming a semiconductor device including a contact hole process, an interlayer insulating film is formed on a silicon substrate including predetermined semiconductor circuit elements, and an ArF photoresist is formed on and formed on the formed interlayer insulating film. Using the patterned ArF photoresist as a mask, the insulating layer is etched to show the metal wiring of the silicon substrate, thereby forming contact holes.
그러나, 이러한 반도체 소자 형성공정에서 주 식각가스로 CxFx 계 가스와 부 식각가스로 CO, Ar, O2등을 사용하여 포토 레지스트 패턴을 마스크로 이용하여 반도체 소자의 절연물을 선택적으로 식각하는 경우에 ArF용 포토 레지스트 패턴으로부터 생성된 폴리머 성분의 부산물이 컨택 홀의 바닥에 잔류하여 원하는 깊이까지 식각하지 못하여(예컨대,식각정지(Etch Stop) 현상) 원하는 컨택 홀을 형성시키지 못하는 문제점이 발생한다.However, in the process of forming a semiconductor device, in the case of selectively etching the insulator of the semiconductor device using a photoresist pattern as a mask using CxFx-based gas as a main etching gas and CO, Ar, O2 as a secondary etching gas, The byproduct of the polymer component generated from the photoresist pattern remains at the bottom of the contact hole and fails to etch to a desired depth (for example, an etch stop phenomenon), thereby failing to form a desired contact hole.
본 발명은 상술한 바와 같은 종래 기술의 문제점을 해결하기 위하여 제안된 것으로, 질소계 공정가스를 사용하는 식각공정을 수행하는 경우에 폴리머 성분의 부산물 생성을 최소화하여 절연막의 식각률을 높이고, 원하는 컨택 홀이 형성될 수 있도록 하는 반도체 소자 형성방법을 제공하는 데 목적이 있다.The present invention is proposed to solve the problems of the prior art as described above, when performing the etching process using a nitrogen-based process gas to minimize the by-product generation of the polymer component to increase the etching rate of the insulating film, the desired contact hole It is an object of the present invention to provide a method for forming a semiconductor device that can be formed.
전술한 목적을 달성하기 위한 본 발명의 일실시 예에 따른 반도체 소자 형성방법의 일 특징은, 반도체 기판상에 절연막을 증착하는 단계, 상기 절연막 상에 포토레지스트를 도포한 후, 패터닝하여 포토레지스트 패턴을 형성하는 단계, 상기 포토레지스트 패턴을 마스크로 이용하고, 질소계 가스를 공정가스로 이용하여 상기 절연막을 선택적으로 식각하여 컨택홀을 형성하는 단계 및 상기 컨택홀 내부에 형성되는 폴리머 성분의 부산물이 상기 질소계 가스와 이온화 반응하여 생성된 CN계 물질을 제거하는 단계를 포함하여 이루어지는 것이다.
보다 바람직하게, 상기 식각공정은, 상기 공정가스와 CF계 가스, 산소 가스 및 일산화탄소 가스로 구성되는 그룹 중에서 선택되는 적어도 하나의 가스로 구성되는 혼합가스를 이용하여 이루어진다. One feature of a method of forming a semiconductor device according to an embodiment of the present invention for achieving the above object is a step of depositing an insulating film on a semiconductor substrate, after applying the photoresist on the insulating film, by patterning the photoresist pattern Forming a contact hole by selectively etching the insulating layer using the photoresist pattern as a mask, using a nitrogen-based gas as a process gas, and by-products of a polymer component formed inside the contact hole. And removing the CN-based material generated by ionization with the nitrogen-based gas.
More preferably, the etching process is performed using a mixed gas composed of at least one gas selected from the group consisting of the process gas, CF-based gas, oxygen gas and carbon monoxide gas.
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이하에서 첨부된 도면을 참조하여 본 발명에 따른 컨택 홀 형성방법을 포함한 반도체 소자 형성방법에 대해서 상세히 설명한다.Hereinafter, a method of forming a semiconductor device including a method of forming a contact hole according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a는 본 발명에 따른 반도체 소자 형성방법을 설명하기 위한 단면도이다.2A is a cross-sectional view illustrating a method of forming a semiconductor device in accordance with the present invention.
도 2a를 살펴보면, 하부에 금속배선을 포함하는 실리콘 기판(200) 전면 상부에 소정의 두께로 층간 절연막(202)을 형성하고, 형성된 층간 절연막(202) 상부에 포토 레지스트 물질을 소정의 두께로 도포한 후 패터닝하여 포토 레지스트 패턴, 즉 ArF 용 포토 레지스트 패턴(204)을 형성한다.Referring to FIG. 2A, an interlayer
여기서, 층간 절연막(202)은 BPSG(Boro Phosphor Silicate Glass) 막, PSG(Phosphor Silicate Glass) 막, USG(Un-doped Silicate Glass) 막 및 TEOS(Tetra Ethyl Ortho Silicate) 막 중 어느 하나를 이용할 수 있다.Here, the
그 다음, ArF용 포토 레지스트 패턴(204)을 마스크로 이용하고 층간 절연막(20)에 주성분의 질소계 가스와 부가스를 함유한 공정가스를 이용하는 식각공정을 수행하여 실리콘 기판(200)의 금속 배선이 보이도록 절연막(202)을 선택적으로 식각하여 컨택 홀을 형성한다.Subsequently, the metal wiring of the
도2b는 본 발명에 따른 반도체 형성방법에 따라 형성된 컨택 홀의 단면을 SEM을 통해 촬영한 이미지이다.2B is a cross-sectional image of a contact hole formed in accordance with the method of forming a semiconductor according to the present invention by SEM.
도 2b에서 보는 바와 같이, 질소계 가스를 주성분으로 하는 공정가스에 부가스를 함유하여 이용하는 식각공정은 챔버 내의 분위기 압력을 예를 들어 80~110mT으로 하고, 소스 파워를 예를 들어 500~1000W으로 하며, 바이어스 파워를 예를 들어 500~1000W으로 하고, 소정의 공정시간 동안 질소계 가스를 주성분으로 하는 공정가스에 부가스를 함유하여 식각공정을 수행하는 것으로 설정할 수 있다. 여기서, 공정시간은 식각하고자 하는 컨택 홀의 깊이에 따라 설정할 수 있다.As shown in FIG. 2B, in the etching process in which a gas is used in the process gas mainly containing nitrogen gas, the atmospheric pressure in the chamber is, for example, 80 to 110 mT, and the source power is, for example, 500 to 1000 W. For example, the bias power may be set to 500 to 1000 W, and the etching process may be performed by adding an adduct to a process gas mainly containing a nitrogen-based gas for a predetermined process time. Here, the process time may be set according to the depth of the contact hole to be etched.
질소계 가스를 주성분으로 하는 공정가스에 함유한 부가스를 사용하는 식각공정을 상세히 설명하면, 챔버 내에서 소정의 공정시간 동안 분위기 압력을 예를 들어 80~110mT, 소스 파워를 예를 들어 500~1000W, 바이어스 파워를 예를 들어 500~1000W으로 한 상태에서 질소계 가스인 예를 들어 100~200sccm의 N2와, 부가스의 CF계 가스인 예를 들어 7~20sccm의 C4F6와, 50~100의 일산화 가스(CO) 및 예를 들어 1~5sccm의 산소가스(O2)를 포함한다.In detail, the etching process using the gas used in the process gas mainly containing nitrogen-based gas, the atmosphere pressure during the predetermined process time in the chamber, for example, 80 ~ 110mT, the source power, for example 500 ~ For example, N 2 of 100-200 sccm, which is a nitrogen gas, and C 4 F 6 of 7-20 sccm, which is a CF gas of a gas of 1000 W, and a bias power of 500-1000 W, for example, are nitrogen gas; monoxide gas (CO) of 50 to 100, and include, for example, oxygen gas (O 2) of 1 ~ 5sccm.
이와 같은 질소계 가스를 주성분으로 하는 공정 가스에 함유된 부가스를 이용하여 반응성 이온식각(RIE:Reactive Ion Etching) 또는 자기강화 반응성 이온식각(MERIE:Magnetic Enhanced Reative Ion Etching) 방법을 통해 절연막의 컨택 홀 내부에 형성되는 폴리머 성분의 부산물 생성을 최소화하고, 생성된 폴리머 성분의 부산물을 질소계 가스와 이온화 반응하여 CN 형태로 제거하여 절연막(202)에 원하는 컨택 홀을 형성시킬 수 있다.Contact of the insulating layer using reactive ion etching (RIE) or magnetic enhanced reactive ion etching (MERIE) using an additive gas contained in such a nitrogen-based process gas. By-product generation of the polymer component formed in the hole may be minimized, and the resulting by-product of the polymer component may be ionized with a nitrogen-based gas to be removed in the form of CN to form a desired contact hole in the
따라서, 도 2b를 보는 바와 같이, 본 발명을 통해 컨택 홀 형성공정에서 폴리머 성분의 생성을 최소화하고, 생성된 폴리머 성분의 부산물을 CN 형태로 제거할 수 있으므로, 정확한 컨택 홀을 형성시킬 수 있다.Therefore, as shown in Figure 2b, the present invention can minimize the production of the polymer component in the contact hole forming process, and by-products of the generated polymer component can be removed in the form of CN, it is possible to form an accurate contact hole.
이상과 같이 본 발명은 비록 한정된 실시 예와 도면에 의해 설명되었으나, 본 발명은 상기의 실시 예에 한정되는 것은 아니며, 본 발명이 속하는 분야에서 통상의 지식을 가진 자라면, 이러한 기재로부터 다양한 수정 및 변형이 가능하다.As described above, although the present invention has been described with reference to the limited embodiments and the drawings, the present invention is not limited to the above-described embodiments, and those skilled in the art to which the present invention pertains, various modifications and Modifications are possible.
그러므로, 본 발명의 범위는 설명된 실시예에 국한되어 정해져서는 아니되며, 후술하는 특허청구범위뿐만 아니라 이 특허 청구범위와 균등한 것들에 의해 정해져야 한다.Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined by the claims below and equivalents thereof.
이상에서 설명한 바와 같이, 본 발명에 따른 컨택 홀 형성과정에서 주성분으로 하는 질소계 가스와 부가스를 함유한 공정가스를 이용하는 식각공정을 수행하여 절연막을 선택적으로 식각하는 경우에 폴리머 성분의 부산물 생성을 최소화하고, 생성되는 폴리머 성분의 부산물을 CN 형태로 제거함으로써, 절연막에 정확한 컨택 홀을 형성시킬 수 있는 효과가 있다.As described above, when the insulating film is selectively etched by performing an etching process using a nitrogen-based gas and a process gas containing as a main component in the process of forming a contact hole according to the present invention, by-product formation of the polymer component is generated. By minimizing and removing the by-products of the resulting polymer component in the form of CN, it is possible to form accurate contact holes in the insulating film.
본 발명의 또 다른 효과로는 질소계 가스를 사용하는 식각공정을 수행하여 절연막을 선택적으로 식각하는 경우에 ArF용 포토레지스트 패턴이 심하게 제거되지 않아 마스크 역할을 충분히 할 수 있으며, 그로 인해 ArF용 포토레지시트 패턴의 CD 마진을 일정하게 유지할 수 있는 효과가 있다.In another embodiment of the present invention, when the insulating film is selectively etched by performing an etching process using a nitrogen-based gas, the ArF photoresist pattern may not be severely removed, thereby sufficiently serving as a mask, and thus the ArF photo The CD margin of the resist pattern can be kept constant.
Claims (7)
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000036484A (en) * | 1998-05-11 | 2000-02-02 | Tokyo Electron Ltd | Plasma processing method |
| KR20010047180A (en) | 1999-11-18 | 2001-06-15 | 박종섭 | Manufacturing method for contact hole in semiconductor device |
| KR20020036255A (en) | 2000-11-09 | 2002-05-16 | 윤종용 | Method for fabricating fine contact hole of semiconductor device |
| KR20050041264A (en) | 2003-10-30 | 2005-05-04 | 주식회사 하이닉스반도체 | Method for fabrication of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000036484A (en) * | 1998-05-11 | 2000-02-02 | Tokyo Electron Ltd | Plasma processing method |
| KR20010047180A (en) | 1999-11-18 | 2001-06-15 | 박종섭 | Manufacturing method for contact hole in semiconductor device |
| KR20020036255A (en) | 2000-11-09 | 2002-05-16 | 윤종용 | Method for fabricating fine contact hole of semiconductor device |
| KR20050041264A (en) | 2003-10-30 | 2005-05-04 | 주식회사 하이닉스반도체 | Method for fabrication of semiconductor device |
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