KR100265348B1 - Method for fabricating mosfet having polycide gate - Google Patents
Method for fabricating mosfet having polycide gate Download PDFInfo
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- KR100265348B1 KR100265348B1 KR1019980024652A KR19980024652A KR100265348B1 KR 100265348 B1 KR100265348 B1 KR 100265348B1 KR 1019980024652 A KR1019980024652 A KR 1019980024652A KR 19980024652 A KR19980024652 A KR 19980024652A KR 100265348 B1 KR100265348 B1 KR 100265348B1
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- film
- semiconductor substrate
- etching
- polysilicon
- metal silicide
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- 238000000034 method Methods 0.000 title claims abstract description 36
- 239000010408 film Substances 0.000 claims abstract description 50
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 31
- 229920005591 polysilicon Polymers 0.000 claims abstract description 31
- 239000004065 semiconductor Substances 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 19
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 19
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 claims abstract description 13
- 239000010410 layer Substances 0.000 claims abstract description 11
- 230000003647 oxidation Effects 0.000 claims abstract description 11
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims abstract description 9
- 239000010409 thin film Substances 0.000 claims abstract description 8
- 239000000126 substance Substances 0.000 claims abstract description 6
- 238000005498 polishing Methods 0.000 claims abstract description 5
- 239000011229 interlayer Substances 0.000 claims abstract description 3
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 24
- 238000005468 ion implantation Methods 0.000 claims description 10
- 125000006850 spacer group Chemical group 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 2
- 229910017052 cobalt Inorganic materials 0.000 claims description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims description 2
- 229910021334 nickel silicide Inorganic materials 0.000 claims 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 claims 1
- 230000002159 abnormal effect Effects 0.000 abstract description 3
- 230000006866 deterioration Effects 0.000 abstract 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 7
- 239000010936 titanium Substances 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 5
- 229910008484 TiSi Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 229910019001 CoSi Inorganic materials 0.000 description 2
- 229910010413 TiO 2 Inorganic materials 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- 229910005881 NiSi 2 Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
Abstract
본 발명은 실리사이드막이 이상산화(Abnormal Oxidation)되는 것과 실리사이드와 폴리실리콘의 계면특성 저하를 방지하여, 안정한 폴리사이드 게이트를 이루는 MOSFET 제조방법을 제공하고자하는 것으로, 이를 위한 본 발명은, 반도체소자 제조방법에 있어서, 반도체기판 상에 게이트절연막, 폴리실리콘막을 순차적으로 형성하는 제1단계; 게이트 마스크 및 식각공정을 실시하여 상기 반도체기판 상에 증착된 박막들을 패터닝하는 제2단계; 열산화 공정을 실시하여 반도체기판에 스크린산화막을 성장시키는 제3단계; 상기 반도체기판에 소스/드레인을 형성하는 제4단계; 층간절연막을 증착하고 상기 폴리실리콘막 표면이 노출되도록 기판전면을 화학적기계적연마하는 제5단계; 상기 노출된 폴리실리콘막을 일부두께 식각하여 요부를 형성하는 제6단계; 및 상기 요부내에 금속실리사이드막을 증착하는 제7단계를 포함하여 이루어진다.The present invention is to provide a MOSFET manufacturing method for forming a stable polyside gate by preventing abnormal oxidation of the silicide film and deterioration of interfacial properties of the silicide and polysilicon, and the present invention provides a semiconductor device manufacturing method. A first step of sequentially forming a gate insulating film, a polysilicon film on a semiconductor substrate; A second step of patterning thin films deposited on the semiconductor substrate by performing a gate mask and an etching process; Performing a thermal oxidation process to grow a screen oxide film on the semiconductor substrate; Forming a source / drain on the semiconductor substrate; Depositing an interlayer dielectric layer and chemical mechanical polishing the entire surface of the substrate to expose the surface of the polysilicon layer; A sixth step of etching a portion of the exposed polysilicon film to form recesses; And a seventh step of depositing a metal silicide film in the recess.
Description
본 발명은 고집적 반도체 메모리소자 제조 공정중, 폴리사이드 게이트(워드라인)를 갖는 모스펫(MOSFET) 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a MOSFET having a polyside gate (word line) during a manufacturing process of a highly integrated semiconductor memory device.
최근 반도체 메모리소자의 집적도가 급격히 증가함에 따라 이에 상응하여 게이트 전극(Gate Electrode)(워드라인)의 요구선폭이 급격히 감소되고 있다. 그 결과 종래의 게이트 전극 물질로서 사용되는 폴리실리콘(Polysilicon) 또는 텅스텐실리사이드(WSi2)/폴리실리콘과 같은 폴리사이드로써는 고집적 반도체소자에서 요구되는 낮은 저항값을 미세선폭상에서 구현할 수 없게 되었다. 그래서 근래에는 타이타늄 실리사이드(TiSi2), CoSi2, NiSi2등의 실리사이드계열 물질을 적용한 게이트 전극 형성에 대하여 활발한 연구가 진행되고 있다. 그중에서도 특히 타이타늄실리사이드는 게이트전극으로서 낮은 비저항, 높은 용융점, 박막 형성의 용이성, 라인패턴(line pattern) 형성의 용이성, 및 열적 안정성 등의 요구특성을 지니고 있는 것으로 알려져 있다.Recently, as the degree of integration of semiconductor memory devices has increased rapidly, corresponding line widths of gate electrodes (word lines) have been rapidly reduced accordingly. As a result, polysilicon such as polysilicon or tungsten silicide (WSi 2 ) / polysilicon, which is used as a conventional gate electrode material, cannot realize the low resistance value required for highly integrated semiconductor devices over a fine line width. Therefore, in recent years, active research is being conducted on the formation of gate electrodes using silicide-based materials such as titanium silicide (TiSi 2 ), CoSi 2 , and NiSi 2 . Among them, titanium silicide, in particular, is known to have required characteristics such as low resistivity, high melting point, ease of thin film formation, ease of line pattern formation, and thermal stability as a gate electrode.
그리고 종래에는 게이트 전극과 소스/드레인 지역에서 동시에 자기정합(Self-Aligned) 방법을 이용하여 타이타늄실리사이드를 형성하는 것이 일반적 연구방향이었으나, 실제 메모리소자에서는 설계 및 공정상의 제약으로 인해서 게이트 전극에만 타이타늄 실리사이드를 적용하는 방향으로 기술개발이 추진되고 있다.In the past, it was a general research direction to form titanium silicide by using a self-aligned method in the gate electrode and the source / drain region at the same time. Technological development is being promoted in the direction of applying.
도1a 내지 도f에는 종래기술에 따른 타이타늄실리사이드를 이용한 폴리사이드 게이트 형성 방법이 도시되어 있다.1A-F illustrate a method of forming a polyside gate using titanium silicide according to the prior art.
먼저, 도1a는 반도체기판(1) 위에 게이트산화막(Gate Oxide)(2), 폴리실리콘막(3), 타이타늄(Ti)(4)을 순차적으로 형성한 상태이고, 도1b는 급속열처리(RTP : Rapid Thermal Process) 공정을 통해 열처리를 실시하여 증착된 타이타늄(4)과 폴리실리콘막(3) 간에 상호반응을 유도하여 낮은 비저항의 타이타늄실리사이드막(TiSi2)(5)을 형성시킨 상태이다.First, FIG. 1A is a state in which a gate oxide film 2, a polysilicon film 3, and titanium 4 are sequentially formed on a semiconductor substrate 1, and FIG. 1B shows rapid thermal processing (RTP). : Induced mutual reaction between the deposited titanium (4) and the polysilicon film (3) by a heat treatment through a Rapid Thermal Process (Ti) process to form a low resistivity titanium silicide film (TiSi 2 ) (5).
이어서, 도1c는 이후의 스페이서 형성을 위한 식각시 게이트가 손상되는 것을 방지하기 위하여 마스크산화막(Mask Oxide)(6)을 증착한 상태이고, 도1d는 마스크 및 식각 공정을 실시하여 게이트 전극을 패터닝한 상태이다.Subsequently, FIG. 1C is a state in which a mask oxide film 6 is deposited in order to prevent the gate from being damaged during the subsequent etching of the spacer. FIG. 1D is a mask and etching process to pattern the gate electrode. It is a state.
이어서, 도1e에는 식각공정에서 유발된 반도체기판(1)의 손상(damage)을 회복시키고, 또한 후속 소스/드레인(Soure/Drain) 이온주입으로 인해 반도체기판(1)이 손상되는 것을 방지하기 위하여 반도체기판(1)위에 스크린산화막(Screen Oxide)(7)을 형성시킨 상태가 도시되어 있다. 그리고, 도1f는 낮은 농도의 이온주입을 실시하여 LDD(Lightly Doped Drain) 소스/드레인(8)을 형성시킨 상태이다. 이후 게이트 측벽에 절연막스페이서를 형성하고 고농도 이온주입을 실시하여 MOSFET을 완성하게 된다.Subsequently, in FIG. 1E, in order to recover damage of the semiconductor substrate 1 caused by the etching process and to prevent damage to the semiconductor substrate 1 due to subsequent source / drain ion implantation. A state in which a screen oxide film 7 is formed on the semiconductor substrate 1 is shown. 1F is a state in which a lightly doped drain (LDD) source / drain 8 is formed by performing ion implantation at a low concentration. After that, an insulating film spacer is formed on the sidewall of the gate, and high concentration ion implantation is performed to complete the MOSFET.
한편, 이상에서 설명한 바와 같은 종래기술은 아래와 같은 문제점을 갖게되는바, 이를 도2 및 도3을 참조하여 살펴본다. 도1과 동일한 박막에 대하여 동일한 도면부호를 부여하였다.On the other hand, the prior art as described above has the following problems, it looks at with reference to Figures 2 and 3. The same reference numerals are given to the same thin films as in FIG.
먼저, 도2에는 RTP 공정을 실시하여 폴리실리콘(3)과 타이타늄(4) 간의 상호반응을 유도하여 타이타늄실리사이드(5)를 형성시킬 때 발생하는 문제점이 도시되어 있다. 폴리실리콘(3)은 근본적으로 입계(Grain Boundary)와 결정립(Grain)으로 구성되는 박막이며, 타이타늄(4)과 상호반응하여 타이타늄실리사이드(5)를 형성시키는 과정에 있어서 그 입계와 결정립에서의 반응속도 차이가 존재하므로 최종적으로, 도2에 도시된 바와 같이, 폴리실리콘(3)과 타이타늄실리사이드(5)의 계면(20)이 매우 불균일하게 형성된다. 그 결과 도1d의 공정단계에서 폴리실리콘(3)/타이타늄실리사이드(5) 복합층에 대한 식각공정을 실시할 때 전체기판에서 각 부분마다 식각해야 할 폴리실리콘(3)/타이타늄 실리사이드(5) 두께비율이 달라지게 된다. 따라서 정확한 식각공정 조건을 확립하기 어렵고, 심한 경우에는 소스/드레인(8) 지역에서 식각 이후에 핀홀(pin hole)이 생길 수도 있다. 또한 폴리실리콘(3)/타이타늄실리사이드(5) 계면(20)의 거칠기가 심해지면 기판의 각부분에서의 저항값이 서로 차이가 나게 되어서 최종적으로 신뢰성있는 메모리소자로의 응용이 불가능해진다.First, FIG. 2 illustrates a problem that occurs when the titanium silicide 5 is formed by inducing an interaction between the polysilicon 3 and the titanium 4 by performing the RTP process. Polysilicon (3) is a thin film consisting essentially of grain boundaries and grains, the reaction at the grain boundaries and grains in the process of forming titanium silicide (5) by interacting with the titanium (4) Finally, as there is a speed difference, as shown in Fig. 2, the interface 20 of the polysilicon 3 and the titanium silicide 5 is very nonuniformly formed. As a result, when the polysilicon (3) / titanium silicide (5) composite layer is etched in the process step of FIG. The ratio will be different. Therefore, it is difficult to establish accurate etching process conditions, and in severe cases, pinholes may occur after etching in the source / drain (8) region. In addition, when the roughness of the polysilicon (3) / titanium silicide (5) interface 20 becomes severe, the resistance values at each part of the substrate are different from each other, thereby making it impossible to finally apply a reliable memory device.
도3에는 도1e의 공정단계인 스크린산화막(7) 형성을 위한 산화공정에서 반도체기판(1)뿐만 아니라 타이타늄실리사이드(5)의 측벽에서도 산화 현상이 발생하는 문제점을 도시하고 있다. 즉, 게이트의 측벽에 노출되어 있는 타이타늄실리사이드(5)가 이상산화되어 상대적으로 두껍고 불균일한 타이타늄산화물층(TiO2)(30)이 생성된다. 그 결과 이 타이타늄산화물층(TiO2)(30)이 후속공정인 소스/드레인 이온주입에 대한 장애물로 작용하게 되어 균일한 구조의 소스/드레인(8) 형성을 방해하게 된다.FIG. 3 illustrates a problem that oxidation occurs not only on the semiconductor substrate 1 but also on the sidewalls of the titanium silicide 5 in the oxidation process for forming the screen oxide film 7 of FIG. 1E. That is, the titanium silicide 5 exposed on the sidewall of the gate is abnormally oxidized to form a relatively thick and non-uniform titanium oxide layer (TiO 2 ) 30. As a result, the titanium oxide layer (TiO 2 ) 30 acts as an obstacle to subsequent source / drain ion implantation, thereby preventing formation of the source / drain 8 having a uniform structure.
본 발명은 상기 문제점을 해결하기 위하여 안출된 것으로써, 실리사이드막이 이상산화(Abnormal Oxidation)되는 것과 실리사이드와 폴리실리콘의 계면특성 저하를 방지하여, 안정한 폴리사이드 게이트를 이루는 MOSFET 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a MOSFET manufacturing method for forming a stable polyside gate by preventing the silicide film from being abnormally oxidized and reducing the interfacial properties of the silicide and polysilicon. There is this.
도1a 내지 도1f는 종래기술에 따른 폴리사이드 게이트 형성 방법을 나타내는 공정 단면도.1A to 1F are cross-sectional views showing a method for forming a polyside gate according to the prior art.
도2 및 도3은 종래기술의 문제점을 나타내는 단면도.2 and 3 are cross-sectional views showing problems of the prior art.
도4a 내지 도4k는 본 발명의 일실시예에 따른 폴리사이드 게이트를 갖는 MOSFET 제조방법을 나타내는 공정 단면도.4A-4K are cross-sectional views illustrating a method of fabricating a MOSFET having a polyside gate according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체기판 2 : 게이트산화막1 semiconductor substrate 2 gate oxide film
3 : 폴리실리콘막 5 : 타이타늄실리사이드막3: polysilicon film 5: titanium silicide film
6 : 마스크산화막 7 : 스크린산화막6 mask oxide film 7 screen oxide film
8 : LDD 소스/드레인 9 : 산화막스페이서8: LDD source / drain 9: oxide spacer
10 : IPO 절연막 40 : 요부10: IPO insulating film 40: main part
상기 목적을 달성하기 위한 본 발명은, 반도체소자 제조방법에 있어서, 반도체기판 상에 게이트절연막, 폴리실리콘막을 순차적으로 형성하는 제1단계; 게이트 마스크 및 식각공정을 실시하여 상기 반도체기판 상에 증착된 박막들을 패터닝하는 제2단계; 열산화 공정을 실시하여 반도체기판에 스크린산화막을 성장시키는 제3단계; 상기 반도체기판에 소스/드레인을 형성하는 제4단계; 층간절연막을 증착하고 상기 폴리실리콘막 표면이 노출되도록 기판전면을 화학적기계적연마하는 제5단계; 상기 노출된 폴리실리콘막을 일부두께 식각하여 요부를 형성하는 제6단계; 및 상기 요부내에 금속실리사이드막을 증착하는 제7단계를 포함하여 이루어진다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method comprising: sequentially forming a gate insulating film and a polysilicon film on a semiconductor substrate; A second step of patterning thin films deposited on the semiconductor substrate by performing a gate mask and an etching process; Performing a thermal oxidation process to grow a screen oxide film on the semiconductor substrate; Forming a source / drain on the semiconductor substrate; Depositing an interlayer dielectric layer and chemical mechanical polishing the entire surface of the substrate to expose the surface of the polysilicon layer; A sixth step of etching a portion of the exposed polysilicon film to form recesses; And a seventh step of depositing a metal silicide film in the recess.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
도4a 내지 도4k는 본 발명의 일실시예에 따른 폴리사이드 게이트를 갖는 MOSFET 제조방법을 나타내는 공정 단면도이다. 종래와 동일한 구성요소에 대해서는 동일한 도면부호를 인용하였다.4A to 4K are cross-sectional views illustrating a method of fabricating a MOSFET having a polyside gate according to an exemplary embodiment of the present invention. Like reference numerals refer to like elements.
먼저, 도4a와 같이, 반도체기판(1) 위에 게이트산화막(2)을 성장시킨 후, LPCVD(Low Pressure Chemical Vapor Deposition)방법으로 낮은 비저항의 폴리실리콘막(3)을 1000∼2000Å 증착한다.First, as shown in FIG. 4A, the gate oxide film 2 is grown on the semiconductor substrate 1, and then a low resistivity polysilicon film 3 is deposited by LPCVD (Low Pressure Chemical Vapor Deposition) method.
이후, 도4b와 같이, 이후의 식각 또는 이온주입 공정에서 게이트 표면이 손상받는 것을 방지하기 위하여 마스크산화막(6)을 900∼1200Å 증착하는데, 이 공정은 생략하여도 약간의 특성 변화만이 존재할뿐 본 발명의 목적 달성에는 영향을 주지 않는다.Then, as shown in Figure 4b, in order to prevent the gate surface is damaged in the subsequent etching or ion implantation process, the mask oxide film 6 is deposited 900 ~ 1200Å, this step is omitted, but only a slight characteristic change is present It does not affect the achievement of the object of the present invention.
계속해서, 도4c에 도시된 바와 같이, 게이트 마스크 및 식각 공정을 실시하여 증착된 박막들을 패터닝한다.Subsequently, as illustrated in FIG. 4C, a gate mask and an etching process are performed to pattern the deposited thin films.
이어서, 도4d에 도시된 바와 같이, 열산화 공정을 실시하여 반도체기판(1)에 40∼100Å의 스크린산화막(7)을 형성하는데, 바람직하게 열산화는 750∼850℃에서 실시한다. 여기서, 폴리실리콘 게이트만이 형성되어 있으므로 그 전극 측벽에서 이상산화 현상은 발생하지 않는다. 따라서 이후 이온주입 공정에 의한 정상적인 LDD 구조의 소스/드레인을 형성시킬 수 있다.Subsequently, as shown in FIG. 4D, a thermal oxidation process is performed to form a screen oxide film 7 of 40 to 100 Pa on the semiconductor substrate 1, preferably thermal oxidation is performed at 750 to 850 캜. Here, since only the polysilicon gate is formed, no abnormal oxidation occurs on the sidewall of the electrode. Therefore, a source / drain of a normal LDD structure may be formed by an ion implantation process.
이어서, 도4e는 저농도의 이온주입 공정으로 LDD 소스/드레인(8)을 형성한 상태이고, 도4f는 스페이서용 산화막을 91200Å 증착하고, 식각을 실시하여 산화막스페이서(9)를 형성한 다음, 다시 상대적으로 고농도의 이온주입을 실시하여 최종적인 소스/드레인(8)을 완성한 상태이다.4E shows a state in which the LDD source / drain 8 is formed by a low concentration ion implantation process, and FIG. 4F shows that an oxide film for spacers is deposited by 91200 kPa, followed by etching to form an oxide film spacer 9. The final source / drain 8 is completed by relatively high concentration of ion implantation.
계속해서, 도4g와 같이, IPO(Inter Poly Oxide) 절연막(10)을 1200∼2500Å 증착하고, 도4h와 같이, 기판전체구조 상부를 CMP(Chemical Mechanical Polishing) 또는 에치백하여 폴리실리콘막(3)의 표면을 노출시킨다.Subsequently, as shown in FIG. 4G, the IPO (Inter Poly Oxide) insulating film 10 is deposited at 1200 to 2500 GPa, and as shown in FIG. 4H, the upper surface of the entire substrate structure is CMP (Chemical Mechanical Polishing) or etched back to form a polysilicon film 3 ) Surface.
이어서, 도4i와 같이, 건식 또는 습식식각을 실시하여 폴리실리콘막(3)을 최초 증착 두께의 반(1/2) 정도를 선택적으로 식각하여 요부(40)를 형성한다.Next, as shown in FIG. 4I, dry or wet etching is performed to selectively etch the polysilicon film 3 to about half of the initial deposition thickness to form the recess 40.
이어서, 도4j와 같이, 물리적(PVD) 또는 화학적(CVD) 증착법을 이용하여 타이타늄실리사이드층(TiSi2)(5)을 500∼1000Å 증착한다. 여기서 타이타늄실리사이드(5) 대신에 코발트실리사이드(CoSi2), 니켈실리사이드(NiSi)등의 실리사이드계 물질을 증착할수도 있다. 이어서, 질소 분위기하에서 RTP(Rapid Thermal Process) 공정을 800∼850℃ 온도에서 10∼30초동안 실시하여, 증착된 타이타늄실리사이드(5)를 비저항이 작은 C54상으로 완전히 전이시킨다.Subsequently, as shown in FIG. 4J, the titanium silicide layer (TiSi 2 ) 5 is deposited by 500 to 1000 Pa using physical (PVD) or chemical (CVD) deposition. Here, instead of the titanium silicide 5, silicide-based materials such as cobalt silicide (CoSi 2 ) and nickel silicide (NiSi) may be deposited. Subsequently, a rapid thermal process (RTP) process is carried out in a nitrogen atmosphere at a temperature of 800 to 850 ° C. for 10 to 30 seconds to completely transfer the deposited titanium silicide 5 onto the C54 phase having a low specific resistance.
여기서, 종래에는 폴리실리콘막(3)과 타이타늄막(4)간의 상호반응을 통하여 타이타늄실리사이드(5)를 형성하였으나, 이와 달리 본 발명은 물리적 또는 화학적 증착법으로 타이타늄실리사이드를 증착하므로 종래의 방법보다 폴리실리콘과 타이타늄실리사이드 간의 계면 거칠기가 매우 양호하게 나타난다. 따라서 이후 제조되는 트랜지스터 특성의 신뢰성을 향상시킬 수 있다.Here, in the prior art, the titanium silicide 5 was formed through the mutual reaction between the polysilicon film 3 and the titanium film 4, whereas the present invention deposits titanium silicide by physical or chemical vapor deposition. The interface roughness between silicon and titanium silicide is very good. Therefore, it is possible to improve the reliability of the transistor characteristics to be manufactured later.
끝으로, 도4k에 도시된 바와 같이, 타이타늄실리사이드(5)를 CMP 처리하여 요부(40)내에만 타이타늄실리사이드(5)가 형성되도록하여 최종적인 폴리실리콘/타이타늄실리사이드의 폴리사이드 게이트를 완성한다. 또한 타이타늄실리사이드(5)를 식각함에 있어서 CMP 공정 대신에 건식 또는 습식식각 등의 에치백(Etch Back) 기술을 이용할 수도 있다.Finally, as shown in FIG. 4K, the titanium silicide 5 is subjected to CMP treatment so that the titanium silicide 5 is formed only in the recess 40 to complete the polysilicon gate of the polysilicon / titanium silicide. In addition, in etching the titanium silicide 5, an etching back technique such as dry or wet etching may be used instead of the CMP process.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명은 스크린산화막을 형성하기 위한 산화공정시 발생하는 실리사이드의 이상산화 현상을 효과적으로 방지할 수 있고, 또한 폴리실리콘과 실리사이드 계면을 안정적으로 유지할 수 있어서, MOSFET의 특성을 개선하게 되므로 고집적화된 반도체소자의 구현을 가능하게 하는 효과를 가지게 된다.The present invention can effectively prevent the abnormal oxidation of silicide generated during the oxidation process for forming the screen oxide film, and also can stably maintain the polysilicon and silicide interface, thereby improving the characteristics of the MOSFET and thus highly integrated semiconductor devices. Will have the effect of enabling.
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