KR100318260B1 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR100318260B1 KR100318260B1 KR1019980059961A KR19980059961A KR100318260B1 KR 100318260 B1 KR100318260 B1 KR 100318260B1 KR 1019980059961 A KR1019980059961 A KR 1019980059961A KR 19980059961 A KR19980059961 A KR 19980059961A KR 100318260 B1 KR100318260 B1 KR 100318260B1
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- film
- tisi
- amorphous silicon
- gate electrode
- gate oxide
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 229910008484 TiSi Inorganic materials 0.000 claims abstract description 48
- 238000000034 method Methods 0.000 claims abstract description 39
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 36
- 229920005591 polysilicon Polymers 0.000 claims abstract description 36
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 28
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 17
- 239000010936 titanium Substances 0.000 claims abstract description 17
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 17
- 238000010438 heat treatment Methods 0.000 claims abstract description 14
- 238000000151 deposition Methods 0.000 claims abstract description 11
- 239000012535 impurity Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 238000005468 ion implantation Methods 0.000 claims description 7
- 239000011229 interlayer Substances 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 3
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000002776 aggregation Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005054 agglomeration Methods 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는, 티타늄 폴리사이드 구조의 게이트 전극을 형성함에 있어서의 TiSi2막과 폴리실리콘막간의 계면 거칠기를 낮출 수 있는 반도체 소자의 제조방법에 관한 것이다. 본 발명의 반도체 소자의 제조방법은, 반도체 기판 상에 게이트 산화막을 형성하고, 상기 게이트 산화막 상에 비도핑된 비정질 실리콘막을 증착하는 단계; 상기 비도핑된 비정질 실리콘막에 불순물을 이온주입하는 단계; 상기 불순물이 이온주입된 비정질 실리콘막 상에 TiSix막을 증착하는 단계; 열처리 공정을 수행하여 상기 TiSix막을 TiSi2막으로 상변화시킴과 동시에 상기 비정질 실리콘막을 결정질의 폴리실리콘막으로 상변화시키는 단계; 상기 TiSi2막 상에 절연막을 증착하는 단계; 상기 절연막, TiSi2막, 폴리실리콘막, 및 게이트 산화막을 패터닝하여 절연막 패턴 및 티타늄 폴리사이드 구조의 게이트 전극을 형성하는 단계를 포함한다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of lowering the interface roughness between a TiSi 2 film and a polysilicon film in forming a gate electrode having a titanium polyside structure. will be. A method of manufacturing a semiconductor device of the present invention includes forming a gate oxide film on a semiconductor substrate and depositing an undoped amorphous silicon film on the gate oxide film; Implanting impurities into the undoped amorphous silicon film; Depositing a TiSi x film on the amorphous silicon film implanted with the impurities; Performing a heat treatment process to change the TiSi x film into a TiSi 2 film and to simultaneously change the amorphous silicon film into a crystalline polysilicon film; Depositing an insulating film on the TiSi 2 film; Patterning the insulating film, the TiSi 2 film, the polysilicon film, and the gate oxide film to form a gate electrode having an insulating film pattern and a titanium polyside structure.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는, 티타늄폴리사이드 구조의 게이트 전극을 형성함에 있어서의 TiSi2막과 폴리실리콘막간의 계면 거칠기를 낮출 수 있는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of lowering the interface roughness between a TiSi 2 film and a polysilicon film in forming a gate electrode having a titanium polyside structure. will be.
모스팻(MOSFET)의 게이트 전극은 주로 폴리실리콘막, 또는, 폴리실리콘막과 텅스텐 실리사이드막(WSi2)의 적층 구조로 형성되어져 왔다. 그런데, 반도체 소자의 집적도가 증가함에 따라 게이트 전극의 선폭이 급격히 감소됨으로써, 상기한 전극 재질로는 고집적 소자에서 요구되는 낮은 저항 값을 만족시킬 수 없었다. 이에 따라, 최근에는 폴리실리콘막 상에 TiSi2막을 증착하여 TiSi2막/폴리실리콘막(이하, 티타늄 폴리사이드) 구조로 게이트 전극을 형성하는 연구가 진행되고 있다.The gate electrode of the MOSFET has been formed mainly of a polysilicon film or a laminated structure of a polysilicon film and a tungsten silicide film WSi 2 . However, as the degree of integration of semiconductor devices increases, the line width of the gate electrode decreases rapidly, and thus the electrode material cannot satisfy the low resistance value required for the high integration device. Accordingly, in recent years, a study for forming a gate electrode as a TiSi 2 film / polysilicon film (hereinafter referred to as titanium polycide) structure proceeds to TiSi 2 film is deposited on the polysilicon film.
도 1a 내지 도 1d는 종래 기술에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도로서, 이를 설명하면 다음과 같다.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art, which will be described below.
우선, 도 1a에 도시된 바와 같이, 반도체 기판(1) 상에 게이트 산화막(2)을 형성하고, 상기 게이트 산화막(2) 상에 인(P) 또는 비소(As) 등으로 도핑된 폴리실리콘막(3)을 증착한다. 그런 다음, TiSix타켓을 이용한 물리적기상증착(Physical Vapor Deposition : 이하, PVD)법으로 폴리실리콘막(3) 상에 TiSix막(4)을 증착한다. 이 때, TiSix막(4)은 비정질 상태이다.First, as shown in FIG. 1A, a gate oxide film 2 is formed on a semiconductor substrate 1, and a polysilicon film doped with phosphorus (P), arsenic (As), or the like is formed on the gate oxide film 2. (3) is deposited. Then, TiSi x a physical vapor deposition using a target: to deposit a (Physical Vapor Deposition or less, PVD) method of a polysilicon film (3), TiSi x film 4 on. At this time, the TiSi x film 4 is in an amorphous state.
이어서, 도 1b에 도시된 바와 같이, 수 초 동안 급속열처리(Rapid Thermal Annealing) 공정을 수행하여 비정질 상태인 TiSix막을 결정질의 TiSi2막(5)으로 상변화시킨다.Subsequently, as shown in FIG. 1B, a rapid thermal annealing process is performed for several seconds to change the amorphous TiSi x film into a crystalline TiSi 2 film 5.
다음으로, 도 1c에 도시된 바와 같이, 자기정렬콘택(Self Aligned Contact) 등의 후속 공정을 위해, TiSi2막(5) 상에 산화막 또는 질화막으로된 절연막을 증착하고, 상기 절연막과, TiSi2막(5), 폴리실리콘막(3) 및 게이트 산화막(2)을 패터닝하여, 절연막 패턴(6) 및 티타늄 폴리사이드 구조의 게이트 전극(10)을 형성한다.Next, as shown in FIG. 1C, an insulating film made of an oxide film or a nitride film is deposited on the TiSi 2 film 5 for a subsequent process such as a self aligned contact, and the like, and the TiSi 2 The film 5, the polysilicon film 3 and the gate oxide film 2 are patterned to form the insulating film pattern 6 and the gate electrode 10 of the titanium polyside structure.
그리고 나서, 도 1d에 도시된 바와 같이, 게이트 전극(10)과 절연막 패턴(6)이 적층된 구조의 측벽에 스페이서(7)를 형성하고, 게이트 전극을 마스크로하는 이온주입 공정을 수행하여 반도체 기판의 표면에 소오스/드레인 영역(8)을 형성한 후, 전체 상부에 층간절연막(9)을 증착한다.Then, as illustrated in FIG. 1D, a spacer 7 is formed on sidewalls of the structure in which the gate electrode 10 and the insulating film pattern 6 are stacked, and an ion implantation process using the gate electrode as a mask is performed to perform semiconductors. After the source / drain regions 8 are formed on the surface of the substrate, the interlayer insulating film 9 is deposited over the whole.
이후, 도시하지는 않았으나, 공지된 후속 공정을 수행하여 반도체 소자를 완성한다.Subsequently, although not shown, the semiconductor device is completed by performing a known subsequent process.
그러나, 전술한 바와 같은 종래 기술에 따른 반도체 소자의 제조방법은, 티타늄 폴리사이드 구조의 게이트 전극을 형성한 후, 그 후속하는 공정, 예컨대, 소오스/드레인 영역과 층간절연막의 형성시에 수반되는 열공정에 의해서 TiSi2막과 폴리실리콘막간의 계면 거칠기(Interface Roughness)가 증가되는 현상이 발생되어, 결과적으로, 티타늄 폴리사이드 구조의 게이트 전극의 신뢰성이 저하되며, 아울러, 게이트 산화막의 신뢰성이 저하되는 문제점이 있다.However, the method of manufacturing a semiconductor device according to the prior art as described above, after forming the gate electrode of the titanium polyside structure, the subsequent process, for example, the heat involved in the formation of the source / drain region and the interlayer insulating film The surface roughness between the TiSi 2 film and the polysilicon film is increased by the process, and as a result, the reliability of the gate electrode of the titanium polyside structure is lowered, and the reliability of the gate oxide film is lowered. There is a problem.
자세하게, 소오스/드레인 영역을 형성하기 위한 공정에서는 불순물을 이온주입한 후, 이온주입된 불순물을 활성화시키기 위하여 열처리 공정이 수행하고 있으며, 또한, 층간절연막을 증착한 후에도 그의 표면 평탄화를 얻기 위해 열처리 공정을 수행하고 있다.In detail, in the process for forming the source / drain regions, after the ion implantation of impurities, a heat treatment process is performed to activate the ion implanted impurities, and a heat treatment process for obtaining the surface planarization even after depositing the interlayer insulating film. Is doing.
그런데, 상기한 열 공정이 수행되는 동안, TiSi2막의 응집(Agglomeration) 현상에 기인하여 발생된 스트레스에 의해 TiSi2막과 폴리실리콘막간의 계면을 통하여 물질 이동이 일어나는 바, 상기 TiSi2막과 폴리실리콘막간의 반응이 진행되며, 이에 따라, 그들간의 계면 거칠기가 증가되고, 결국, 게이트 전극의 특성이 안정적이지 못하게 된다.By the way, the heat for the process is carried out, TiSi 2 film aggregation (Agglomeration) by a stress generated due to the phenomenon TiSi 2 mass transfer occurs bar through the interface of the film and the polysilicon interlude, the TiSi 2 film and the poly The reaction between the silicon films proceeds, thereby increasing the interface roughness therebetween, resulting in unstable characteristics of the gate electrode.
또한, TiSi2막과 폴리실리콘막간의 계면 거칠기가 매우 심한 경우에는 TiSi2막이 게이트 산화막과 접촉하게 됨으로써, 상기 게이트 산화막의 특성 열화도 초래된다.In addition, when the interfacial roughness between the TiSi 2 film and the polysilicon film is very severe, the TiSi 2 film is brought into contact with the gate oxide film, thereby deteriorating the characteristics of the gate oxide film.
게다가, 티타늄 폴리사이드 구조의 게이트 전극을 형성하기 위하여, 종래에는 결정립 크기(Grain Size)가 매우 큰 주상 구조(Columnar Structure)의 폴리실리콘막을 사용하고 있는데, 이 경우에는 TiSi2막과 폴리실리콘막간의 계면 거칠기가 더욱 증가하게 된다. 즉, 폴리실리콘 결정립(Grain)들간에는 입계(Grain Boundary)가 존재하고, 이러한 입계에서의 물질 이동이 결정립들간의 물질 이동 보다 크고, 아울러, TiSi2막과의 반응이 입계에서 더욱 용이하기 때문에 TiSi2막과 폴리실리콘막간의 계면 거칠기가 더욱 증가된다.In addition, in order to form a gate electrode having a titanium polyside structure, a polysilicon film having a columnar structure having a very large grain size is conventionally used. In this case, between the TiSi 2 film and the polysilicon film, The interface roughness is further increased. In other words, there is a grain boundary between the polysilicon grains (Grain), the mass movement at these grain boundaries is larger than the mass movement between the grains, and TiSi 2 because the reaction with the TiSi 2 film is easier at the grain boundaries 2 The interface roughness between the film and the polysilicon film is further increased.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로서,TiSi2막과 폴리실리콘막간의 계면 거칠기가 증가되는 것을 방지할 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device capable of preventing an increase in the interfacial roughness between a TiSi 2 film and a polysilicon film.
도 1a 내지 도 1d는 종래 기술에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도.2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
11 : 반도체 기판 12 : 게이트 산화막11 semiconductor substrate 12 gate oxide film
13 : 비정질 실리콘막 13a : 폴리실리콘막13: amorphous silicon film 13a: polysilicon film
14 : TiSix막 14a : TiSi2막14: TiSi x film 14a: TiSi 2 film
15 : 절연막 패턴 16 : 스페이서15 insulating film pattern 16 spacer
17 : 소오스/드레인 영역 18 : 층간절연막17 source / drain region 18 interlayer insulating film
20 : 게이트 전극20: gate electrode
상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 제조방법은, 반도체 기판 상에 게이트 산화막을 형성하고, 상기 게이트 산화막 상에 비도핑된 비정질 실리콘막을 증착하는 단계; 상기 비도핑된 비정질 실리콘막에 불순물을 이온주입하는 단계; 상기 불순물이 이온주입된 비정질 실리콘막 상에 TiSix막을 증착하는 단계; 열처리 공정을 수행하여 상기 TiSix막을 TiSi2막으로 상변화시킴과 동시에 상기 비정질 실리콘막을 결정질의 폴리실리콘막으로 상변화시키는 단계; 상기 TiSi2막 상에 절연막을 증착하는 단계; 상기 절연막, TiSi2막, 폴리실리콘막, 및 게이트 산화막을 패터닝하여 절연막 패턴 및 티타늄 폴리사이드 구조의 게이트 전극을 형성하는 단계를 포함한다.A method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of forming a gate oxide film on a semiconductor substrate, and depositing an undoped amorphous silicon film on the gate oxide film; Implanting impurities into the undoped amorphous silicon film; Depositing a TiSi x film on the amorphous silicon film implanted with the impurities; Performing a heat treatment process to change the TiSi x film into a TiSi 2 film and to simultaneously change the amorphous silicon film into a crystalline polysilicon film; Depositing an insulating film on the TiSi 2 film; Patterning the insulating film, the TiSi 2 film, the polysilicon film, and the gate oxide film to form a gate electrode having an insulating film pattern and a titanium polyside structure.
본 발명에 따르면, 폴리실리콘막 대신에 비정질 실리콘막을 이용하고, 이후에, 상기한 비정질 실리콘막에 불순물을 도핑시킴과 동시에 열공정시에 비정질 실리콘막이 폴리실리콘막으로 상변화되도록 함으로써, 후속의 열공정에 의해 TiSi2막과 폴리실리콘막간의 계면 거칠기가 증가되는 것을 방지할 수 있다.According to the present invention, an amorphous silicon film is used instead of a polysilicon film, and then, the doping of the above-mentioned amorphous silicon film is carried out, and at the same time the phase of the amorphous silicon film is changed to a polysilicon film during the thermal process, thereby performing a subsequent thermal process. This can prevent an increase in the interface roughness between the TiSi 2 film and the polysilicon film.
(실시예)(Example)
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도이다.2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
먼저, 도 2a에 도시된 바와 같이, 반도체 기판(11)의 표면 상에 열산화 공정을 통해 게이트 산화막(12)을 형성하고, 그런다음, 상기 게이트 산화막(12) 상에 도핑되지 않은 비정질 실리콘막(13)을 500∼1,500Å 두께로 증착한다.First, as shown in FIG. 2A, a gate oxide film 12 is formed on the surface of the semiconductor substrate 11 through a thermal oxidation process, and then an undoped amorphous silicon film is formed on the gate oxide film 12. (13) is deposited to a thickness of 500 to 1500 mW.
이어서, 도 2b에 도시된 바와 같이, 상기 비정질 실리콘막(13)에 n형 또는 p형의 불순물을 이온주입한다. 이때, 이온주입 농도는 1014∼1016ions/㎠ 정도로 하며, 특히, 이온주입 에너지는 투사 범위(Projected Range)를 비정질 실리콘막의 중심부에 맞추어 수행함이 바람직하다.Subsequently, as illustrated in FIG. 2B, n-type or p-type impurities are implanted into the amorphous silicon film 13. In this case, the ion implantation concentration is about 10 14 to 10 16 ions / cm 2, and in particular, the ion implantation energy is preferably performed by adjusting the projected range to the center of the amorphous silicon film.
다음으로, 도 2c에 도시된 바와 같이, 도핑된 비정질 실리콘막(13) 상에 TiSix타켓을 이용한 PVD법으로 비정질 상태인 TiSix막(14)을 증착한다. 이때, 증착 두께는 500∼1,000Å 정도로 함이 바람직하다.Next, as shown in FIG. 2C, the TiSi x film 14 in an amorphous state is deposited on the doped amorphous silicon film 13 by PVD using a TiSi x target. At this time, the deposition thickness is preferably about 500 to 1,000 Pa.
그 다음, 도 2d에 도시된 바와 같이, 700∼1,000℃ 온도에서 10∼30초 동안 급속열처리 공정을 수행하여 비정질 상태인 TiSix막을 결정질의 TiSi2막(14a)으로 상변화시킨다. 이때, 상기 급속열처리 공정이 수행되는 동안, 비정질 실리콘막도 결정화되어 폴리실리콘막(13a)으로 상변화되며, 아울러, 비정질 실리콘막에 도핑되어 있던 불순물도 활성화된다. 여기서, 비정질 실리콘막은 열처리에 의해 결정화되어 폴리실리콘막(13a)으로 상변화되기는 하지만, 열처리 시간이 매우 짧은 것에 기인하여 결정립 크기가 매우 작은 폴리실리콘막으로 상변화된다.Next, as shown in FIG. 2D, a rapid heat treatment process is performed at 700 to 1,000 ° C. for 10 to 30 seconds to change the amorphous TiSi x film into a crystalline TiSi 2 film 14a. At this time, during the rapid heat treatment process, the amorphous silicon film is also crystallized and phase-changed into the polysilicon film 13a, and the impurities doped in the amorphous silicon film are also activated. Here, the amorphous silicon film is crystallized by heat treatment and phase-changed into the polysilicon film 13a. However, the amorphous silicon film is phase-changed into a polysilicon film having a very small grain size due to the very short heat treatment time.
따라서, 급속열처리에 의해 상변화된 폴리실리콘막(13a)은 그의 결정립이 주상 구조가 아니기 때문에, 티타늄 폴리사이드 구조로 게이트 전극을 형성한 후에, 공지된 후속의 열공정이 수행되는 경우에는 결정립들간의 입계에서 물질 이동 및 TiSi2막(14a)과 폴리실리콘막(13a)간의 반응이 진행되더라도 계면 거칠기는 증가되지 않는다.Therefore, since the crystal grains of the polysilicon film 13a phase-changed by rapid heat treatment are not columnar structures, after forming the gate electrode with a titanium polyside structure, grain boundaries between the crystal grains when a subsequent known thermal process is performed The interfacial roughness does not increase even when the mass transfer and the reaction between the TiSi 2 film 14a and the polysilicon film 13a proceed.
계속해서, 도 2e에 도시된 바와 같이, TiSi2막(14a) 상에 산화막 또는 질화막으로된 절연막을 증착하고, 상기 절연막 상에 감광막 패턴(도시안됨)을 형성한 상태에서, 상기 감광막 패턴을 식각 마스크로하는 식각 공정을 통해 상기 절연막과 TiSi2막(14a)과, 폴리실리콘막(13a), 및 게이트 산화막(12)을 패터닝하여 절연막 패턴(15) 및 티타늄 폴리사이드 구조의 게이트 전극(20)을 형성한다.Subsequently, as illustrated in FIG. 2E, an insulating film made of an oxide film or a nitride film is deposited on the TiSi 2 film 14a, and the photosensitive film pattern is etched while the photosensitive film pattern (not shown) is formed on the insulating film. The insulating film, the TiSi 2 film 14a, the polysilicon film 13a, and the gate oxide film 12 are patterned through an etching process using a mask to form an insulating film pattern 15 and a gate electrode 20 having a titanium polyside structure. To form.
그리고 나서, 티타늄 폴리사이드 구조의 게이트 전극(20)과 절연막 패턴(15)이 적층된 구조물의 측벽에 스페이서(16)를 형성하고, 이어서, 게이트 전극(20) 양측의 반도체 기판(11) 부분에 소오스/드레인 영역(17)을 형성한 후, 상기 단계까지의 결과물 상에 층간절연막(18)을 형성한다.Then, the spacers 16 are formed on sidewalls of the structure in which the gate electrode 20 and the insulating film pattern 15 of the titanium polyside structure are stacked, and then the semiconductor substrate 11 portions on both sides of the gate electrode 20 are formed. After the source / drain regions 17 are formed, an interlayer insulating film 18 is formed on the resultant up to this step.
이후, 공지된 후속 공정을 수행하여 반도체 소자를 완성조한다.Thereafter, known subsequent processes are performed to complete the semiconductor device.
이상에서와 같이, 본 발명은 폴리실리콘막 대신에 비정질 실리콘막을 이용하고, 아울러, 급속열처리 공정에 의해 상기 비정질 실리콘막이 미세 결정립을 갖는폴리실리콘막으로 상변화되도록 함으로써, TiSi2막과 폴리실리콘막간의 계면 거칠기가 후속의 열공정에 의해 거칠어지는 현상을 방지할 수 있다. 이에 따라, 티타늄 폴리사이드 구조로된 게이트 전극의 특성을 향상시킬 수 있고, 아울러, 게이트 산화막의 신뢰성을 확보할 수 있다.As described above, the present invention uses an amorphous silicon film in place of the polysilicon film, and also allows the amorphous silicon film to be phase-changed into a polysilicon film having fine crystal grains by a rapid heat treatment process, thereby interposing the TiSi 2 film and the polysilicon film. The phenomenon that the interfacial roughness of is roughened by a subsequent thermal process can be prevented. As a result, the characteristics of the gate electrode having the titanium polyside structure can be improved, and the reliability of the gate oxide film can be ensured.
따라서, 티타늄 폴리사이드 구조의 게이트 전극과 게이트 산화막의 신뢰성을 확보할 수 있는 것에 기인하여, 고집적 소자의 제조에 매우 유리하게 적용시킬 수 있다.Therefore, it is possible to ensure the reliability of the gate electrode and the gate oxide film of the titanium polyside structure, which can be applied very advantageously to the production of highly integrated devices.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시 할 수 있다.In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.
Claims (7)
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