KR20000041468A - Method of forming polycide gate electrode by using silicon film of amorphous phase - Google Patents
Method of forming polycide gate electrode by using silicon film of amorphous phase Download PDFInfo
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- KR20000041468A KR20000041468A KR1019980057327A KR19980057327A KR20000041468A KR 20000041468 A KR20000041468 A KR 20000041468A KR 1019980057327 A KR1019980057327 A KR 1019980057327A KR 19980057327 A KR19980057327 A KR 19980057327A KR 20000041468 A KR20000041468 A KR 20000041468A
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- film
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- gate electrode
- polysilicon
- amorphous silicon
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- 238000000034 method Methods 0.000 title claims description 52
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title description 5
- 229910052710 silicon Inorganic materials 0.000 title description 5
- 239000010703 silicon Substances 0.000 title description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 44
- 229920005591 polysilicon Polymers 0.000 claims abstract description 44
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 14
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 229910021341 titanium silicide Inorganic materials 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims abstract description 5
- 238000010438 heat treatment Methods 0.000 claims description 11
- 238000000059 patterning Methods 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000004151 rapid thermal annealing Methods 0.000 abstract description 3
- 229920006268 silicone film Polymers 0.000 abstract 3
- 229910008484 TiSi Inorganic materials 0.000 description 23
- 239000010410 layer Substances 0.000 description 9
- 238000000151 deposition Methods 0.000 description 7
- 230000008018 melting Effects 0.000 description 7
- 238000002844 melting Methods 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- 229910052719 titanium Inorganic materials 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 230000002776 aggregation Effects 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000005054 agglomeration Methods 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000010405 reoxidation reaction Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
Abstract
Description
본 발명은 반도체 기술에 관한 것으로, 특히 모스 트랜지스터(MOSFET)의 게이트 전극 형성 공정에 관한 것이며, 더 자세히는 비정질실리콘막을 이용한 폴리사이드(polycide) 게이트 전극 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a process of forming a gate electrode of a MOSFET, and more particularly, to a method of forming a polycide gate electrode using an amorphous silicon film.
일반적으로, 모스 트랜지스터의 게이트 전극은 폴리실리콘막을 사용하여 형성하여 왔다. 그러나, 반도체 소자의 고집적화에 따라 게이트 전극을 비롯한 각종 패턴이 미세화 되고 있으며, 최근에는 0.15㎛ 선폭 이하까지 미세화가 진행되고 있다. 이에 따라, 통상적인 게이트 전극 형성시 사용되어 온 도핑된 폴리실리콘(doped polysilicon)은 그 자체의 높은 비저항 특성으로 인하여 지연 시간이 길어 빠른 동작을 요구하는 소자에 적용하기가 어려운 문제점이 있었다. 이러한 문제점은 반도체 장치의 고집적화에 따라 더욱 심각한 문제로 대두되고 있으며, 이를 개선하기 위하여 텅스텐, 티타늄 등의 고융점 금속 원소를 이용한 폴리사이드(polycide, 실리사이드(silicide)/폴리실리콘) 구조의 게이트 전극에 대한 관심이 증대되고 있다.In general, the gate electrode of the MOS transistor has been formed using a polysilicon film. However, with the higher integration of semiconductor devices, various patterns including gate electrodes have been miniaturized, and in recent years, miniaturization has been progressed to 0.15 µm or less. Accordingly, doped polysilicon, which has been used in the conventional gate electrode formation, has a problem that it is difficult to apply to devices requiring fast operation because of its high resistivity. This problem is becoming more serious due to the high integration of semiconductor devices. In order to improve this problem, a gate electrode having a polycide (silicide / polysilicon) structure using a high melting point metal element such as tungsten or titanium is improved. Attention is growing.
첨부된 도면 도 1a 내지 도 1c는 종래기술에 따른 티타늄 폴리사이드 구조의 게이트 전극 형성 공정을 도시한 것으로, 종래의 공정은 우선, 도 1a에 도시된 바와 같이 반도체 기판(10) 상에 게이트 산화막(gate oxide)(11)을 성장시킨 후, 그 상부에 도핑된 폴리실리콘막(12)을 증착한다.1A to 1C illustrate a process of forming a gate electrode having a titanium polyside structure according to the prior art, and the conventional process is first performed on a semiconductor substrate 10 as shown in FIG. 1A. After the gate oxide 11 is grown, a doped polysilicon film 12 is deposited thereon.
다음으로, 도 1b에 도시된 바와 같이 TiSix타겟(target)을 이용하여 PVD(physical vapor deposition) 방법으로 폴리실리콘막(12) 상에 TiSix막을 증착한다. 이어서, 소정 온도에서 수 초 동안 급속 열처리(RTP, Rapid Thermal Process)를 진행하여 비정질의 TiSix막을 결정질(crystalline)의 TiSi2막(13)으로 상변화(phase transformation) 시킨다.Next, as shown in FIG. 1B, a TiSi x film is deposited on the polysilicon film 12 by a physical vapor deposition (PVD) method using a TiSi x target. Subsequently, a rapid thermal process (RTP) is performed for a few seconds at a predetermined temperature to phase change the amorphous TiSi x film into a crystalline TiSi 2 film 13.
마지막으로, 도 1c는 SAC(Self-Aligned Contact) 공정 등의 후속 공정을 위해 산화막(6)(또는 질화막)을 TiSi2막(13) 상에 증착한 후, 사진 및 식각 공정을 실시하여 게이트 전극을 패터닝한 후의 상태를 도시하고 있다.Finally, FIG. 1C shows a gate electrode formed by depositing an oxide film 6 (or nitride) on a TiSi 2 film 13 for a subsequent process such as a self-aligned contact (SAC) process, and then performing a photo and etching process. The state after patterning is shown.
통상적인 반도체 소자 제조 공정에서는 게이트 전극 패터닝 후에 후속 열공정으로 게이트 재산화(gate re-oxidation) 공정, 소오스/드레인(source/drain) 형성 및 열처리 공정, 층간절연막(inter-layer dielectric) 형성 및 평탄화를 위한 열처리 공정, 캐패시터(capacitor) 형성을 위한 열처리 공정이 수반된다.In the conventional semiconductor device manufacturing process, a gate re-oxidation process, a source / drain formation and heat treatment process, an inter-layer dielectric formation and planarization are performed by a subsequent thermal process after the gate electrode patterning. A heat treatment process for the process, a heat treatment process for forming a capacitor (capacitor) is involved.
첨부된 도면 도 2는 종래기술에 따라 형성된 티타늄 폴리사이드 구조의 게이트 전극의 단면을 도시한 것으로, 상기의 후속 열공정에서 TiSi2/폴리실리콘계면(interface)의 거칠기(roughness)가 악화된 상태를 나타낸 것이다. 이처럼 계면의 거칠기가 심해지는 이유는 후속 열공정에서 TiSi2막(23)의 응집(agglomeration) 현상으로 인해 발생한 스트레스에 의해 TiSi2/폴리실리콘계면을 통한 물질 이동이 생김과 동시에 TiSi2막(23)과 폴리실리콘막(22)의 반응도 진행되기 때문이다. 심할 경우, TiSi2막(23)이 게이트 산화막(21)과 맞닿게 되는 현상까지 발생한다. 이처럼 TiSi2/폴리실리콘계면의 거칠기가 심해질수록 게이트 산화막(22)의 특성이 열화되어 소자의 신뢰성이 크게 저하된다. 미설명 도면 부호 '20'은 실리콘 기판, '24'는 마스크 산화막, '25'는 스페이서 산화막, '26'은 소오스/드레인 접합을 각각 나타낸 것이다.2 is a cross-sectional view of a gate electrode of a titanium polyside structure formed according to the prior art, and shows a state in which the roughness of the TiSi 2 / polysilicon interface is deteriorated in the subsequent thermal process. It is shown. The reason is that the surface roughness severe at the same time and TiSi 2 / poly material movement causing through the silicon interface by the stress caused by aggregation (agglomeration) developing the TiSi 2 film 23 in a subsequent thermal process TiSi 2 film (23 This is because the reaction between the polysilicon film 22 and the polysilicon film 22 proceeds. In severe cases, a phenomenon occurs in which the TiSi 2 film 23 comes into contact with the gate oxide film 21. As the roughness of the TiSi 2 / polysilicon interface increases, the characteristics of the gate oxide film 22 deteriorate, so that the reliability of the device is greatly reduced. Reference numeral 20 denotes a silicon substrate, 24 denotes a mask oxide layer, 25 denotes a spacer oxide layer, and 26 denotes a source / drain junction.
전술한 종래기술에서는 폴리사이드 구조의 게이트 전극을 형성하기 위한 폴리실리콘막이 결정립이 매우 큰 주상 구조(columnar structure)를 가지고, 이에 하나의 결정립계(grain boundary)가 TiSi2막과 게이트 산화막을 연결하는 구조를 이루기 때문에 후속 열처리 공정에 의해 결정립계를 통한 물질 이동 및 TiSi2막과 폴리실리콘막의 반응이 더욱 용이해지므로 TiSi2/폴리실리콘계면의 거칠기가 더욱 심해지는 것이다.In the above-described prior art, a polysilicon film for forming a gate electrode having a polyside structure has a columnar structure having a very large crystal grain, and one grain boundary connects the TiSi 2 film to the gate oxide film. Since the subsequent heat treatment process facilitates mass transfer through the grain boundary and the reaction between the TiSi 2 film and the polysilicon film, the roughness of the TiSi 2 / polysilicon interface becomes more severe.
이상에서는 TiSi2/폴리실리콘 구조의 폴리사이드 게이트 전극을 일례로 들어 그 문제점을 살펴보았으나, 이러한 문제점들은 비단 TiSi2/폴리실리콘 구조의 폴리사이드 게이트 전극 형성시에만 나타나는 것이 아니라, 텅스텐 등의 고융점 금속 원소를 게이트 전극에 적용하는 거의 모든 경우에 나타날 수 있는 것이다.In the above, the problems have been described by taking a polyside gate electrode having a TiSi 2 / polysilicon structure as an example, but these problems are not only seen when forming a polyside gate electrode having a TiSi 2 / polysilicon structure, but also have a high content such as tungsten. It can be seen in almost all cases where the melting point metal element is applied to the gate electrode.
본 발명은 고융점 금속의 확산에 따른 실리사이드/폴리실리콘 계면의 거칠기(roughness)를 개선할 수 있는 반도체 소자의 폴리사이드 게이트 전극 형성방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method for forming a polyside gate electrode of a semiconductor device capable of improving roughness of a silicide / polysilicon interface due to diffusion of a high melting point metal.
도 1a 내지 도 1c는 종래기술에 따른 티타늄 폴리사이드 구조의 게이트 전극 형성 공정도.1a to 1c is a gate electrode formation process of the titanium polyside structure according to the prior art.
도 2는 종래기술에 따라 형성된 티타늄 폴리사이드 구조의 게이트 전극의 단면도.2 is a cross-sectional view of a gate electrode of a titanium polyside structure formed according to the prior art.
도 3a 내지 도 3d는 본 발명의 일 실시예에 따른 폴리사이드 게이트 전극 형성 공정도.3A to 3D are process diagrams for forming a polyside gate electrode according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
40 : 실리콘 기판 41 : 게이트 산화막40: silicon substrate 41: gate oxide film
42 : 폴리실리콘막 43 : 비정질실리콘막42 polysilicon film 43 amorphous silicon film
44 : TiSi2막 45 : 마스크 산화막44: TiSi 2 film 45: mask oxide film
본 발명은 고융점 금속의 확산이 주로 폴리실리콘의 결정립계를 통해 이루어지다는데 착안하여, 폴리실리콘막과 실리사이드막 사이에 결정립과 결정립계의 구분이 없는 비정질실리콘막을 삽입하여 후속 열처리시 고융점 금속의 확산을 방지하는 기술이다.The present invention focuses on the diffusion of the high melting point metal mainly through the grain boundary of polysilicon, and the diffusion of the high melting point metal during subsequent heat treatment by inserting an amorphous silicon film having no distinction between grains and grain boundaries between the polysilicon film and the silicide film. It is a technique to prevent.
상기의 기술적 과제를 달성하기 위하여 본 발명으로부터 제공되는 특징적인 반도체 소자의 폴리사이드 게이트 전극 형성방법은, 반도체 기판 상에 게이트 절연막을 형성하는 제1 단계; 상기 게이트 절연막 상에 도핑된 폴리실리콘막을 형성하는 제2 단계; 상기 폴리실리콘막 상에 비정질실리콘막을 형성하는 제3 단계; 상기 비정질실리콘막 상에 실리사이드막을 형성하는 제4 단계; 및 상기 실리사이드막, 상기 비정질실리콘막 및 상기 폴리실리콘막을 선택 식각하여 게이트 전극을 패터닝하는 제5 단계를 포함하여 이루어진다.In order to achieve the above technical problem, a method for forming a polyside gate electrode of a characteristic semiconductor device provided by the present invention includes: a first step of forming a gate insulating film on a semiconductor substrate; Forming a doped polysilicon film on the gate insulating film; A third step of forming an amorphous silicon film on the polysilicon film; Forming a silicide film on the amorphous silicon film; And a fifth step of patterning a gate electrode by selectively etching the silicide layer, the amorphous silicon layer, and the polysilicon layer.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
첨부된 도면 도 3a 내지 도 3d는 본 발명의 일 실시예에 따른 폴리사이드 게이트 전극 형성 공정을 도시한 것으로, 이하 이를 참조하여 설명한다.3A to 3D illustrate a process of forming a polyside gate electrode according to an exemplary embodiment of the present invention, which will be described with reference to the following.
우선, 도 3a에 도시된 바와 같이 실리콘 기판(40) 상에 게이트 산화막(41)을 형성하고, 그 상부에 폴리실리콘막(42)을 증착한다. 이때, 폴리실리콘막(42)은 인-시츄(in-situ) 도핑, 이온주입법 등을 사용하여 도핑시킨다.First, as shown in FIG. 3A, a gate oxide film 41 is formed on the silicon substrate 40, and a polysilicon film 42 is deposited on the gate oxide film 41. At this time, the polysilicon film 42 is doped using in-situ doping, ion implantation, or the like.
다음으로, 도 3b에 도시된 바와 같이 폴리실리콘막(42) 상에 비정질실리콘막(43)을 50∼200Å 두께로 증착한다. 이때, 비정질실리콘막(43)의 증착은 폴리실리콘막(42)의 증착과 인-시츄로 온도만을 달리하여 증착할 수 있다. 참고적으로, 비정질실리콘의 증착 온도는 500∼580℃이며, 580℃ 이상의 온도에서는 폴리실리콘이 증착된다.Next, as shown in FIG. 3B, an amorphous silicon film 43 is deposited on the polysilicon film 42 to a thickness of 50 to 200 GPa. At this time, the deposition of the amorphous silicon film 43 may be deposited by varying only the temperature in-situ with the deposition of the polysilicon film 42. For reference, the deposition temperature of amorphous silicon is 500 to 580 ° C, and polysilicon is deposited at a temperature of 580 ° C or higher.
다음으로, 도 3c에 도시된 바와 같이 비정질실리콘막(43) 상에 비정질의 TiSix막을 증착하고, 700∼900℃ 온도에서 10∼30초 동안 RTA(Rapid Thermal Annealing) 공정을 진행하여 비정질 TiSix막을 결정질 TiSi2막(44)으로 상변화 시킨다. 이때, 비정질실리콘막(43)에서도 결정화가 진행될 수 있으나 열처리 시간이 매우 짧기 때문에 거의 비정질에 가깝거나 결정립 크기가 매우 작은 폴리실리콘막이 형성될 수 있다. 이처럼 비정질실리콘막(43)의 상(phase)이 비정질상에 가깝거나 결정립 크기가 매우 작은 다결정질상일 경우, 후속 열공정시 결정립계를 통한 고융점 금속 원소의 확산 및 TiSi2막(44)과 폴리실리콘막(42)의 반응이 진행되더라도 TiSi2막(44)과 게이트 산화막(41)이 직접 접촉하게 되는 확률이 현저히 줄어들게 된다. 한편, 이와 같이 결정화를 위하여 의도적인 열처리 공정을 수행하지 않더라도, 게이트 전극 패터닝 후의 후속 열공정에 의해 TiSix막(43)의 결정화가 이루어질 수 있다. 여기서, 후속 열공정이라 함은, 앞서 언급한 바와 같이 게이트 재산화 공정, 소오스/드레인 형성 열처리 공정, 층간절연막 평탄화를 위한 열처리 공정, 캐패시터 형성을 위한 열처리 공정 등을 말한다.Next, the process proceeds to the deposition of amorphous TiSi x film, and the temperature at 700~900 ℃ 10-30 seconds RTA (Rapid Thermal Annealing) process on the amorphous silicon film 43 as shown in Figure 3c amorphous TiSi x The film is phase changed into a crystalline TiSi 2 film 44. In this case, crystallization may proceed in the amorphous silicon film 43, but since the heat treatment time is very short, a polysilicon film that is nearly amorphous or has a very small grain size may be formed. As described above, when the phase of the amorphous silicon film 43 is a polycrystalline phase that is close to the amorphous phase or has a very small grain size, diffusion of the high melting point metal element through the grain boundary during the subsequent thermal process and the TiSi 2 film 44 and the polysilicon film Even if the reaction of (42) proceeds, the probability of direct contact between the TiSi 2 film 44 and the gate oxide film 41 is significantly reduced. On the other hand, even if the intentional heat treatment process is not performed for crystallization as described above, the TiSi x film 43 may be crystallized by a subsequent heat process after the gate electrode patterning. Here, the subsequent thermal process refers to a gate reoxidation process, a source / drain formation heat treatment process, a heat treatment process for planarization of an interlayer insulating film, a heat treatment process for capacitor formation, and the like, as mentioned above.
이후, 도 3d에 도시된 바와 같이 통상적인 SAC 공정 등의 후속 공정을 위해 마스크 산화막(45)(또는 질화막)을 증착한 후 사진 및 식각 공정을 실시하여 게이트 전극을 패터닝한다.Thereafter, as illustrated in FIG. 3D, the gate electrode is patterned by depositing a mask oxide layer 45 (or nitride layer) for a subsequent process such as a conventional SAC process and performing a photo and etching process.
본 발명의 다른 실시예는 상기 도3b에서와 같이 비정질실리콘막(43) 증착 후, 폴리실리콘막(42)에 도핑된 종류와 동일한 도전형의 도펀트를 이온주입하는 것이다. 이때 불순물 도즈(dose) 1014∼1016ions/㎠으로 하며, 이온주입 에너지는 주입된 이온들이 비정질실리콘막(43) 바로 하부에 위치하도록 조절한다. 이와 같이 이온주입 공정을 실시하는 이유는 폴리실리콘막(42)에 여분의 도펀트를 공급하기 위한 것으로, 후속 열공정에서 폴리실리콘막(42)에 도핑되어 있는 도펀트들이 도핑되지 않은 비정질실리콘막(43)으로 확산되어 소위 게이트 공핍(Gate Depletion) 현상이 발생하는 것을 방지하기 위함이다.Another embodiment of the present invention is to ion implant the dopant of the same conductivity type as the doped polysilicon layer 42 after the deposition of the amorphous silicon layer 43 as shown in FIG. At this time, the impurity dose (dose) 10 14 ~ 10 16 ions / ㎠, the ion implantation energy is adjusted so that the implanted ions are located directly below the amorphous silicon film 43. The reason for performing the ion implantation process as described above is to supply an extra dopant to the polysilicon film 42. In the subsequent thermal process, the amorphous silicon film 43 in which the dopants doped in the polysilicon film 42 are not doped is doped. This is to prevent the so-called gate depletion phenomenon from being diffused to the surface.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
예를 들어, 전술한 실시예에서는 티타늄 실리사이드/폴리실리콘 구조의 폴리사이드 게이트 전극을 형성하는 경우를 일례로 들어 설명하였으나, 본 발명은 폴리사이드 구조에 텅스텐 실리사이드와 같은 다른 실리사이드막을 채용하는 경우에도 적용할 수 있다.For example, in the above-described embodiment, a case of forming a polysilicon gate electrode having a titanium silicide / polysilicon structure has been described as an example, but the present invention is also applicable to the case where another silicide film such as tungsten silicide is employed as the polyside structure. can do.
전술한 본 발명은 게이트 전극 패터닝 후의 후속 열공정에 의해 고융점 금속 원소의 확산 및 실리사이드막과 폴리실리콘막의 반응을 방지하는 효과가 있으며, 이로 인하여 반도체 소자의 신뢰도를 향상시키는 효과를 기대할 수 있다.The present invention described above has an effect of preventing the diffusion of the high melting point metal element and the reaction of the silicide film and the polysilicon film by a subsequent thermal process after the gate electrode patterning, and thus an effect of improving the reliability of the semiconductor device can be expected.
Claims (8)
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| KR1019980057327A KR20000041468A (en) | 1998-12-22 | 1998-12-22 | Method of forming polycide gate electrode by using silicon film of amorphous phase |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040016696A (en) * | 2002-08-19 | 2004-02-25 | 삼성전자주식회사 | Method for forming electrode in semiconductor device and device thereof |
| KR100684928B1 (en) * | 2000-07-07 | 2007-02-20 | 학교법인연세대학교 | Compound semiconductor device including diffusion blocking layer of network structure and Method of manufacturing the same |
| US7439176B2 (en) | 2005-04-04 | 2008-10-21 | Samsung Electronics Co., Ltd. | Semiconductor device multilayer structure, fabrication method for the same, semiconductor device having the same, and semiconductor device fabrication method |
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1998
- 1998-12-22 KR KR1019980057327A patent/KR20000041468A/en not_active Application Discontinuation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100684928B1 (en) * | 2000-07-07 | 2007-02-20 | 학교법인연세대학교 | Compound semiconductor device including diffusion blocking layer of network structure and Method of manufacturing the same |
| KR20040016696A (en) * | 2002-08-19 | 2004-02-25 | 삼성전자주식회사 | Method for forming electrode in semiconductor device and device thereof |
| US7439176B2 (en) | 2005-04-04 | 2008-10-21 | Samsung Electronics Co., Ltd. | Semiconductor device multilayer structure, fabrication method for the same, semiconductor device having the same, and semiconductor device fabrication method |
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