JPWO2019167509A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JPWO2019167509A1 JPWO2019167509A1 JP2020502873A JP2020502873A JPWO2019167509A1 JP WO2019167509 A1 JPWO2019167509 A1 JP WO2019167509A1 JP 2020502873 A JP2020502873 A JP 2020502873A JP 2020502873 A JP2020502873 A JP 2020502873A JP WO2019167509 A1 JPWO2019167509 A1 JP WO2019167509A1
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- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
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Abstract
Description
まず、第1の実施の形態の半導体装置について図1を用いて説明する。図1は、第1の実施の形態の半導体装置の側断面図である。半導体装置10は、図1に示されるように、半導体素子11a,11bと、半導体素子11a,11bがおもて面に接合されたセラミック回路基板13(基板)と、セラミック回路基板13の裏面に接合された放熱板17とを有している。なお、このように図1に示す半導体装置10は、後述する図2における第1領域16c及び第2領域16dを含むような位置の断面図である。
第2の実施の形態では、第1の実施の形態の金属板16に対してディンプルの数を増やした場合の半導体装置について、図6を用いて説明する。図6は、第2の実施の形態の半導体装置の要部拡大側断面図である。なお、図6の半導体装置10aは、半導体装置10の金属板16以外の構成については半導体装置10と同じ構成を有している。また、同じ構成には同じ符号を付しており、それらの詳細な説明については省略する。また、図6に示す半導体装置10aは、図1で示すところの半導体装置10の左側のディンプル16a,16bの周辺を拡大して表示している。
第3の実施の形態では、第1の実施の形態の金属板16に対してディンプルが1つの場合の半導体装置について、図7を用いて説明する。図7は、第3の実施の形態の半導体装置の要部拡大側断面図である。なお、図7の半導体装置10bは、半導体装置10と同じ構成を有している。同じ構成には同じ符号を付しており、それらの詳細な説明については省略する。また、図7に示す半導体装置10bは、図1で示すところの半導体装置10の左側のディンプル16a,16bの周辺を拡大して表示している。
11a,11b 半導体素子
11a1 第3端面
12a,12b,18 はんだ
13 セラミック回路基板
14 絶縁板
14a 最外端面
15a,15b 導電パターン
15a1 第1端面
16 金属板
16a,16b,16f,16g ディンプル
16a1 最外端部
16a2,16b2 最内端部
16c 第1領域
16d 第2領域
16e 第2端面
17 放熱板
Claims (14)
- 半導体素子と、
絶縁板と前記絶縁板のおもて面に形成され、前記半導体素子が配置される導電パターンと前記絶縁板の裏面に形成され、前記導電パターンの第1端面の位置よりも外側に位置する第2端面を備え、複数の第1凹部が外周縁部の少なくとも一部に沿って裏面に形成された金属板とを有する基板と、
を有し、
側断面視で、前記第1凹部の最外端部の位置は前記導電パターンの前記第1端面の位置よりも外側に位置している、
半導体装置。 - 前記金属板の裏面に複数の第2凹部が前記複数の第1凹部の内側に前記外周縁部に沿って形成されている、
請求項1に記載の半導体装置。 - 側断面視で、前記第2凹部の最内端部は、前記第1端面よりも内側に位置している、
請求項2に記載の半導体装置。 - 側断面視で、前記第2凹部の前記最内端部が前記半導体素子の第3端面の位置よりも外側に位置している、
請求項3に記載の半導体装置。 - 前記金属板の裏面に前記第1凹部と前記第2凹部との間に、前記外周縁部に沿って複数列の凹部が形成されている、
請求項2に記載の半導体装置。 - 前記金属板の裏面に形成された前記第1凹部同士の間隔は、0.1mm以上、0.5mm以下である、
請求項1に記載の半導体装置。 - 前記第1凹部の底部から前記金属板のおもて面までは第1厚さの厚みが存在している、
請求項1に記載の半導体装置。 - 前記第1厚さは、前記金属板の厚さに対して、30%以上、95%以下である、
請求項7に記載の半導体装置。 - 前記第2凹部の底部から前記金属板のおもて面までは第2厚さの厚みが存在している、
請求項2に記載の半導体装置。 - 前記第2厚さは、前記金属板の厚さに対して、30%以上、95%以下である、
請求項9に記載の半導体装置。 - 前記複数の第1凹部が前記金属板の裏面に前記外周縁部に沿って環状に形成されている、
請求項1に記載の半導体装置。 - 前記半導体素子は、前記第1凹部が形成されている前記金属板の裏面の第1領域よりも中央側の第2領域上に対応する前記導電パターン上に配置されている、
請求項11に記載の半導体装置。 - 側断面視で、前記第1凹部の最内端部の位置は前記導電パターンの前記第1端面の位置よりも内側に位置している、
請求項1に記載の半導体装置。 - 前記基板がはんだを介して接合されている放熱板をさらに有する、
請求項1に記載の半導体装置。
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JP2021108321A (ja) * | 2019-12-27 | 2021-07-29 | 京セラ株式会社 | 印刷配線板及び印刷配線板の製造方法 |
JP7459539B2 (ja) | 2020-02-07 | 2024-04-02 | 富士電機株式会社 | 半導体装置 |
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