WO2019167509A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2019167509A1 WO2019167509A1 PCT/JP2019/002647 JP2019002647W WO2019167509A1 WO 2019167509 A1 WO2019167509 A1 WO 2019167509A1 JP 2019002647 W JP2019002647 W JP 2019002647W WO 2019167509 A1 WO2019167509 A1 WO 2019167509A1
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Definitions
- the present invention relates to a semiconductor device.
- a semiconductor device including a semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor) or a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is used as, for example, a power converter.
- a semiconductor device is a ceramic having an insulating plate and a front surface of the insulating plate together with the semiconductor element, and having a plurality of conductive patterns on which the semiconductor elements are arranged and a metal plate formed on the back surface of the insulating plate. Includes circuit board. Further, in the semiconductor device, in order to cool the heat generated by the semiconductor element during operation, the ceramic circuit board is disposed in a heat radiating portion such as a heat sink made of copper.
- the semiconductor element is heated and cooled when the ceramic circuit board and the ceramic circuit board are joined to the heat radiating portion via solder, respectively.
- the temperature of the semiconductor device changes according to its own operation, and the temperature changes in the external environment. For this reason, the ceramic circuit board is subjected to thermal stress due to the difference in thermal expansion coefficient with respect to the conductive pattern of the insulating plate and the metal plate. If the ceramic circuit board is subjected to thermal stress, the insulating plate may be broken. This leads to a decrease in the reliability of the semiconductor device.
- Patent Document 1 The dimples described in Patent Document 1 are formed on the front surface of the conductive pattern of the ceramic circuit board. Therefore, the mounting area of semiconductor elements, electronic components, wiring members, etc. is reduced, and a relatively large ceramic circuit board is required.
- the present invention has been made in view of these points, and an object thereof is to provide a semiconductor device that is compact, can relieve thermal stress, and has high reliability.
- a semiconductor element an insulating plate, and a conductive pattern formed on a front surface of the insulating plate, the conductive pattern on which the semiconductor element is disposed, and a back surface of the insulating plate, the conductive pattern And a substrate having a second end surface located outside the position of the first end surface, and a plurality of first recesses formed on the back surface along at least a part of the outer peripheral edge portion.
- a semiconductor device is provided in which the position of the outermost end portion of the first recess is located outside the position of the first end face of the conductive pattern in a side sectional view.
- a plurality of second recesses are formed on the back surface of the metal plate along the outer peripheral edge inside the plurality of first recesses.
- the innermost end portion of the second recess is located inside the first end surface in a side sectional view.
- the innermost end portion of the second recess is located outside the position of the third end face of the semiconductor element in a side sectional view.
- a plurality of rows of recesses are formed along the outer peripheral edge portion between the first recess and the second recess on the back surface of the metal plate.
- the interval between the first recesses formed on the back surface of the metal plate is 0.1 mm or more and 0.5 mm or less.
- a first thickness exists from the bottom of the first recess to the front surface of the metal plate.
- the first thickness is 30% or more and 95% or less with respect to the thickness of the metal plate.
- a second thickness exists from the bottom of the second recess to the front surface of the metal plate.
- the second thickness is 30% or more and 95% or less with respect to the thickness of the metal plate.
- the plurality of first recesses are formed in an annular shape along the outer peripheral edge on the back surface of the metal plate.
- the semiconductor element is disposed on the conductive pattern corresponding to the second region on the center side of the first region on the back surface of the metal plate in which the first recess is formed.
- the position of the innermost end portion of the first recess is located inside the position of the first end surface of the conductive pattern in a side sectional view.
- it further includes a heat radiating plate to which the substrate is joined via solder.
- it is compact, can reduce thermal stress, and can prevent a decrease in reliability of the semiconductor device.
- FIG. 1 is a side sectional view of a semiconductor device according to a first embodiment. It is a top view of the back surface of the metal plate of the ceramic circuit board of the semiconductor device of 1st Embodiment.
- FIG. 6 is an enlarged side sectional view (No. 1) of a principal part of a semiconductor device of a reference example.
- FIG. 3 is an enlarged side cross-sectional view (No. 2) of a main part of a semiconductor device of a reference example.
- 1 is an enlarged side sectional view of a main part of a semiconductor device according to a first embodiment. It is a principal part expanded side sectional view of the semiconductor device of 2nd Embodiment. It is a principal part expanded side sectional view of the semiconductor device of 3rd Embodiment.
- FIG. 1 is a sectional side view of the semiconductor device according to the first embodiment.
- the semiconductor device 10 includes semiconductor elements 11 a and 11 b, a ceramic circuit board 13 (substrate) in which the semiconductor elements 11 a and 11 b are bonded to the front surface, and a back surface of the ceramic circuit board 13. It has the heat sink 17 joined.
- the semiconductor device 10 shown in FIG. 1 is a cross-sectional view of a position including a first region 16c and a second region 16d in FIG. 2 to be described later.
- the semiconductor elements 11a and 11b include switching elements such as IGBTs and power MOSFETs, for example.
- the switching element is made of silicon or silicon carbide.
- Such semiconductor elements 11a and 11b include, for example, a drain electrode (or collector electrode) on the back surface and a gate electrode and a source electrode (or emitter electrode) on the front surface.
- the semiconductor elements 11a and 11b include diodes such as SBD (SchottkyottBarrier Diode) and FWD (Free Wheeling Diode) as necessary.
- Such semiconductor elements 11a and 11b each have a cathode electrode as a main electrode on the back surface and an anode electrode as a main electrode on the front surface. Note that the number (two) of the semiconductor elements 11a and 11b shown in FIG. 1 is an example. The number can be determined by design as appropriate without being limited to this case.
- the ceramic circuit board 13 has an insulating plate 14, conductive patterns 15 a and 15 b formed on the front surface of the insulating plate 14, and a metal plate 16 formed on the back surface of the insulating plate 14.
- the insulating plate 14 is made of a ceramic having high thermal conductivity, such as aluminum oxide, aluminum nitride, silicon nitride, and the like.
- the thickness of the insulating plate 14 is preferably 0.2 mm or more and 1.5 mm or less, and more preferably 0.25 mm or more and 1.0 mm or less.
- the conductive patterns 15a and 15b are made of a material having excellent conductivity. As such a material, for example, copper, aluminum, or an alloy containing at least one of them is used.
- the thickness of the conductive patterns 15a and 15b is preferably 0.1 mm or more and 1.0 mm or less, and more preferably 0.125 mm or more and 0.6 mm or less.
- the semiconductor elements 11a and 11b are joined to the conductive patterns 15a and 15b via the solders 12a and 12b, respectively.
- On the conductive patterns 15a and 15b in addition to the semiconductor elements 11a and 11b, electronic components such as a thermistor and a capacitor, and wiring members such as a bonding wire, a lead frame, and a connection terminal may be appropriately disposed. it can. Further, the conductive patterns 15a and 15b can be plated with a material having excellent corrosion resistance.
- Such a material is, for example, nickel, titanium, chromium, molybdenum, tantalum, niobium, tungsten, vanadium, bismuth, zirconium, hafnium, gold, silver, platinum, palladium, or an alloy containing at least one of them.
- the number, arrangement position, and shape of the conductive patterns 15a and 15b shown in FIG. 1 are merely examples. In addition to this case, the number, arrangement position, and shape can be determined by appropriate design.
- the metal plate 16 is made of a metal such as copper, aluminum, iron, silver, or an alloy containing at least one of them having excellent thermal conductivity.
- the thickness T1 of the metal plate 16 is preferably 0.1 mm or more and 1.0 mm or less, and more preferably 0.125 mm or more and 0.6 mm or less.
- a plurality of dimples 16 a and 16 b (concave portions) are formed on the back surface of the metal plate 16. The dimples 16 a and 16 b do not penetrate the metal plate 16.
- the depth D of the dimples 16a and 16b is preferably 30% or more and 95% or less of the thickness T1 of the metal plate 16, and more preferably 60% or more and 90% of the thickness T1 of the metal plate 16 It is as follows.
- the dimples 16a and 16b can increase the effect of relieving stress by increasing the depth. On the other hand, if the depth is too deep, a gap is likely to be generated between the solder 18 and the dimple 16, and there is a possibility that heat dissipation is reduced and partial discharge occurs.
- the thickness T1 of the metal plate 16 is about 0.3 mm
- the depth D of the dimples 16a and 16b is about 0.25 mm
- the thickness T2 to the surface is about 0.05 mm.
- a first area and a second area are set on the metal plate 16. Details of the dimples 16a and 16b and the first region and the second region of the metal plate 16 will be described later.
- the ceramic circuit board 13 having such a configuration, for example, a DCB (Direct Copper Bonding) board or an AMB (Active Metal Blazed) board can be used.
- the ceramic circuit board 13 can conduct heat generated in the semiconductor elements 11 a and 11 b to the heat radiating plate 17 through the conductive patterns 15 a and 15 b, the insulating plate 14, and the metal plate 16.
- the insulating plate 14 has, for example, a rectangular shape in plan view.
- the metal plate 16 has a rectangular shape with a smaller area than the insulating plate 14 in plan view. Therefore, the ceramic circuit board 13 has, for example, a rectangular shape.
- the heat radiating plate 17 has a ceramic circuit board 13 disposed on its front surface via solder 18.
- a heat sink 17 is excellent in thermal conductivity, for example, aluminum, iron, silver, copper, or an alloy composed of at least one of these, a composite material made of aluminum and silicon carbide, magnesium and silicon carbide. It is comprised by the composite material which consists of.
- a material such as nickel may be formed on the surface of the heat sink 17 by plating or the like. Specifically, in addition to nickel, there are a nickel-phosphorus alloy, a nickel-boron alloy, and the like.
- a cooler (not shown) may be joined to the rear surface side of the heat radiating plate 17 via solder or silver solder, or may be mechanically attached via thermal paste or the like. Thereby, the heat dissipation can be further improved.
- the cooler in this case is made of, for example, aluminum, iron, silver, copper, or an alloy composed of at least one of them having excellent thermal conductivity.
- a fin, a heat sink composed of a plurality of fins, a cooling device by water cooling, or the like can be applied.
- the heat sink 17 may be integrated with such a cooler. In that case, it is comprised with aluminum, iron, silver, copper excellent in thermal conductivity, or at least one of these.
- solders 12a, 12b, and 18 used in the semiconductor device 10 are, for example, alloys of tin-silver-copper, alloys of tin-zinc-bismuth, alloys of tin-copper, tin-silver.
- -It is composed of lead-free solder whose main component is at least one of alloys made of indium-bismuth.
- additives such as nickel, germanium, cobalt, or silicon may be included.
- the semiconductor elements 11a and 11b and the ceramic circuit board 13 on the heat sink 17 may be sealed with a sealing member.
- a case surrounding the semiconductor elements 11a and 11b and the ceramic circuit board 13 may be attached to the heat radiating plate 17, and the inside of the case may be sealed with a sealing member.
- a thermosetting resin such as an epoxy resin, a phenol resin, a maleimide resin, a silicon resin, or a silicon gel can be applied to the sealing member.
- a filler such as silicon oxide, aluminum oxide, boron nitride, or aluminum nitride may be included as a filler.
- the case is a box shape that covers the side portions of the semiconductor elements 11a and 11b and the ceramic circuit board 13, and is made of a thermoplastic resin.
- the resin include polyphenylene sulfide (PPS), polybutylene terephthalate (PBT) resin, polybutylene succinate (PBS) resin, polyamide (PA) resin, and acrylonitrile butadiene styrene (ABS) resin.
- PPS polyphenylene sulfide
- PBT polybutylene terephthalate
- PBS polybutylene succinate
- PA polyamide
- ABS acrylonitrile butadiene styrene
- FIG. 2 is a plan view of the back surface of the metal plate of the ceramic circuit board of the semiconductor device according to the first embodiment. 2 shows the case where the metal plate 16 of the ceramic circuit board 13 of the semiconductor device 10 of FIG. 1 is viewed from the back side.
- the back surface of such a metal plate 16 includes a first region 16c in which the dimples 16a and 16b are annularly formed along the outer peripheral edge, and a second region other than the first region 16c in which the dimples 16a and 16b are not formed.
- An area 16d is set.
- the first area 16 c is set to an area surrounding the central portion of the metal plate 16.
- dimples 16a are formed in an annular shape along the outer peripheral edge of the metal plate 16 at a predetermined interval W on the outside.
- dimples 16b are formed on the outer peripheral edge of the metal plate 16 at a predetermined interval W along an annular shape. If such an interval W is too narrow, the flow of the solder 18 is deteriorated. If the distance W is too large, the effects of the dimples 16a and 16b cannot be obtained. Therefore, the interval W between the dimples 16a and 16b is preferably 0.1 mm or more and 0.5 mm or less, more preferably 0.15 mm or more and 0.3 mm or less.
- the second region 16d is a central portion of the metal plate 16, and is surrounded by the first region 16c.
- the semiconductor elements 11a and 11b in the semiconductor device 10 are arranged on the second region 16d of the metal plate 16 of the ceramic circuit board 13 as shown in FIG. Heat generated from the semiconductor elements 11 a and 11 b is conducted to the first region 16 c of the metal plate 16 through the conductive patterns 15 a and 15 b and the insulating plate 14.
- the semiconductor elements 11 a and 11 b are arranged on the first region 16 c of the metal plate 16 of the ceramic circuit board 13, a plurality of dimples 16 a and 16 b are formed in the first region 16 c of the metal plate 16.
- the thermal conductivity is reduced.
- the shape of the dimples 16a and 16b in a plan view is a circular shape (having a hemispherical cross section), but the present invention is not limited to this case.
- the shape of the dimples 16a and 16b in plan view may be an elliptical shape, a long hole shape, or a rectangular shape.
- the cross-sectional shapes of the dimples 16a and 16b may be, for example, a square shape, a trapezoidal shape, a triangular shape, or the like.
- a plurality of dimples 16 a and 16 b are formed in the first region 16 c close to the outer periphery along the outer periphery of the back surface of the metal plate 16 of the ceramic circuit substrate 13. For this reason, even if a thermal stress corresponding to a temperature change in the semiconductor device 10 is generated in the ceramic circuit board 13, shrinkage of the ceramic circuit board 13 due to the temperature change is alleviated by the plurality of dimples 16 a and 16 b. Therefore, it is possible to prevent cracking of the ceramic circuit board 13 and peeling of the metal plate 16 and the conductive patterns 15a and 15b.
- the dimples 16 a and 16 b formed on the back surface of the metal plate 16 do not penetrate the metal plate 16.
- the metal plate 16 has a thickness from the bottom surface of the dimples 16 a and 16 b to the front surface of the metal plate 16. Therefore, the highly reliable semiconductor device 10 can be obtained without reducing the mounting parts such as the semiconductor elements 11a and 11b.
- the dimples 16 a and 16 b are filled with solder 18, and the solder 18 can be joined to the metal plate 16. Further, when the dimples 16a and 16b are filled with the solder 18, no gaps are formed in the dimples 16a and 16b. For this reason, the fall of heat dissipation and generation
- the plurality of dimples 16a and 16b may be formed along the two short sides of the rectangular metal plate 16 in the first region 16c, and may not be formed at positions along the two long sides. Further, for example, the plurality of dimples 16a and 16b may be formed only in the vicinity of the corner of the metal plate 16 in the first region 16c. 2 shows the case where the dimples 16a are also formed at the corners of the first region 16c corresponding to the corners of the rectangular metal plate 16, this is not restrictive.
- a plurality of dimples 16 a may be arranged in a bow shape near the corner of the first region 16 c corresponding to the corner of the metal plate 16.
- the corner of the first region 16c may be chamfered.
- the dimples 16a may be arranged side by side at the edge corresponding to the chamfered first region.
- FIGS. 3 and 4 are enlarged cross-sectional side views of a main part of a semiconductor device of a reference example.
- the semiconductor devices 20 and 30 in FIGS. 3 and 4 have the same configuration as the semiconductor device 10 except for the metal plate 16 of the semiconductor device 10 shown in FIG. Detailed description thereof will be omitted.
- the semiconductor devices 20 and 30 shown in FIG. 3 and FIG. 4 are enlarged and displayed around the area corresponding to the dimples 16a and 16b on the left side of the semiconductor device 10 shown in FIG.
- the semiconductor device 20 includes a semiconductor element 11a, a ceramic circuit board 23 having the semiconductor element 11a bonded to the front surface, and a heat sink 17 bonded to the back surface of the ceramic circuit board 23.
- the ceramic circuit board 23 includes an insulating plate 14, a conductive pattern 15 a formed on the front surface of the insulating plate 14, and a metal plate 26 formed on the back surface of the insulating plate 14.
- a plurality of dimples 26 a and 26 b are respectively formed on the back surface of the metal plate 26. The dimples 26 a and 26 b do not penetrate the metal plate 36.
- the distance from the position of the outermost end surface 14a of the insulating plate 14 to the position of the first end surface 15a1 of the outermost end portion of the conductive pattern 15a is set.
- the distance a and the distance from the position of the outermost end surface 14a of the insulating plate 14 to the position of the second end surface 26e of the outermost end portion of the metal plate 26 are set as a distance b.
- the distance a and the distance b are equal. That is, in the ceramic circuit board 23, the position of the first end face 15a1 of the conductive pattern 15a is equal to the position of the second end face 26e of the outermost end portion of the metal plate 26.
- a distance from the position of the outermost end surface 14a of the insulating plate 14 to the position of the outermost end portion 26a1 of the dimple 26a formed on the outermost part of the back surface of the metal plate 26 is a distance c.
- distance a distance b and distance c> distance a. That is, in the semiconductor device 20, the dimples 36a and 36b are formed inside the position of the first end face 15a1 of the conductive pattern 15a.
- the semiconductor device 30 includes a semiconductor element 11 a, a ceramic circuit substrate 33 in which the semiconductor element 11 a is bonded to the front surface, and a heat sink bonded to the back surface of the ceramic circuit substrate 33.
- the ceramic circuit board 33 includes an insulating plate 14, a conductive pattern 15 a formed on the front surface of the insulating plate 14, and a metal plate 36 formed on the back surface of the insulating plate 14.
- a plurality of dimples 36 a and 36 b are respectively formed on the back surface of the metal plate 36. The dimples 36 a and 36 b do not penetrate the metal plate 36.
- distance a> distance b and distance c> distance a That is, in the semiconductor device 30, the dimples 36a and 36b are formed inside the position of the first end face 15a1 of the conductive pattern 15a.
- the ceramic circuit board 33 of the semiconductor device 30 when a thermal stress due to a temperature change is generated, an inflection point is generated in the vicinity immediately below the first end face 15a1 of the conductive pattern 15a. For this reason, the insulating plate 14 may be cracked due to a crack generated in a region surrounded by a broken-line circle C in FIG.
- FIG. 5 is an enlarged cross-sectional side view of a main part of the semiconductor device according to the first embodiment. 5 shows an enlarged view of the periphery of the left dimples 16a and 16b of the semiconductor device 10 of FIG. Further, in FIG. 5, the periphery of the left dimples 16 a and 16 b of the semiconductor device 10 is enlarged and displayed. On the other hand, the periphery of the right dimples 16a and 16b of the semiconductor device 10 has the same configuration.
- the distance from the position of the outermost end surface 14a of the insulating plate 14 to the position of the first end surface 15a1 of the outermost end portion of the conductive pattern 15a is a distance a.
- a distance from the position of the outermost end surface 14 a of the insulating plate 14 to the position of the second end surface 16 e of the outermost end portion of the metal plate 16 is a distance b.
- the ceramic circuit board 13 is formed so that the distance b ⁇ the distance a.
- the distance from the position of the outermost end surface 14a of the insulating plate 14 to the position of the first end surface of the outermost end portion of the conductive pattern 15a is also the distance a.
- a distance c is a distance from the position of the outermost end surface 14a of the insulating plate 14 to the position of the outermost end portion 16a1 of the dimple 16a formed on the outermost surface of the back surface of the metal plate 16.
- a distance from the position of the outermost end surface 14a of the insulating plate 14 to the position of the innermost end portion 16b2 of the dimple 16b formed in the innermost part of the back surface of the metal plate 16 is defined as a distance d.
- the distance e from the position of the outermost end surface 14a of the insulating plate 14 to the third end surface 11a1 of the semiconductor element 11a is defined as a distance e.
- the ceramic circuit board 13 and the dimples 16 a and 16 b are formed so that the distance c ⁇ distance a, the distance a ⁇ distance d, and the distance d ⁇ distance e.
- the stress is relaxed in a region from the position of the outermost end portion 16a1 of the dimple 16a to the position of the innermost end portion 16b2 of the dimple 16b. . Therefore, the deformation near the conductive pattern 15a is small and no inflection point is generated. For this reason, the crack of the insulating plate 14 is prevented.
- the semiconductor device 10 includes semiconductor elements 11 a and 11 b and a ceramic circuit board 13.
- the ceramic circuit board 13 is formed on the front surfaces of the insulating plate 14 and the insulating plate 14, and is formed on the back surfaces of the conductive patterns 15a and 15b on which the semiconductor elements 11a and 11b are arranged and the insulating plate 14, and the conductive pattern 15a.
- the second end surface 16e is located outside the position of the first end surface 15a1, and a plurality of dimples 16a have a metal plate 16 formed on the back surface along at least part of the outer peripheral edge.
- the outermost end portion 16 a 1 of the dimple 16 a is located outside the position of the first end surface 15 a 1 of the conductive pattern 15 a in a side sectional view. For this reason, even if a thermal stress corresponding to a temperature change in the semiconductor device 10 is generated in the ceramic circuit board 13, deformation of the ceramic circuit board 13 due to the temperature change is alleviated by the plurality of dimples 16a and 16b. Therefore, it is possible to prevent cracking of the ceramic circuit board 13 and peeling of the metal plate 16 and the conductive patterns 15a and 15b.
- the innermost end portion 16b2 of the dimple 16b is located inside the position of the first end face 15a1 of the conductive pattern 15a in a side sectional view. Moreover, the innermost end portion 16b2 of the dimple 16b is located outside the position of the third end surface 11a1 of the semiconductor element 11a in a side sectional view. For this reason, the deformation
- the dimples 16 a and 16 b formed on the back surface of the metal plate 16 do not penetrate the metal plate 16 and have a thickness from the bottom surface of the dimples 16 a and 16 b to the front surface of the metal plate 16. For this reason, the dimples 16 a and 16 b are filled with the solder 18, and the solder 18 can be joined to the metal plate 16. Further, when the dimples 16a and 16b are filled with the solder 18, since no gaps are formed in the dimples 16a and 16b, deterioration of heat dissipation and occurrence of partial discharge are prevented.
- the distance W between the dimples 16a and 16b formed in the first region 16c on the back surface of the metal plate 16 is 0.1 mm or more and 0.5 mm or less.
- FIG. 6 is an enlarged cross-sectional side view of a main part of the semiconductor device according to the second embodiment. 6 has the same configuration as that of the semiconductor device 10 except for the metal plate 16 of the semiconductor device 10. Moreover, the same code
- the semiconductor device 10a shown in FIG. 6 displays an enlarged view of the periphery of the dimples 16a and 16b on the left side of the semiconductor device 10 shown in FIG.
- the semiconductor device 10 a includes a semiconductor element 11 a, a ceramic circuit substrate 13 in which the semiconductor element 11 a is bonded to the front surface, and a heat dissipation plate 17 bonded to the back surface of the ceramic circuit substrate 13.
- the ceramic circuit board 13 includes an insulating plate 14, conductive patterns 15 a and 15 b formed on the front surface of the insulating plate 14, and a metal plate 16 formed on the back surface of the insulating plate 14.
- the metal plate 16 is further formed with dimples 16f and 16g between the dimples 16a and 16b on the back surface (first region 16c (see FIG. 2)) of the metal plate 16 in a cross-sectional view.
- the dimples 16 f and 16 g do not penetrate the metal plate 16.
- the sizes of the dimples 16f and 16g are the same as the sizes of the dimples 16a and 16b. Further, such dimples 16a, 16b, 16f, and 16g are, for example, formed in the first region 16c in an annular shape along the outer peripheral edge portion of the metal plate 16 at a predetermined interval W on the outer side. .
- dimples 16f are annularly formed along the outer peripheral edge of the metal plate 16 at a predetermined interval W.
- dimples 16g are formed annularly along the outer peripheral edge of the metal plate 16 at a predetermined interval W inside the dimples 16f. In the innermost part, dimples 16b are formed annularly along the outer peripheral edge of the metal plate 16 at a predetermined interval W.
- a distance c is a distance from the position of the outermost end surface 14a of the insulating plate 14 to the position of the outermost end portion 16a1 of the dimple 16a formed on the outermost surface of the back surface of the metal plate 16.
- a distance from the position of the outermost end surface 14a of the insulating plate 14 to the position of the innermost end portion 16b2 of the dimple 16b formed in the innermost part of the back surface of the metal plate 16 is defined as a distance d.
- the ceramic circuit board 13 and the dimples 16a, 16b, 16f, and 16g are formed so that the distance c ⁇ distance a, the distance a ⁇ distance d, and the distance d ⁇ distance e. ing.
- the ceramic circuit board 13 of the semiconductor device 10a when thermal stress is generated due to temperature change, in the region from the position of the outermost end 16a1 of the dimple 16a to the position of the innermost end 16b2 of the dimple 16b, the vicinity of the conductive pattern 15a. Stress is relieved. Therefore, the deformation is small and no inflection point is generated. For this reason, the crack of the insulating plate 14 is prevented.
- the case where two dimples 16f and 16g are added between the dimples 16a and 16b has been described as an example.
- the number of dimples that can be added between the dimples 16a and 16b may be one or three or more.
- FIG. 7 is an enlarged cross-sectional side view of a main part of the semiconductor device according to the third embodiment. 7 has the same configuration as the semiconductor device 10. The same components are denoted by the same reference numerals, and detailed description thereof will be omitted.
- the semiconductor device 10b shown in FIG. 7 shows an enlarged view of the periphery of the dimples 16a and 16b on the left side of the semiconductor device 10 shown in FIG.
- the semiconductor device 10 b includes a semiconductor element 11 a, a ceramic circuit board 13 in which the semiconductor element 11 a is bonded to the front surface, and a heat dissipation plate 17 bonded to the back surface of the ceramic circuit board 13.
- the ceramic circuit board 13 includes an insulating plate 14, conductive patterns 15 a and 15 b formed on the front surface of the insulating plate 14, and a metal plate 16 formed on the back surface of the insulating plate 14. In the metal plate 16, only the dimples 16a are formed on the back surface (first region 16c (see FIG. 2)) of the metal plate 16 in a side sectional view.
- such dimples 16a are formed in the first region 16c along the outer periphery of the metal plate 16 at a predetermined interval W.
- the distance a, the distance b, and the distance e are set in both the semiconductor device 10b and the ceramic circuit board 13.
- the distance c from the position of the outermost end surface 14a of the insulating plate 14 to the position of the outermost end portion 16a1 of the dimple 16a formed on the outermost surface of the rear surface of the metal plate 16 is a distance c
- the outermost end surface 14a of the insulating plate 14 The distance from the position to the position of the innermost end portion 16a2 of the dimple 16a formed in the innermost part of the back surface of the metal plate 16 is defined as a distance d.
- the ceramic circuit board 13 and the dimple 16a are formed so that the distance c ⁇ distance a, the distance a ⁇ distance d, and the distance d ⁇ distance e.
- the dimples 16a, 16b, 16f, and 16g formed on the back surface of the metal plate 16 are also provided in the semiconductor devices 10a and 10b according to the second and third embodiments, similarly to the semiconductor device 10 according to the first embodiment. Is not penetrating the metal plate 16, and has a thickness from the bottom surfaces of the dimples 16 a, 16 b, 16 f, 16 g to the front surface of the metal plate 16. Therefore, the dimples 16 a, 16 b, 16 f, and 16 g are filled with the solder 18, and the solder 18 can be joined to the metal plate 16.
- each interval W between the dimples 16a, 16b, 16f, and 16g formed in the first region 16c on the back surface of the metal plate 16 is 0.1 mm or more and 0.5 mm or less.
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Abstract
熱応力の発生と共に、品質の低下を抑制することができる。 半導体装置(10)は、側断面視で、導電パターン(15a)の第1端面(15a1)の位置は、ディンプル(16a)の最外端部(16a1)の位置と、ディンプル(16b)の最内端部(16b2)の位置との間に位置している。このため、半導体装置(10)における温度変化に応じた熱応力がセラミック回路基板(13)に生じても、複数のディンプル(16a,16b)により温度変化によるセラミック回路基板(13)に対する変形が緩和されるようになる。したがって、セラミック回路基板(13)の割れ、金属板(16)並びに導電パターン(15a)の剥がれを防止することができる。
Description
本発明は、半導体装置に関する。
IGBT(Insulated Gate Bipolar Transistor)、パワーMOSFET(Metal Oxide Semiconductor Field Effect Transistor)等の半導体素子を含む半導体装置は、例えば、電力変換装置として利用されている。このような半導体装置は、当該半導体素子と共に絶縁板と絶縁板のおもて面に形成され、半導体素子が配置される複数の導電パターンと絶縁板の裏面に形成された金属板とを有するセラミック回路基板を含んでいる。さらに、半導体装置は、動作時に半導体素子の発熱を冷却するために、上記セラミック回路基板が、例えば、銅で構成されたヒートシンク等の放熱部に配置される。
このような半導体装置では、半導体素子をセラミック回路基板、セラミック回路基板を放熱部にそれぞれはんだを介して接合する際に加熱されて、冷却される。また、半導体装置は自身の動作に応じて温度変化し、また、外部環境の温度変化を受ける。このため、セラミック回路基板は、絶縁板の導電パターン並びに金属板に対する熱膨張係数の差により、熱応力を受けてしまう。セラミック回路基板が熱応力を受けてしまうと、絶縁板が割れてしまうおそれがある。これが半導体装置の信頼性の低下につながる。
そこで、セラミック回路基板に、ディンプル(孔)を形成することで、セラミック回路基板に発生する熱応力を緩和することが提案されている(例えば、特許文献1参照)。
特許文献1に記載されたディンプルは、セラミック回路基板の導電パターンのおもて面に形成される。そのため、半導体素子、電子部品や配線部材等の実装面積が少なくなり、相対的に大きなセラミック回路基板が必要であった。
本発明は、このような点に鑑みてなされたものであり、コンパクトで、熱応力を緩和することができ、信頼性の高い半導体装置を提供することを目的とする。
本発明の一観点によれば、半導体素子と、絶縁板と前記絶縁板のおもて面に形成され、前記半導体素子が配置される導電パターンと前記絶縁板の裏面に形成され、前記導電パターンの第1端面の位置よりも外側に位置する第2端面を備え、複数の第1凹部が外周縁部の少なくとも一部に沿って裏面に形成された金属板とを有する基板と、を有し、側断面視で、前記第1凹部の最外端部の位置は前記導電パターンの前記第1端面の位置よりも外側に位置している、半導体装置が提供される。
また、前記金属板の裏面に複数の第2凹部が前記複数の第1凹部の内側に前記外周縁部に沿って形成されている。
また、側断面視で、前記第2凹部の最内端部は、前記第1端面よりも内側に位置している。
また、側断面視で、前記第2凹部の前記最内端部が前記半導体素子の第3端面の位置よりも外側に位置している。
また、前記金属板の裏面に前記第1凹部と前記第2凹部との間に、前記外周縁部に沿って複数列の凹部が形成されている。
また、前記金属板の裏面に形成された前記第1凹部同士の間隔は、0.1mm以上、0.5mm以下である。
また、前記第1凹部の底部から前記金属板のおもて面までは第1厚さの厚みが存在している。
また、前記第1厚さは、前記金属板の厚さに対して、30%以上、95%以下である。
また、前記第2凹部の底部から前記金属板のおもて面までは第2厚さの厚みが存在している。
また、前記第2厚さは、前記金属板の厚さに対して、30%以上、95%以下である。
また、前記複数の第1凹部が前記金属板の裏面に前記外周縁部に沿って環状に形成されている。
また、前記半導体素子は、前記第1凹部が形成されている前記金属板の裏面の第1領域よりも中央側の第2領域上に対応する前記導電パターン上に配置されている。
また、側断面視で、前記第1凹部の最内端部の位置は前記導電パターンの前記第1端面の位置よりも内側に位置している。
また、前記基板がはんだを介して接合されている放熱板をさらに有する。
開示の技術によれば、コンパクトで、熱応力を緩和して、半導体装置の信頼性の低下を防止することができる。
本発明の上記及び他の目的、特徴及び利点は本発明の例として好ましい実施の形態を表す添付の図面と関連した以下の説明により明らかになるであろう。
以下、図面を参照して、実施の形態について説明する。
[第1の実施の形態]
まず、第1の実施の形態の半導体装置について図1を用いて説明する。図1は、第1の実施の形態の半導体装置の側断面図である。半導体装置10は、図1に示されるように、半導体素子11a,11bと、半導体素子11a,11bがおもて面に接合されたセラミック回路基板13(基板)と、セラミック回路基板13の裏面に接合された放熱板17とを有している。なお、このように図1に示す半導体装置10は、後述する図2における第1領域16c及び第2領域16dを含むような位置の断面図である。
まず、第1の実施の形態の半導体装置について図1を用いて説明する。図1は、第1の実施の形態の半導体装置の側断面図である。半導体装置10は、図1に示されるように、半導体素子11a,11bと、半導体素子11a,11bがおもて面に接合されたセラミック回路基板13(基板)と、セラミック回路基板13の裏面に接合された放熱板17とを有している。なお、このように図1に示す半導体装置10は、後述する図2における第1領域16c及び第2領域16dを含むような位置の断面図である。
半導体素子11a,11bは、例えば、IGBT、パワーMOSFET等のスイッチング素子を含んでいる。当該スイッチング素子は、シリコンまたは炭化シリコンから構成される。このような半導体素子11a,11bは、例えば、裏面にドレイン電極(または、コレクタ電極)を、おもて面にゲート電極及びソース電極(または、エミッタ電極)をそれぞれ備えている。また、半導体素子11a,11bは、必要に応じて、SBD(Schottky Barrier Diode)、FWD(Free Wheeling Diode)等のダイオードを含んでいる。このような半導体素子11a,11bは、裏面に主電極としてカソード電極を、おもて面に主電極としてアノード電極をそれぞれ備えている。なお、図1に示す半導体素子11a,11bの個数(2個)は一例である。この場合に限らずに、適宜設計により個数を定めることができる。
セラミック回路基板13は、絶縁板14と絶縁板14のおもて面に形成された導電パターン15a,15bと絶縁板14の裏面に形成された金属板16とを有している。絶縁板14は、熱伝導性に優れた、酸化アルミニウム、窒化アルミニウム、窒化珪素等の熱伝導性が高いセラミックスにより構成されている。絶縁板14の厚さは、好ましくは、0.2mm以上、1.5mm以下であり、より好ましくは、0.25mm以上、1.0mm以下である。導電パターン15a,15bは、導電性に優れた材質により構成されている。このような材質として、例えば、銅、アルミニウム、または、少なくともこれらの一種を含む合金等により構成されている。導電パターン15a,15bの厚さは、好ましくは、0.1mm以上、1.0mm以下であり、より好ましくは、0.125mm以上、0.6mm以下である。このような導電パターン15a,15b上に、半導体素子11a,11bがはんだ12a,12bを介してそれぞれ接合されている。なお、このような導電パターン15a,15b上には、半導体素子11a,11bの他に、サーミスタやコンデンサ等の電子部品、ボンディングワイヤー、リードフレームや接続端子等の配線部材を、適宜配置することができる。また、導電パターン15a,15bは、耐食性に優れた材質によりめっき処理を行うことも可能である。このような材質は、例えば、ニッケル、チタン、クロム、モリブデン、タンタル、ニオブ、タングステン、バナジウム、ビスマス、ジルコニウム、ハフニウム、金、銀、白金、パラジウム、または、少なくともこれらの一種を含む合金等である。なお、図1に示す導電パターン15a,15bも個数、配置位置並びに形状は一例である。この場合に限らずに、適宜設計により個数、配置位置並びに形状を定めることができる。
金属板16は、熱伝導性に優れた銅、アルミニウム、鉄、銀、または、少なくともこれらの一種を含む合金等の金属により構成されている。金属板16の厚さT1は、好ましくは、0.1mm以上、1.0mm以下であり、より好ましくは、0.125mm以上、0.6mm以下である。また、金属板16の裏面に複数のディンプル16a,16b(凹部)がそれぞれ形成されている。ディンプル16a,16bは、金属板16を貫通するものではない。ディンプル16a,16bの深さDは、好ましくは、金属板16の厚さT1の30%以上、95%以下であって、より好ましくは、金属板16の厚さT1の60%以上、90%以下である。ディンプル16a,16bは、深くすることで応力を緩和する効果を大きくすることができる。一方、深すぎると、はんだ18とディンプル16との間に空隙が生じやすく、放熱性の低下や部分放電が発生するおそれがある。例えば、金属板16の厚さT1が0.3mm程度である場合に、ディンプル16a,16bの深さDは0.25mm程度であって、ディンプル16a,16bの底部から金属板16のおもて面までの厚さT2は0.05mm程度である。また、金属板16には、図1に示されるように第1領域及び第2領域が設定されている。なお、金属板16のディンプル16a,16b並びに第1領域及び第2領域の詳細については後述する。
このような構成を有するセラミック回路基板13として、例えば、DCB(Direct Copper Bonding)基板、AMB(Active Metal Blazed)基板を用いることができる。セラミック回路基板13は、半導体素子11a,11bで発生した熱を導電パターン15a,15b、絶縁板14及び金属板16を介して、放熱板17に伝導させることができる。なお、絶縁板14は平面視で、例えば、矩形状を成している。また、金属板16は平面視で、絶縁板14よりも面積が小さな矩形状を成している。したがって、セラミック回路基板13は、例えば、矩形状を成している。
放熱板17は、図1に示されるように、そのおもて面にセラミック回路基板13がはんだ18を介して配置されている。このような放熱板17は、熱伝導性に優れた、例えば、アルミニウム、鉄、銀、銅、または、少なくともこれらの一種から構成される合金、アルミニウムと炭化シリコンからなる複合材、マグネシウムと炭化シリコンとからなる複合材により構成されている。また、耐食性を向上させるために、例えば、ニッケル等の材料をめっき処理等により放熱板17の表面に形成してもよい。具体的には、ニッケルの他に、ニッケル-リン合金、ニッケル-ボロン合金等がある。なお、この放熱板17の裏面側に冷却器(図示を省略)をはんだまたは銀ろう等を介して接合させ、または、サーマルペースト等を介して機械的に取りつけてもよい。これにより放熱性をさらに向上させることも可能である。この場合の冷却器は、例えば、熱伝導性に優れたアルミニウム、鉄、銀、銅、または、少なくともこれらの一種から構成される合金等により構成されている。また、冷却器として、フィン、または、複数のフィンから構成されるヒートシンク並びに水冷による冷却装置等を適用することができる。また、放熱板17は、このような冷却器と一体化されていてもよい。その場合は、熱伝導性に優れたアルミニウム、鉄、銀、銅、または、少なくともこれらの一種により構成される。そして、耐食性を向上させるために、例えば、ニッケル等の材料をめっき処理等により冷却器と一体化された放熱板の表面に形成してもよい。具体的には、ニッケルの他に、ニッケル-リン合金、ニッケル-ボロン合金等がある。また、セラミック回路基板13の裏面には、上記の放熱板17に代わって、上記の冷却器をはんだ18を介して、接合してもよい。なお、上記の半導体装置10で利用されているはんだ12a,12b,18は、例えば、錫-銀-銅からなる合金、錫-亜鉛-ビスマスからなる合金、錫-銅からなる合金、錫-銀-インジウム-ビスマスからなる合金のうち少なくともいずれかの合金を主成分とする鉛フリーはんだにより構成される。さらに、ニッケル、ゲルマニウム、コバルトまたはシリコン等の添加物が含まれてもよい。
また、このような構成を有する半導体装置10では、放熱板17上の半導体素子11a,11b及びセラミック回路基板13を封止部材により封止してもよい。または、放熱板17に半導体素子11a,11b及びセラミック回路基板13を囲むケースを取り付けてケース内を封止部材により封止してもよい。なお、この場合の封止部材は、例えば、エポキシ樹脂、フェノール樹脂、マレイミド樹脂、シリコン樹脂、シリコンゲル等の熱硬化性樹脂を適用することができる。さらに、フィラーとして酸化シリコン、酸化アルミニウム、窒化ホウ素または窒化アルミニウム等の充填材とを含んでいてもよい。そして、ケースは、半導体素子11a,11b及びセラミック回路基板13の側部を覆う箱型であって、熱可塑性樹脂により構成されている。当該樹脂として、ポリフェニレンサルファイド(PPS)、ポリブチレンテレフタレート(PBT)樹脂、ポリブチレンサクシネート(PBS)樹脂、ポリアミド(PA)樹脂、または、アクリロニトリルブタジエンスチレン(ABS)樹脂等がある。また、このようなケースは、接着剤(図示を省略)を介して放熱板17に接合される。
次に、このような半導体装置10のセラミック回路基板13の金属板16のディンプル16a,16bについて、図2を用いて説明する。図2は、第1の実施の形態の半導体装置のセラミック回路基板の金属板の裏面の平面図である。なお、図2は、図1の半導体装置10のセラミック回路基板13の金属板16を裏面から見た場合を示している。このような金属板16の裏面は、ディンプル16a,16bが外周縁部に沿って環状に形成される第1領域16cと、ディンプル16a,16bが形成されていない、第1領域16c以外の第2領域16dとが設定されている。
第1領域16cは、金属板16の中央部を取り囲む領域に設定されている。第1領域16cには、外側にディンプル16aが所定の間隔Wで金属板16の外周縁部に沿って環状に形成されている。ディンプル16aの内側に、ディンプル16bが所定の間隔Wで金属板16の外周縁部に環状に沿って形成されている。このような間隔Wは、狭すぎると、はんだ18の流れが悪くなる。また、間隔Wが大きすぎると、ディンプル16a,16bの効果が得られない。そのため、ディンプル16a,16bの間隔Wは、好ましくは、0.1mm以上、0.5mm以下であり、より好ましくは0.15mm以上、0.3mm以下である。なお、第1の実施の形態では、第1領域16cに、金属板16の外周に沿って2列のディンプル16a,16bが形成されている場合を示している。この場合に限らず、1列でも、3列以上のディンプルを形成することも可能である。
また、第2領域16dは、金属板16の中央部であって、第1領域16cに周りを取り囲まれている。半導体装置10における半導体素子11a,11bは、図1に示したように、セラミック回路基板13の金属板16の第2領域16d上に配置される。半導体素子11a,11bから発生した熱は導電パターン15a,15b及び絶縁板14を経由して金属板16の第1領域16cに伝導する。例えば、半導体素子11a,11bがセラミック回路基板13の金属板16の第1領域16c上に配置されると、金属板16の第1領域16cには複数のディンプル16a,16bが形成されているために、熱伝導性が低下してしまう。一方、半導体素子11a,11bをセラミック回路基板13の金属板16の第2領域16d上に配置すると、第1領域16c上に配置された場合に比べて放熱性の低下が抑制される。なお、図1及び図2では、ディンプル16a,16bの平面視の形状は円形状(断面は半球状)である場合を示しているがこの場合に限らない。例えば、ディンプル16a,16bの平面視の形状としては楕円形状、長穴形状、方形状でもよい。また、ディンプル16a,16bの断面形状として、例えば、方形状、台形状、三角形状等でもよい。
このように上記半導体装置10は、セラミック回路基板13の金属板16の裏面の外周縁部に沿って環状に外周縁部寄りの第1領域16cに複数のディンプル16a,16bが形成されている。このため、半導体装置10における温度変化に応じた熱応力がセラミック回路基板13に生じても、複数のディンプル16a,16bにより温度変化によるセラミック回路基板13に対する収縮が緩和されるようになる。したがって、セラミック回路基板13の割れ、金属板16並びに導電パターン15a,15bの剥がれを防止することができる。
また、金属板16の裏面に形成されたディンプル16a,16bは、金属板16を貫通していない。金属板16は、ディンプル16a,16bの底面から金属板16のおもて面まで厚さを備えている。このため、半導体素子11a,11b等の実装部品を減らすことなく、信頼性の高い半導体装置10が得られる。また、ディンプル16a,16b内にはんだ18が充填されて、はんだ18は金属板16と接合することができる。さらに、ディンプル16a,16bにはんだ18が充填されるとディンプル16a,16bに空隙ができない。このため、放熱性の低下並びに部分放電の発生が防止される。なお、図2では、セラミック回路基板13の金属板16の裏面の第1領域16cにおいて、外周縁部に沿って複数のディンプル16a,16bが環状に形成されている場合を示したが、この場合に限らない。例えば、複数のディンプル16a,16bは、第1領域16cにおいて、矩形な金属板16の2つの短辺に沿って形成され、2つの長辺に沿った位置には形成されなくてもよい。また、例えば、複数のディンプル16a,16bは、第1領域16cにおいて、金属板16の角部近傍にのみに形成されていてもよい。また、図2では、ディンプル16aは、矩形状の金属板16の角部に対応した第1領域16cの角部にも形成する場合を示したが、この場合に限らない。例えば、ディンプル16aは、金属板16の角部に対応した第1領域16cの角部近傍に弓なりに複数並んでいてもよい。また、例えば、金属板16の角部が面取りされている場合には、第1領域16cの角部も面取りされていてよい。その場合、ディンプル16aは、面取りされた第1領域に対応した縁部に並んで配置されていてよい。
ところで、半導体装置10では、セラミック回路基板13に対するディンプル16a,16bの位置に応じて、セラミック回路基板13に対する熱応力に起因した損傷をより抑制することができる。そこで、以下では、半導体装置10のセラミック回路基板13に対する熱応力に起因した損傷を確実に抑制するためのセラミック回路基板13に対するディンプル16a,16bの適切な位置について説明する。
まず、参考例としての半導体装置について図3及び図4を用いて説明する。図3及び図4は、参考例の半導体装置の要部拡大側断面図である。なお、図3及び図4の半導体装置20,30は、図1に示した半導体装置10の金属板16以外の構成については半導体装置10と同じ構成を有して、同じ符号を付しており、それらの詳細な説明については省略する。また、図3及び図4に示す半導体装置20,30は、図1で示すところの半導体装置10の左側のディンプル16a,16bに当たる領域の周辺を拡大して表示している。
半導体装置20は、図3に示されるように、半導体素子11aと、半導体素子11aがおもて面に接合されたセラミック回路基板23と、セラミック回路基板23の裏面に接合された放熱板17とを有している。セラミック回路基板23は、絶縁板14と絶縁板14のおもて面に形成された導電パターン15aと絶縁板14の裏面に形成された金属板26とを有している。金属板26の裏面に複数のディンプル26a,26bがそれぞれ形成されている。ディンプル26a,26bは、金属板36を貫通するものではない。
このような半導体装置20では、図3によれば、セラミック回路基板23において、絶縁板14の最外端面14aの位置から導電パターン15aの最外端部の第1端面15a1の位置までの距離を距離a、絶縁板14の最外端面14aの位置から金属板26の最外端部の第2端面26eの位置までの距離を距離bとする。半導体装置20では、距離aと距離bとが等しい。すなわち、セラミック回路基板23では、導電パターン15aの第1端面15a1の位置と金属板26の最外端部の第2端面26eの位置とが等しい。また、絶縁板14の最外端面14aの位置から金属板26の裏面の最外部に形成されたディンプル26aの最外端部26a1の位置までの距離を距離cとする。半導体装置20では、距離a=距離b、なおかつ、距離c>距離aである。すなわち、半導体装置20では、ディンプル36a,36bが導電パターン15aの第1端面15a1の位置よりも内側に形成されている。
このような半導体装置20では、距離a=距離bである。このため、温度変化が発生しても、セラミック回路基板23において、絶縁板14における曲げ応力の発生は小さい。しかしながら、ディンプル26a,26bの有無に関わらず、導電パターン15aの第1端面15a1の直下近傍と金属板26の第2端面26eの直上近傍に応力が集中する。表裏で対向した部分に応力が集中するため、絶縁板14は、この領域に亀裂が生じて、割れてしまうおそれがある。
また、半導体装置30は、図4に示されるように、半導体素子11aと、半導体素子11aがおもて面に接合されたセラミック回路基板33と、セラミック回路基板33の裏面に接合された放熱板17とを有している。セラミック回路基板33は、絶縁板14と絶縁板14のおもて面に形成された導電パターン15aと絶縁板14の裏面に形成された金属板36とを有している。金属板36の裏面に複数のディンプル36a,36bがそれぞれ形成されている。ディンプル36a,36bは、金属板36を貫通するものではない。
このような半導体装置30では、図4に示されるように、セラミック回路基板33において、絶縁板14の最外端面14aの位置から導電パターン15aの最外端部の第1端面15a1の位置までの距離を距離a、絶縁板14の最外端面14aの位置から金属板36の最外端部の第2端面36eの位置までの距離を距離bとする。また、絶縁板14の最外端面14aの位置から金属板36の裏面の最外部に形成されたディンプル36aの最外端部36a1の位置までの距離を距離cとする。半導体装置30では、距離a>距離b、なおかつ、距離c>距離aである。すなわち、半導体装置30では、ディンプル36a,36bが導電パターン15aの第1端面15a1の位置よりも内側に形成されている。半導体装置30のセラミック回路基板33では、温度変化による熱応力が発生すると、導電パターン15aの第1端面15a1の直下近傍に変曲点が発生する。このため、絶縁板14は、図4中の破線の円Cで囲まれた領域に亀裂が生じて、割れてしまうおそれがある。
そこで、上記を鑑みて、金属板16に対してディンプル16a,16bを形成した第1の実施の形態の半導体装置10について、図5を用いて説明する。図5は、第1の実施の形態の半導体装置の要部拡大側断面図である。なお、図5は、図1の半導体装置10の左側のディンプル16a,16bの周辺を拡大して表示している。また、図5では、半導体装置10の左側のディンプル16a,16bの周辺を拡大して表示している。一方、半導体装置10の右側のディンプル16a,16bの周辺も同様の構成である。
図5によれば、セラミック回路基板13において、絶縁板14の最外端面14aの位置から導電パターン15aの最外端部の第1端面15a1の位置までの距離を距離aとする。そして、絶縁板14の最外端面14aの位置から金属板16の最外端部の第2端面16eの位置までの距離を距離bとする。このような半導体装置10では、距離b<距離aとなるように、セラミック回路基板13を形成している。なお、図5では図示していない導電パターン15bについても、絶縁板14の最外端面14aの位置から導電パターン15aの最外端部の第1端面の位置までの距離も距離aである。また、絶縁板14の最外端面14aの位置から金属板16の裏面の最外部に形成されたディンプル16aの最外端部16a1の位置までの距離を距離cとする。絶縁板14の最外端面14aの位置から金属板16の裏面の最内部に形成されたディンプル16bの最内端部16b2の位置までの距離を距離dとする。さらに、絶縁板14の最外端面14aの位置から半導体素子11aの第3端面11a1までの距離を距離eとする。このような半導体装置10では、距離c<距離a、さらに、距離a<距離d、さらに、距離d<距離eとなるように、セラミック回路基板13及びディンプル16a,16bを形成している。半導体装置10のセラミック回路基板13では、温度変化による熱応力が発生すると、ディンプル16aの最外端部16a1の位置からディンプル16bの最内端部16b2の位置までの領域において、応力が緩和される。そのため、導電パターン15a近傍の変形が小さく、変曲点が発生しない。このため、絶縁板14の割れが防止される。
上記半導体装置10は、半導体素子11a,11bと、セラミック回路基板13と、を有している。セラミック回路基板13は、絶縁板14と絶縁板14のおもて面に形成され、半導体素子11a,11bが配置される導電パターン15a,15bと絶縁板14の裏面に形成され、導電パターン15aの第1端面15a1の位置よりも外側に位置する第2端面16eを備え、複数のディンプル16aが外周縁部の少なくとも一部に沿って裏面に形成された金属板16とを有する。そして、半導体装置10において、側断面視で、ディンプル16aの最外端部16a1は、導電パターン15aの第1端面15a1の位置よりも外側に位置している。このため、半導体装置10における温度変化に応じた熱応力がセラミック回路基板13に生じても、複数のディンプル16a,16bにより温度変化によるセラミック回路基板13に対する変形が緩和されるようになる。したがって、セラミック回路基板13の割れ、金属板16並びに導電パターン15a,15bの剥がれを防止することができる。
さらに、半導体装置10において、側断面視で、ディンプル16bの最内端部16b2は、導電パターン15aの第1端面15a1の位置よりも内側に位置している。また、側断面視で、ディンプル16bの最内端部16b2は、半導体素子11aの第3端面11a1の位置よりも外側に位置している。このため、温度変化によるセラミック回路基板13に対する変形が、より緩和されるようになる。また、セラミック回路基板13の外縁部に外力が加わっても、絶縁板14の割れが防止される。
そして、金属板16の裏面に形成されたディンプル16a,16bは、金属板16を貫通しておらず、ディンプル16a,16bの底面から金属板16のおもて面まで厚さを備えている。このため、ディンプル16a,16b内にはんだ18が充填されて、はんだ18は金属板16と接合することができる。また、ディンプル16a,16bにはんだ18が充填されるとディンプル16a,16bに空隙ができないために、放熱性の低下並びに部分放電の発生が防止される。さらに、金属板16の裏面の第1領域16cに形成されているディンプル16a,16bのそれぞれの間隔Wは、0.1mm以上、0.5mm以下である。このため、はんだ18がセラミック回路基板13の外縁部まで濡れ広がり、セラミック回路基板13と放熱板17とをはんだ18により隙間なく確実に接合することができる。したがって、このような半導体装置10は品質の低下を抑制して、信頼性の低下を防止することができる。
[第2の実施の形態]
第2の実施の形態では、第1の実施の形態の金属板16に対してディンプルの数を増やした場合の半導体装置について、図6を用いて説明する。図6は、第2の実施の形態の半導体装置の要部拡大側断面図である。なお、図6の半導体装置10aは、半導体装置10の金属板16以外の構成については半導体装置10と同じ構成を有している。また、同じ構成には同じ符号を付しており、それらの詳細な説明については省略する。また、図6に示す半導体装置10aは、図1で示すところの半導体装置10の左側のディンプル16a,16bの周辺を拡大して表示している。
第2の実施の形態では、第1の実施の形態の金属板16に対してディンプルの数を増やした場合の半導体装置について、図6を用いて説明する。図6は、第2の実施の形態の半導体装置の要部拡大側断面図である。なお、図6の半導体装置10aは、半導体装置10の金属板16以外の構成については半導体装置10と同じ構成を有している。また、同じ構成には同じ符号を付しており、それらの詳細な説明については省略する。また、図6に示す半導体装置10aは、図1で示すところの半導体装置10の左側のディンプル16a,16bの周辺を拡大して表示している。
半導体装置10aは、図6に示されるように、半導体素子11aと、半導体素子11aがおもて面に接合されたセラミック回路基板13と、セラミック回路基板13の裏面に接合された放熱板17とを有している。セラミック回路基板13は、絶縁板14と絶縁板14のおもて面に形成された導電パターン15a,15bと絶縁板14の裏面に形成された金属板16とを有している。金属板16は、断面視で金属板16の裏面(第1領域16c(図2参照))にディンプル16a,16bの間にさらにディンプル16f,16gがそれぞれ形成されている。ディンプル16f,16gは、金属板16を貫通するものではない。なお、ディンプル16f,16gのサイズは、ディンプル16a,16bのサイズと同様である。また、このようなディンプル16a,16b,16f,16gは、例えば、第1領域16cには、外側にディンプル16aが所定の間隔Wで金属板16の外周縁部に沿って環状に形成されている。ディンプル16aの内側に、ディンプル16fが所定の間隔Wで金属板16の外周縁部に沿って環状に形成されている。さらに、ディンプル16fの内側に、ディンプル16gが所定の間隔Wで金属板16の外周縁部に沿って環状に形成されている。最内部に、ディンプル16bが所定の間隔Wで金属板16の外周縁部に沿って環状に形成されている。
また、半導体装置10aでも、セラミック回路基板13において、距離a、距離b、距離eが設定されている。また、絶縁板14の最外端面14aの位置から金属板16の裏面の最外部に形成されたディンプル16aの最外端部16a1の位置までの距離を距離cとする。絶縁板14の最外端面14aの位置から金属板16の裏面の最内部に形成されたディンプル16bの最内端部16b2の位置までの距離を距離dとする。このような半導体装置10aでも、距離c<距離a、さらに、距離a<距離d、さらに、距離d<距離eとなるように、セラミック回路基板13及びディンプル16a,16b,16f,16gを形成している。
半導体装置10aのセラミック回路基板13でも、温度変化による熱応力が発生すると、ディンプル16aの最外端部16a1の位置からディンプル16bの最内端部16b2の位置までの領域において、導電パターン15a近傍の応力が緩和される。そのため、変形が小さく、変曲点が発生しない。このため、絶縁板14の割れが防止される。なお、第2の実施の形態では、ディンプル16a,16bの間に2つのディンプル16f,16gを追加した場合を例に挙げて説明した。ディンプル16a,16bの間に追加可能なディンプルの数は1つでも、3つ以上でもよい。
[第3の実施の形態]
第3の実施の形態では、第1の実施の形態の金属板16に対してディンプルが1つの場合の半導体装置について、図7を用いて説明する。図7は、第3の実施の形態の半導体装置の要部拡大側断面図である。なお、図7の半導体装置10bは、半導体装置10と同じ構成を有している。同じ構成には同じ符号を付しており、それらの詳細な説明については省略する。また、図7に示す半導体装置10bは、図1で示すところの半導体装置10の左側のディンプル16a,16bの周辺を拡大して表示している。
第3の実施の形態では、第1の実施の形態の金属板16に対してディンプルが1つの場合の半導体装置について、図7を用いて説明する。図7は、第3の実施の形態の半導体装置の要部拡大側断面図である。なお、図7の半導体装置10bは、半導体装置10と同じ構成を有している。同じ構成には同じ符号を付しており、それらの詳細な説明については省略する。また、図7に示す半導体装置10bは、図1で示すところの半導体装置10の左側のディンプル16a,16bの周辺を拡大して表示している。
半導体装置10bは、図7に示されるように、半導体素子11aと、半導体素子11aがおもて面に接合されたセラミック回路基板13と、セラミック回路基板13の裏面に接合された放熱板17とを有している。セラミック回路基板13は、絶縁板14と絶縁板14のおもて面に形成された導電パターン15a,15bと絶縁板14の裏面に形成された金属板16とを有している。金属板16は、側断面視で金属板16の裏面(第1領域16c(図2参照))にディンプル16aのみが形成されている。また、このようなディンプル16aは、例えば、第1領域16cに、ディンプル16aが所定の間隔Wで金属板16の外周に沿って形成されている。また、半導体装置10bでも、セラミック回路基板13においても、距離a、距離b、距離eが設定されている。また、絶縁板14の最外端面14aの位置から金属板16の裏面の最外部に形成されたディンプル16aの最外端部16a1の位置までの距離を距離c、絶縁板14の最外端面14aの位置から金属板16の裏面の最内部に形成されたディンプル16aの最内端部16a2の位置までの距離を距離dとする。このような半導体装置10bでも、距離c<距離a、さらに、距離a<距離d、さらに、距離d<距離eとなるように、セラミック回路基板13及びディンプル16aを形成している。
半導体装置10bのセラミック回路基板13でも、温度変化による熱応力が発生すると、ディンプル16aの最外端部16a1の位置からディンプル16aの最内端部16a2の位置までの領域において、導電パターン15a近傍の応力が緩和される。そのため、変形が小さく、変曲点が発生しない。このため、絶縁板14の割れが防止される。
さらに、第2,第3の実施の形態の半導体装置10a,10bも、第1の実施の形態の半導体装置10と同様に、金属板16の裏面に形成されたディンプル16a,16b,16f,16gは、金属板16を貫通しておらず、ディンプル16a,16b,16f,16gの底面から金属板16のおもて面まで厚さを備えている。このため、ディンプル16a,16b,16f,16g内にはんだ18が充填されて、はんだ18は金属板16と接合することができる。また、ディンプル16a,16b,16f,16gにはんだ18が充填されるとディンプル16a,16b,16f,16gに空隙ができないために、放熱性の低下並びに部分放電の発生が防止される。
さらに、金属板16の裏面の第1領域16cに形成されているディンプル16a,16b,16f,16gのそれぞれの間隔Wは、0.1mm以上、0.5mm以下である。このため、はんだ18がセラミック回路基板13の外縁部まで濡れ広がり、セラミック回路基板13と放熱板17とをはんだ18により隙間なく確実に接合することができる。したがって、このような半導体装置10a,10bは品質の低下を抑制して、信頼性の低下を防止することができる。
上記については単に本発明の原理を示すものである。さらに、多数の変形、変更が当業者にとって可能であり、本発明は上記に示し、説明した正確な構成及び応用例に限定されるものではなく、対応するすべての変形例及び均等物は、添付の請求項及びその均等物による本発明の範囲とみなされる。
10,10a,10b 半導体装置
11a,11b 半導体素子
11a1 第3端面
12a,12b,18 はんだ
13 セラミック回路基板
14 絶縁板
14a 最外端面
15a,15b 導電パターン
15a1 第1端面
16 金属板
16a,16b,16f,16g ディンプル
16a1 最外端部
16a2,16b2 最内端部
16c 第1領域
16d 第2領域
16e 第2端面
17 放熱板
11a,11b 半導体素子
11a1 第3端面
12a,12b,18 はんだ
13 セラミック回路基板
14 絶縁板
14a 最外端面
15a,15b 導電パターン
15a1 第1端面
16 金属板
16a,16b,16f,16g ディンプル
16a1 最外端部
16a2,16b2 最内端部
16c 第1領域
16d 第2領域
16e 第2端面
17 放熱板
Claims (14)
- 半導体素子と、
絶縁板と前記絶縁板のおもて面に形成され、前記半導体素子が配置される導電パターンと前記絶縁板の裏面に形成され、前記導電パターンの第1端面の位置よりも外側に位置する第2端面を備え、複数の第1凹部が外周縁部の少なくとも一部に沿って裏面に形成された金属板とを有する基板と、
を有し、
側断面視で、前記第1凹部の最外端部の位置は前記導電パターンの前記第1端面の位置よりも外側に位置している、
半導体装置。 - 前記金属板の裏面に複数の第2凹部が前記複数の第1凹部の内側に前記外周縁部に沿って形成されている、
請求項1に記載の半導体装置。 - 側断面視で、前記第2凹部の最内端部は、前記第1端面よりも内側に位置している、
請求項2に記載の半導体装置。 - 側断面視で、前記第2凹部の前記最内端部が前記半導体素子の第3端面の位置よりも外側に位置している、
請求項3に記載の半導体装置。 - 前記金属板の裏面に前記第1凹部と前記第2凹部との間に、前記外周縁部に沿って複数列の凹部が形成されている、
請求項2に記載の半導体装置。 - 前記金属板の裏面に形成された前記第1凹部同士の間隔は、0.1mm以上、0.5mm以下である、
請求項1に記載の半導体装置。 - 前記第1凹部の底部から前記金属板のおもて面までは第1厚さの厚みが存在している、
請求項1に記載の半導体装置。 - 前記第1厚さは、前記金属板の厚さに対して、30%以上、95%以下である、
請求項7に記載の半導体装置。 - 前記第2凹部の底部から前記金属板のおもて面までは第2厚さの厚みが存在している、
請求項2に記載の半導体装置。 - 前記第2厚さは、前記金属板の厚さに対して、30%以上、95%以下である、
請求項9に記載の半導体装置。 - 前記複数の第1凹部が前記金属板の裏面に前記外周縁部に沿って環状に形成されている、
請求項1に記載の半導体装置。 - 前記半導体素子は、前記第1凹部が形成されている前記金属板の裏面の第1領域よりも中央側の第2領域上に対応する前記導電パターン上に配置されている、
請求項11に記載の半導体装置。 - 側断面視で、前記第1凹部の最内端部の位置は前記導電パターンの前記第1端面の位置よりも内側に位置している、
請求項1に記載の半導体装置。 - 前記基板がはんだを介して接合されている放熱板をさらに有する、
請求項1に記載の半導体装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201980004101.7A CN111052353B (zh) | 2018-03-01 | 2019-01-28 | 半导体装置 |
DE112019001086.7T DE112019001086T5 (de) | 2018-03-01 | 2019-01-28 | Halbleitervorrichtung |
JP2020502873A JP7047895B2 (ja) | 2018-03-01 | 2019-01-28 | 半導体装置 |
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JPWO2020121680A1 (ja) * | 2018-12-10 | 2021-06-03 | 富士電機株式会社 | 半導体装置 |
JP2021108321A (ja) * | 2019-12-27 | 2021-07-29 | 京セラ株式会社 | 印刷配線板及び印刷配線板の製造方法 |
WO2022219934A1 (ja) * | 2021-04-12 | 2022-10-20 | 富士電機株式会社 | 半導体装置 |
US11521941B2 (en) | 2019-01-16 | 2022-12-06 | Fuji Electric Co., Ltd. | Semiconductor device with a substrate having depressions formed thereon |
WO2022259676A1 (ja) * | 2021-06-09 | 2022-12-15 | Ngkエレクトロデバイス株式会社 | 半導体装置用基板 |
JP7459539B2 (ja) | 2020-02-07 | 2024-04-02 | 富士電機株式会社 | 半導体装置 |
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CN114245633A (zh) * | 2021-11-30 | 2022-03-25 | 中航光电科技股份有限公司 | 多通道数字光模块气密封装结构及陶瓷电路板 |
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CN111052353B (zh) | 2023-12-08 |
DE112019001086T5 (de) | 2020-11-12 |
US20200194386A1 (en) | 2020-06-18 |
US11133271B2 (en) | 2021-09-28 |
CN111052353A (zh) | 2020-04-21 |
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