JPWO2018135147A1 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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Abstract
Description
本発明にかかる半導体装置は、シリコンよりバンドギャップが広いワイドバンドギャップ半導体を用いて構成される。実施の形態1においては、ワイドバンドギャップ半導体として例えば炭化珪素(SiC)を用いて作製された炭化珪素半導体装置について、MOSFETを例に説明する。図1A、図1Bは、実施の形態1にかかる炭化珪素半導体装置の構成を示す断面図である。
次に、実施の形態1にかかる炭化珪素半導体装置の製造方法について、例えば1200Vの耐圧クラスのMOSFETを作成する場合を例に説明する。図5〜図8は、実施の形態1にかかる炭化珪素半導体装置の製造途中の状態を示す断面図である。まず、例えば2×1019/cm3程度の不純物濃度で窒素がドーピングされたn+型炭化珪素基板1を用意する。n+型炭化珪素基板1は、主面が例えば、<11−20>方向に4度程度のオフ角を有する(000−1)面であってもよい。次に、n+型炭化珪素基板1の(000−1)面上に、1.0×1016/cm3の不純物濃度で窒素がドーピングされた厚さ10μm程度のn-型炭化珪素エピタキシャル層2を成長させる。ここで、図5に示される構造となる。
次に、実施の形態2にかかる炭化珪素半導体装置の構造について説明する。図9は、実施の形態2にかかる炭化珪素半導体装置の構造を示す断面図である。図9に示すように、実施の形態2にかかる半導体装置が実施の形態1にかかる半導体装置と異なる点は、p型ベース層3が下部領域に設けられず、下部領域にはp型炭化珪素層15が設けられていることである。
次に、実施の形態2にかかる炭化珪素半導体装置の製造方法について、例えば1200Vの耐圧クラスのMOSFETを作成する場合を例に説明する。実施の形態2にかかる半導体装置の製造方法は、まず、実施の形態1と同様にp型ベース層3を選択的に形成する工程を行う。この際、実施の形態2では、下部領域にp型ベース層3を形成しない。
次に、実施の形態3にかかる炭化珪素半導体装置の構造について説明する。図10は、実施の形態3にかかる炭化珪素半導体装置の構造を示す断面図である。図10に示すように、実施の形態3にかかる半導体装置が実施の形態1にかかる半導体装置と異なる点は、p型ベース層3が下部領域に設けられず、下部領域には、n-型炭化珪素エピタキシャル層2が設けられていることである。
実施の形態3にかかる炭化珪素半導体装置は、実施の形態2にかかる炭化珪素半導体装置の製造方法において、p型炭化珪素層15を形成しないことにより製造される。このため、実施の形態3にかかる炭化珪素半導体装置の製造方法の説明は省略する。
2 n-型炭化珪素エピタキシャル層
3 p型ベース層
4 n+型ソース領域
5 p+型コンタクト領域
6 ゲート絶縁膜
7 絶縁膜
8 ゲート電極
9 層間絶縁膜
10 ソース電極
11 ゲート電極パッド
12 電流センスパッド
13 温度センスパッド
14 ドレイン電極
15 p型炭化珪素層
16 ライフタイムキラー領域
17 終端構造部
20 ゲートパッド部
Claims (8)
- 第1導電型の半導体基板と、
前記半導体基板のおもて面に設けられた、前記半導体基板より低不純物濃度の第1導電型の第1半導体層と、
前記第1半導体層の、前記半導体基板側に対して反対側の表面層に選択的に設けられた第2導電型の第2半導体層と、
前記第2半導体層の、前記半導体基板側に対して反対側の表面層に選択的に設けられた第1導電型の第1半導体領域と、
前記第2半導体層の、前記半導体基板側に対して反対側の表面層に選択的に設けられた、前記第2半導体層より高不純物濃度の第2導電型の第2半導体領域と、
前記第1半導体領域と前記第1半導体層とに挟まれた前記第2半導体層の表面上の少なくとも一部にゲート絶縁膜を介して設けられたゲート電極と、
前記第1半導体領域と前記第2半導体層の表面に設けられた第1電極と、
前記半導体基板の裏面に設けられた第2電極と、
前記ゲート電極と電気的に接続されたゲート電極パッドと、
を備え、
前記ゲート電極パッドと深さ方向に対向する第1下部領域は、キャリアの再結合率が、前記第1電極と深さ方向に対向する第2下部領域より低いことを特徴とする半導体装置。 - 前記第1下部領域は、前記第2下部領域よりも一桁以上不純物濃度が低い前記第2半導体層であることを特徴とする請求項1に記載の半導体装置。
- 前記第1下部領域は、前記第1半導体層の、前記半導体基板側に対して反対側の表面層に選択的に設けられた、前記第2下部領域よりも一桁以上不純物濃度が低い第2導電型の第3半導体層であることを特徴とする請求項1に記載の半導体装置。
- 前記第1下部領域は、前記第1半導体層であることを特徴とする請求項1に記載の半導体装置。
- オン状態の時、主電流が流れる活性領域において、主素子として適用しない領域と深さ方向に対向する領域は、前記第1下部領域と同様な構造であることを特徴とする請求項1〜4のいずれか一つに記載の半導体装置。
- 前記主素子として適用しない領域は、電流センスパッド部、温度センスパッド部および演算回路部であることを特徴とする請求項5に記載の半導体装置。
- 前記第1下部領域の内部に、ライフタイムキラーを注入したライフタイムキラー領域が設けられることを特徴とする請求項1〜6のいずれか一つに記載の半導体装置。
- 第1導電型の半導体基板のおもて面に、前記半導体基板より低不純物濃度の第1導電型の第1半導体層を形成する第1工程と、
前記第1半導体層の、前記半導体基板側に対して反対側の表面層に選択的に第2導電型の第2半導体層を形成する第2工程と、
前記第2半導体層の、前記半導体基板側に対して反対側の表面層に選択的に第1導電型の第1半導体領域を形成する第3工程と、
前記第2半導体層の、前記半導体基板側に対して反対側の表面層に選択的に、前記第2半導体層より高不純物濃度の第2導電型の第2半導体領域を形成する第4工程と、
前記第1半導体領域と前記第1半導体層とに挟まれた前記第2半導体層の表面上の少なくとも一部にゲート絶縁膜を介してゲート電極を形成する第5工程と、
前記第1半導体領域と前記第2半導体層の表面に第1電極を形成する第6工程と、
前記半導体基板の裏面に第2電極を形成する第7工程と、
前記ゲート電極と電気的に接続されたゲート電極パッドを形成する第8工程と、
を含み、
前記ゲート電極パッドと深さ方向に対向する第1下部領域を、キャリアの再結合率が、前記第1電極と深さ方向に対向する第2下部領域より低く形成することを特徴とする半導体装置の製造方法。
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