JPWO2016170443A1 - 半導体装置および電子機器 - Google Patents
半導体装置および電子機器 Download PDFInfo
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- JPWO2016170443A1 JPWO2016170443A1 JP2017513382A JP2017513382A JPWO2016170443A1 JP WO2016170443 A1 JPWO2016170443 A1 JP WO2016170443A1 JP 2017513382 A JP2017513382 A JP 2017513382A JP 2017513382 A JP2017513382 A JP 2017513382A JP WO2016170443 A1 JPWO2016170443 A1 JP WO2016170443A1
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- Prior art keywords
- film
- wiring
- insulating film
- transistor
- oxide semiconductor
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Abstract
Description
本実施の形態においては、トランジスタを有する半導体装置の一例について、図1乃至図3を用いて以下説明を行う。
本実施の形態では、本発明の一態様の半導体装置および半導体装置の作製方法について、図4乃至図30を参照して説明する。
図4(A)は、本発明の一態様の半導体装置であるトランジスタ500の上面図であり、図4(B)は、図4(A)に示す一点鎖線X1−X2間における切断面の断面図、図4(C)は一点鎖線Y1−Y2間における切断面の断面図に相当する。
基板502としては、例えばガラス基板、セラミック基板、石英基板、サファイア基板等、少なくとも後の熱処理に耐えうる程度の耐熱性を有している基板を用いるとよい。また、シリコンや炭化シリコンを材料とした単結晶半導体基板、多結晶半導体基板、シリコンゲルマニウム等の化合物半導体基板、SOI基板等を適用することも可能であり、これらの基板上に半導体素子が設けられたものを、基板502として用いてもよい。なお、基板502として、ガラス基板を用いる場合、第6世代、第7世代、第8世代、第9世代、第10世代等の大面積基板を用いることで、大型の表示装置を作製することができる。このような大面積基板を用いることで製造コストを低減させることができるため好ましい。また、基板502として可撓性基板を用いてもよい。
トランジスタ500の第1のゲート絶縁膜として機能する絶縁膜506および絶縁膜507としては、プラズマ化学気相堆積(PECVD:Plasma Enhanced Chemical Vapor Deposition)法、スパッタリング法等により、酸化シリコン膜、酸化窒化シリコン膜、窒化酸化シリコン膜、窒化シリコン膜、酸化アルミニウム膜、酸化ハフニウム膜、酸化イットリウム膜、酸化ジルコニウム膜、酸化ガリウム膜、酸化タンタル膜、酸化マグネシウム膜、酸化ランタン膜、酸化セリウム膜および酸化ネオジム膜を一種以上含む絶縁膜を、それぞれ用いることができる。なお、絶縁膜506および絶縁膜507の積層構造とせずに、上述の材料から選択された単層の絶縁膜、または3層以上の絶縁膜を用いてもよい。
酸化物半導体膜508としては、先に示す材料を用いることができる。酸化物半導体膜508がIn−M−Zn酸化物の場合、In−M−Zn酸化物を成膜するために用いるスパッタリングターゲットの金属元素の原子数比は、In≧M(Inの原子数はMの原子数以上)、Zn≧M(Znの原子数はMの原子数以上)を満たすことが好ましい。このようなスパッタリングターゲットの金属元素の原子数比として、In:M:Zn=1:1:1、In:M:Zn=1:1:1.2、In:M:Zn=2:1:3、In:M:Zn=3:1:2、In:M:Zn=4:2:4.1が好ましい。また、酸化物半導体膜508がIn−M−Zn酸化物の場合、スパッタリングターゲットとしては、多結晶のIn−M−Zn酸化物を含むターゲットを用いると好ましい。多結晶のIn−M−Zn酸化物を含むターゲットを用いることで、結晶性を有する酸化物半導体膜508を形成しやすくなる。なお、成膜される酸化物半導体膜508の原子数比はそれぞれ、誤差として上記のスパッタリングターゲットに含まれる金属元素の原子数比のプラスマイナス40%の変動を含む。例えば、スパッタリングターゲットとして、原子数比がIn:Ga:Zn=4:2:4.1を用いる場合、成膜される酸化物半導体膜508の原子数比は、In:Ga:Zn=4:2:3近傍となる場合がある。
以下では、酸化物半導体の構造について説明する。
まずは、CAAC−OSについて説明する。
次に、nc−OSについて説明する。
a−like OSは、nc−OSと非晶質酸化物半導体との間の構造を有する酸化物半導体である。
次に、酸化物半導体のキャリア密度について、以下に説明を行う。
絶縁膜514および絶縁膜516は、酸化物半導体膜508に酸素を供給する機能を有する。また、絶縁膜518は、トランジスタ500の保護絶縁膜および第2のゲート絶縁膜としての機能を有する。また、絶縁膜514および絶縁膜516は、酸素を有する。また、絶縁膜514は、酸素を透過することのできる絶縁膜である。なお、絶縁膜514は、後に形成する絶縁膜516を形成する際の、酸化物半導体膜508へのダメージ緩和膜としても機能する。
次に、本発明の一態様の半導体装置であるトランジスタ500の作製方法について、図15乃至図30を用いて詳細に説明する。
次に、図15乃至図30に示すトランジスタ500の作製方法とは異なる作製方法について、以下説明する。
本実施の形態では、表示素子として液晶素子を用いる表示装置の構成について説明する。
本実施の形態では、本発明の一態様の半導体装置を有する記憶装置について、図32乃至図36を用いて説明を行う。
本実施の形態では、本発明の一態様の半導体装置を有する表示モジュールおよび電子機器について、図37および図38を用いて説明を行う。
409 絶縁膜
422 絶縁膜
428 絶縁膜
450 半導体基板
452 絶縁膜
454 導電膜
456 領域
460 領域
462 絶縁膜
464 絶縁膜
466 絶縁膜
468 絶縁膜
472a 領域
472b 領域
474a 導電膜
474b 導電膜
474c 導電膜
476a 導電膜
476b 導電膜
478a 導電膜
478b 導電膜
478c 導電膜
480a 導電膜
480b 導電膜
480c 導電膜
490 絶縁膜
492 絶縁膜
494 絶縁膜
496a 導電膜
496b 導電膜
496c 導電膜
496d 導電膜
498a 導電膜
498b 導電膜
498c 導電膜
498d 導電膜
500 トランジスタ
502 基板
504 導電膜
506 絶縁膜
507 絶縁膜
508 酸化物半導体膜
508a 酸化物半導体膜
508b 酸化物半導体膜
509 酸化物半導体膜
509a 絶縁膜
509b 酸化物半導体膜
512 導電膜
512a 導電膜
512b 導電膜
514 絶縁膜
516 絶縁膜
518 絶縁膜
519 絶縁膜
520 導電膜
520a 導電膜
520b 導電膜
531 バリア膜
536a マスク
536b マスク
538 エッチャント
539 エッチャント
540 酸素
540a 酸素
542 エッチャント
542a コンタクトホール
542b コンタクトホール
542c コンタクトホール
570 トランジスタ
600 トランジスタ
602 基板
604 導電膜
606 絶縁膜
608 酸化物半導体膜
608a 酸化物半導体膜
608b 酸化物半導体膜
612a 導電膜
612b 導電膜
614 絶縁膜
615 絶縁膜
616 導電膜
617 導電膜
618 絶縁膜
700 半導体装置
701 基板
702 画素部
703 画素
704 ソースドライバ
705 基板
706 ゲートドライバ
706a ゲートドライバ
706b ゲートドライバ
708 FPC端子部
710 配線
711 配線部
712 シール材
716 FPC
717 走査線
717a 走査線
717b 走査線
718 配線
719 コンタクトホール
719a コンタクトホール
719b コンタクトホール
719c コンタクトホール
720 信号線
721 領域
722 領域
730 領域
734 絶縁膜
736 着色層
738 遮光膜
744 突起
750 トランジスタ
752 トランジスタ
760 接続電極
764 絶縁膜
766 絶縁膜
768 絶縁膜
770 平坦化絶縁膜
772 導電膜
774 導電膜
775 液晶素子
776 液晶層
778 構造体
780 異方性導電膜
790 容量素子
1000 セル
1001 配線
1002 配線
1003 配線
1004 配線
1005 配線
1006 配線
1010 セルアレイ
1011 配線
1012 配線
1014 配線
1015 配線
1016 配線
1017 配線
1100 セル
1200 トランジスタ
1400 容量素子
5000 筐体
5001 表示部
5002 表示部
5003 スピーカ
5004 LEDランプ
5005 操作キー
5006 接続端子
5007 センサ
5008 マイクロフォン
5009 スイッチ
5010 赤外線ポート
5011 記録媒体読込部
5012 支持部
5013 イヤホン
5014 アンテナ
5015 シャッターボタン
5016 受像部
5017 充電器
8000 表示モジュール
8001 上部カバー
8002 下部カバー
8003 FPC
8004 タッチパネル
8005 FPC
8006 表示パネル
8007 バックライト
8008 光源
8009 フレーム
8010 プリント基板
8011 バッテリ
Claims (9)
- 第1の配線と、第2の配線と、第3の配線と、第1の駆動回路と、第2の駆動回路と、セルアレイと、を有し、
前記セルアレイは、トランジスタと、保持容量と、を含むセルを複数有し、
前記トランジスタは、第1の絶縁膜と、酸化物半導体膜と、第2の絶縁膜と、を有し、
前記酸化物半導体膜は、前記第1の絶縁膜を介して前記第2の配線と重なる領域と、前記第2の絶縁膜を介して前記第3の配線と重なる領域と、を有し、
前記第1の配線は、前記第1の駆動回路に電気的に接続され、
前記第2の配線は、前記第2の駆動回路に電気的に接続され、
前記トランジスタは、前記第2の配線の上方に配置され、
前記第2の配線は、前記トランジスタと重なる領域に、前記トランジスタの第1のゲート電極として機能する領域を有し、
前記第3の配線は、前記トランジスタの上方に配置され、
前記第3の配線は、前記トランジスタと重なる領域に、前記トランジスタの第2のゲート電極として機能する領域を有し、
前記第3の配線は、前記第2の配線と重なる領域を有し、
前記第2の配線が、前記セルアレイ以外の領域で前記第3の配線と電気的に接続されることを特徴とする半導体装置。 - 前記第2の配線および前記第3の配線は、前記セルのうち少なくとも1つにおいて電気的に接続されることを特徴とする、
請求項1に記載の半導体装置。 - 第1の配線と、第2の配線と、第3の配線と、第1の駆動回路と、第2の駆動回路と、第3の駆動回路と、セルアレイと、を有し、
前記第2の駆動回路と前記第3の駆動回路の間に前記セルアレイが配置され、
前記セルアレイは、トランジスタと、保持容量と、を含むセルを複数有し、
前記トランジスタは、第1の絶縁膜と、酸化物半導体膜と、第2の絶縁膜と、を有し、
前記酸化物半導体膜は、前記第1の絶縁膜を介して前記第2の配線と重なる領域と、前記第2の絶縁膜を介して前記第3の配線と重なる領域と、を有し、
前記第1の配線は、前記第1の駆動回路に電気的に接続され、
前記第2の配線は、前記第2の駆動回路または前記第3の駆動回路に電気的に接続され、
前記トランジスタは、前記第2の配線の上方に配置され、
前記第2の配線は、前記トランジスタと重なる領域に、前記トランジスタの第1のゲート電極として機能する領域を有し、
前記第3の配線は、前記トランジスタの上方に配置され、
前記第3の配線は、前記トランジスタと重なる領域に、前記トランジスタの第2のゲート電極として機能する領域を有し、
前記第3の配線は、前記第2の配線と重なる領域を有し、
前記第2の配線が、前記セルアレイ以外の領域で前記第3の配線と電気的に接続されることを特徴とする半導体装置。 - 前記セルアレイと前記第2の駆動回路の間の領域において、前記第2の配線と前記第3の配線とが電気的に接続される、
請求項1又は請求項3に記載の半導体装置。 - 前記第2の配線と前記第3の配線との接続部における、前記第2の配線の幅は、前記セルと重なる領域における前記第2の配線の幅よりも広いことを特徴とする、
請求項1又は請求項3に記載の半導体装置。 - 前記第3の配線の電気抵抗は、前記第2の配線の電気抵抗以下であることを特徴とする、
請求項1又は請求項3に記載の半導体装置。 - 前記第3の配線は、銅元素を有することを特徴とする、
請求項1又は請求項3に記載の半導体装置。 - 前記セルは画素であり、前記セルアレイは画素部であることを特徴とする、
請求項1又は請求項3に記載の半導体装置。 - 請求項1又は請求項3に記載の半導体装置を有する電子機器。
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CN107534057B (zh) | 2021-04-30 |
KR20170137822A (ko) | 2017-12-13 |
KR20220151034A (ko) | 2022-11-11 |
CN113314545A (zh) | 2021-08-27 |
KR102462475B1 (ko) | 2022-11-01 |
WO2016170443A1 (ja) | 2016-10-27 |
US10591791B2 (en) | 2020-03-17 |
CN107534057A (zh) | 2018-01-02 |
US20180095336A1 (en) | 2018-04-05 |
JP6723225B2 (ja) | 2020-07-15 |
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