JPS6491247A - Register file - Google Patents

Register file

Info

Publication number
JPS6491247A
JPS6491247A JP62249514A JP24951487A JPS6491247A JP S6491247 A JPS6491247 A JP S6491247A JP 62249514 A JP62249514 A JP 62249514A JP 24951487 A JP24951487 A JP 24951487A JP S6491247 A JPS6491247 A JP S6491247A
Authority
JP
Japan
Prior art keywords
input
clock
scanning
pulse
action
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62249514A
Other languages
Japanese (ja)
Other versions
JPH0664545B2 (en
Inventor
Yasuhiro Nakai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62249514A priority Critical patent/JPH0664545B2/en
Publication of JPS6491247A publication Critical patent/JPS6491247A/en
Publication of JPH0664545B2 publication Critical patent/JPH0664545B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Executing Machine-Instructions (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To omit the input of a clock required for a resetting action to be done before a scanning operation by producing a pulse to reset a latch circuit group at the rise of a scanning action carried out by an access address. CONSTITUTION:A pulse generating circuit 14 produces a pulse in place of a clock at the rise of a scanning action and an address secondary latch circuit group 7 is reset. At the same time, the output of an adder 8 is applied as a write/read address together with the data on a selector group 10 added as the input data. The word value 0 of a register file is read out with input of a 1st clock used for scanning and written with a shift given to a higher position by a bit. While the data supplied in a scan-in mode is written into the lowest rank bit. Hereafter said word value is added by 1 via the adder 8 for each input of a clock and then successively shifted. Thus a scanning action is carried out.
JP62249514A 1987-10-01 1987-10-01 Register file Expired - Lifetime JPH0664545B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62249514A JPH0664545B2 (en) 1987-10-01 1987-10-01 Register file

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62249514A JPH0664545B2 (en) 1987-10-01 1987-10-01 Register file

Publications (2)

Publication Number Publication Date
JPS6491247A true JPS6491247A (en) 1989-04-10
JPH0664545B2 JPH0664545B2 (en) 1994-08-22

Family

ID=17194106

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62249514A Expired - Lifetime JPH0664545B2 (en) 1987-10-01 1987-10-01 Register file

Country Status (1)

Country Link
JP (1) JPH0664545B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6291871A (en) * 1985-10-18 1987-04-27 Fujitsu Ltd Diagnostic system for synchronizing and asynchronizing circuits

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6291871A (en) * 1985-10-18 1987-04-27 Fujitsu Ltd Diagnostic system for synchronizing and asynchronizing circuits

Also Published As

Publication number Publication date
JPH0664545B2 (en) 1994-08-22

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