JPS5679352A - Address generator - Google Patents
Address generatorInfo
- Publication number
- JPS5679352A JPS5679352A JP15722979A JP15722979A JPS5679352A JP S5679352 A JPS5679352 A JP S5679352A JP 15722979 A JP15722979 A JP 15722979A JP 15722979 A JP15722979 A JP 15722979A JP S5679352 A JPS5679352 A JP S5679352A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- adder
- address
- register
- word
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Executing Machine-Instructions (AREA)
Abstract
PURPOSE: To shorten the instruction execution time in the event of using high level language, by shifting an input of the adder by use of the shifting circuit, in case the address is generated by the adder.
CONSTITUTION: An output of the register 7 is provided to the binary adder 10 through the output of the resister 6 and the shift circuit 15. When the logic 1 is provided to this circuit 15 from the control line 16, the contents of the register 7 are shifted by 1 bit, and are provided to the adder 10. Accordingly, the word type head address stored in the resister 7, and the doubled address stored in the register 7 are added by the adder 10, and the result is output to the address bus 12. Therefore, the word-type array element address is easily generated automatically. In this regard, if a 2 bit shifting circuit is added as to the circuit 15, it is applicable to the double word type or the type having furthr word length, as well. Also, when plural control signals are provided, the (n) bit shifting circuit is controlled, and the address of various types of language can be generated by the same circuit.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15722979A JPS5679352A (en) | 1979-12-03 | 1979-12-03 | Address generator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15722979A JPS5679352A (en) | 1979-12-03 | 1979-12-03 | Address generator |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5679352A true JPS5679352A (en) | 1981-06-29 |
JPS6336017B2 JPS6336017B2 (en) | 1988-07-18 |
Family
ID=15645044
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15722979A Granted JPS5679352A (en) | 1979-12-03 | 1979-12-03 | Address generator |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5679352A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60173653A (en) * | 1984-02-20 | 1985-09-07 | Oki Electric Ind Co Ltd | Dma controller |
JPS60173643A (en) * | 1984-02-20 | 1985-09-07 | Oki Electric Ind Co Ltd | Address generating device |
JPS6142035A (en) * | 1984-08-03 | 1986-02-28 | Hitachi Ltd | Logical type information processor |
JP2011503758A (en) * | 2007-11-20 | 2011-01-27 | クゥアルコム・インコーポレイテッド | System and method for determining the address of an element in a table |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3818203A (en) * | 1973-08-27 | 1974-06-18 | Honeywell Inc | Matrix shifter |
JPS5081233A (en) * | 1973-11-16 | 1975-07-01 | ||
JPS5299027A (en) * | 1976-02-16 | 1977-08-19 | Hitachi Ltd | Address designating system |
JPS52132644A (en) * | 1976-02-20 | 1977-11-07 | Intel Corp | Method of processing plural digital signals at a time and digital logical circuit for processing digital signals |
JPS52138845A (en) * | 1976-05-14 | 1977-11-19 | Hitachi Shipbuilding Eng Co | Address control circuit for direct data transfer |
-
1979
- 1979-12-03 JP JP15722979A patent/JPS5679352A/en active Granted
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3818203A (en) * | 1973-08-27 | 1974-06-18 | Honeywell Inc | Matrix shifter |
JPS5081233A (en) * | 1973-11-16 | 1975-07-01 | ||
JPS5299027A (en) * | 1976-02-16 | 1977-08-19 | Hitachi Ltd | Address designating system |
JPS52132644A (en) * | 1976-02-20 | 1977-11-07 | Intel Corp | Method of processing plural digital signals at a time and digital logical circuit for processing digital signals |
JPS52138845A (en) * | 1976-05-14 | 1977-11-19 | Hitachi Shipbuilding Eng Co | Address control circuit for direct data transfer |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60173653A (en) * | 1984-02-20 | 1985-09-07 | Oki Electric Ind Co Ltd | Dma controller |
JPS60173643A (en) * | 1984-02-20 | 1985-09-07 | Oki Electric Ind Co Ltd | Address generating device |
JPS6142035A (en) * | 1984-08-03 | 1986-02-28 | Hitachi Ltd | Logical type information processor |
JPH0427575B2 (en) * | 1984-08-03 | 1992-05-12 | Hitachi Seisakusho Kk | |
JP2011503758A (en) * | 2007-11-20 | 2011-01-27 | クゥアルコム・インコーポレイテッド | System and method for determining the address of an element in a table |
Also Published As
Publication number | Publication date |
---|---|
JPS6336017B2 (en) | 1988-07-18 |
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