JPS5679352A - Address generator - Google Patents

Address generator

Info

Publication number
JPS5679352A
JPS5679352A JP15722979A JP15722979A JPS5679352A JP S5679352 A JPS5679352 A JP S5679352A JP 15722979 A JP15722979 A JP 15722979A JP 15722979 A JP15722979 A JP 15722979A JP S5679352 A JPS5679352 A JP S5679352A
Authority
JP
Japan
Prior art keywords
circuit
adder
address
register
word
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15722979A
Other languages
Japanese (ja)
Other versions
JPS6336017B2 (en
Inventor
Hiroshi Kadota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15722979A priority Critical patent/JPS5679352A/en
Publication of JPS5679352A publication Critical patent/JPS5679352A/en
Publication of JPS6336017B2 publication Critical patent/JPS6336017B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE: To shorten the instruction execution time in the event of using high level language, by shifting an input of the adder by use of the shifting circuit, in case the address is generated by the adder.
CONSTITUTION: An output of the register 7 is provided to the binary adder 10 through the output of the resister 6 and the shift circuit 15. When the logic 1 is provided to this circuit 15 from the control line 16, the contents of the register 7 are shifted by 1 bit, and are provided to the adder 10. Accordingly, the word type head address stored in the resister 7, and the doubled address stored in the register 7 are added by the adder 10, and the result is output to the address bus 12. Therefore, the word-type array element address is easily generated automatically. In this regard, if a 2 bit shifting circuit is added as to the circuit 15, it is applicable to the double word type or the type having furthr word length, as well. Also, when plural control signals are provided, the (n) bit shifting circuit is controlled, and the address of various types of language can be generated by the same circuit.
COPYRIGHT: (C)1981,JPO&Japio
JP15722979A 1979-12-03 1979-12-03 Address generator Granted JPS5679352A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15722979A JPS5679352A (en) 1979-12-03 1979-12-03 Address generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15722979A JPS5679352A (en) 1979-12-03 1979-12-03 Address generator

Publications (2)

Publication Number Publication Date
JPS5679352A true JPS5679352A (en) 1981-06-29
JPS6336017B2 JPS6336017B2 (en) 1988-07-18

Family

ID=15645044

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15722979A Granted JPS5679352A (en) 1979-12-03 1979-12-03 Address generator

Country Status (1)

Country Link
JP (1) JPS5679352A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60173653A (en) * 1984-02-20 1985-09-07 Oki Electric Ind Co Ltd Dma controller
JPS60173643A (en) * 1984-02-20 1985-09-07 Oki Electric Ind Co Ltd Address generating device
JPS6142035A (en) * 1984-08-03 1986-02-28 Hitachi Ltd Logical type information processor
JP2011503758A (en) * 2007-11-20 2011-01-27 クゥアルコム・インコーポレイテッド System and method for determining the address of an element in a table

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3818203A (en) * 1973-08-27 1974-06-18 Honeywell Inc Matrix shifter
JPS5081233A (en) * 1973-11-16 1975-07-01
JPS5299027A (en) * 1976-02-16 1977-08-19 Hitachi Ltd Address designating system
JPS52132644A (en) * 1976-02-20 1977-11-07 Intel Corp Method of processing plural digital signals at a time and digital logical circuit for processing digital signals
JPS52138845A (en) * 1976-05-14 1977-11-19 Hitachi Shipbuilding Eng Co Address control circuit for direct data transfer

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3818203A (en) * 1973-08-27 1974-06-18 Honeywell Inc Matrix shifter
JPS5081233A (en) * 1973-11-16 1975-07-01
JPS5299027A (en) * 1976-02-16 1977-08-19 Hitachi Ltd Address designating system
JPS52132644A (en) * 1976-02-20 1977-11-07 Intel Corp Method of processing plural digital signals at a time and digital logical circuit for processing digital signals
JPS52138845A (en) * 1976-05-14 1977-11-19 Hitachi Shipbuilding Eng Co Address control circuit for direct data transfer

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60173653A (en) * 1984-02-20 1985-09-07 Oki Electric Ind Co Ltd Dma controller
JPS60173643A (en) * 1984-02-20 1985-09-07 Oki Electric Ind Co Ltd Address generating device
JPS6142035A (en) * 1984-08-03 1986-02-28 Hitachi Ltd Logical type information processor
JPH0427575B2 (en) * 1984-08-03 1992-05-12 Hitachi Seisakusho Kk
JP2011503758A (en) * 2007-11-20 2011-01-27 クゥアルコム・インコーポレイテッド System and method for determining the address of an element in a table

Also Published As

Publication number Publication date
JPS6336017B2 (en) 1988-07-18

Similar Documents

Publication Publication Date Title
AU6392686A (en) Digital intergrated circuit
JPS5690483A (en) Address buffer circuit
JPS5633703A (en) Signal converting circuit
JPS5523501A (en) Shift operation unit
JPS5679352A (en) Address generator
JPS54117640A (en) Memory address designation system
JPS54147738A (en) Data processing system
KR970016939A (en) Random number generator with standby control circuitry that improves the randomness of the number read from the random number generator
JPS54109872A (en) Pla system of electronic type multifunction watch
JPS54119847A (en) Memory unit
JPS55147737A (en) Operation unit for variable pipe line
JPS57209503A (en) Sequence controller
JPS5533235A (en) Microprogram control system
JPS5640949A (en) Parallel arithmetic processor
JPS5674666A (en) Voltage level generator
JPS5622292A (en) Memory element
JPS5642857A (en) Address control device
JPS54137251A (en) Code conversion system
JPS5617454A (en) Information processor
JPS556622A (en) Microprogram sequence control circuuit
JPS5384437A (en) Control system for test pattern generation
JPS5515526A (en) Microprogram control circuit
JPS538031A (en) Address setting system
JPS5378745A (en) Composing system of control memory
JPS54149439A (en) Sequence control circuit