JPS6419599A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS6419599A
JPS6419599A JP62174704A JP17470487A JPS6419599A JP S6419599 A JPS6419599 A JP S6419599A JP 62174704 A JP62174704 A JP 62174704A JP 17470487 A JP17470487 A JP 17470487A JP S6419599 A JPS6419599 A JP S6419599A
Authority
JP
Japan
Prior art keywords
memory
mmr2
evaluate
cpu
independently
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62174704A
Other languages
Japanese (ja)
Inventor
Kazuo Naito
Michio Fujimoto
Masaru Watanabe
Akinori Matsuo
Yoshiharu Nagayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi ULSI Engineering Corp
Hitachi Ltd
Original Assignee
Hitachi ULSI Engineering Corp
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi ULSI Engineering Corp, Hitachi Ltd filed Critical Hitachi ULSI Engineering Corp
Priority to JP62174704A priority Critical patent/JPS6419599A/en
Publication of JPS6419599A publication Critical patent/JPS6419599A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE:To evaluate a function independently, by forming plural evaluation only pads controllable to realize the direct access of a memory not being opened to the outside directly from the outside in the memory. CONSTITUTION:The titled circuit is formed so that the function can be evaluated independently without interposing the access control of a CPU for the memory incorporated in a single chip microcomputer MCU, especially, the memory MMR2 consisting of an EPROM capable of storing a program by bringing the terminal of a tester into contact with the plural evaluation only pads TP. The pad TP is provided with a signal input/output function equivalent to a signal to be transferred between the memory MMR2 and the CPU. And it is possible to separate the defect of the memory MMR2 from that of the CPU surely by enabling the pad to evaluate the memory MMR2 independently. And also, it is possible to shorten an evaluation time to evaluate the computer MCU.
JP62174704A 1987-07-15 1987-07-15 Semiconductor integrated circuit Pending JPS6419599A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62174704A JPS6419599A (en) 1987-07-15 1987-07-15 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62174704A JPS6419599A (en) 1987-07-15 1987-07-15 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS6419599A true JPS6419599A (en) 1989-01-23

Family

ID=15983202

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62174704A Pending JPS6419599A (en) 1987-07-15 1987-07-15 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS6419599A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0757498A (en) * 1993-08-12 1995-03-03 Nippon Motorola Ltd Microcomputer with easily testing circuit
WO2002075341A1 (en) * 2001-03-19 2002-09-26 Hitachi, Ltd. Semiconductor device and its test method
JP2007327963A (en) * 2001-03-19 2007-12-20 Renesas Technology Corp Semiconductor device and test method of semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0757498A (en) * 1993-08-12 1995-03-03 Nippon Motorola Ltd Microcomputer with easily testing circuit
WO2002075341A1 (en) * 2001-03-19 2002-09-26 Hitachi, Ltd. Semiconductor device and its test method
JP2007327963A (en) * 2001-03-19 2007-12-20 Renesas Technology Corp Semiconductor device and test method of semiconductor device
KR100886928B1 (en) * 2001-03-19 2009-03-09 가부시키가이샤 히타치세이사쿠쇼 Semiconductor device and its test method
US7982217B2 (en) 2001-03-19 2011-07-19 Renesas Electronics Corporation Semiconductor device and its test method

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