JPS6419599A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS6419599A JPS6419599A JP62174704A JP17470487A JPS6419599A JP S6419599 A JPS6419599 A JP S6419599A JP 62174704 A JP62174704 A JP 62174704A JP 17470487 A JP17470487 A JP 17470487A JP S6419599 A JPS6419599 A JP S6419599A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- mmr2
- evaluate
- cpu
- independently
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
PURPOSE:To evaluate a function independently, by forming plural evaluation only pads controllable to realize the direct access of a memory not being opened to the outside directly from the outside in the memory. CONSTITUTION:The titled circuit is formed so that the function can be evaluated independently without interposing the access control of a CPU for the memory incorporated in a single chip microcomputer MCU, especially, the memory MMR2 consisting of an EPROM capable of storing a program by bringing the terminal of a tester into contact with the plural evaluation only pads TP. The pad TP is provided with a signal input/output function equivalent to a signal to be transferred between the memory MMR2 and the CPU. And it is possible to separate the defect of the memory MMR2 from that of the CPU surely by enabling the pad to evaluate the memory MMR2 independently. And also, it is possible to shorten an evaluation time to evaluate the computer MCU.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62174704A JPS6419599A (en) | 1987-07-15 | 1987-07-15 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62174704A JPS6419599A (en) | 1987-07-15 | 1987-07-15 | Semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6419599A true JPS6419599A (en) | 1989-01-23 |
Family
ID=15983202
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62174704A Pending JPS6419599A (en) | 1987-07-15 | 1987-07-15 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6419599A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0757498A (en) * | 1993-08-12 | 1995-03-03 | Nippon Motorola Ltd | Microcomputer with easily testing circuit |
WO2002075341A1 (en) * | 2001-03-19 | 2002-09-26 | Hitachi, Ltd. | Semiconductor device and its test method |
JP2007327963A (en) * | 2001-03-19 | 2007-12-20 | Renesas Technology Corp | Semiconductor device and test method of semiconductor device |
-
1987
- 1987-07-15 JP JP62174704A patent/JPS6419599A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0757498A (en) * | 1993-08-12 | 1995-03-03 | Nippon Motorola Ltd | Microcomputer with easily testing circuit |
WO2002075341A1 (en) * | 2001-03-19 | 2002-09-26 | Hitachi, Ltd. | Semiconductor device and its test method |
JP2007327963A (en) * | 2001-03-19 | 2007-12-20 | Renesas Technology Corp | Semiconductor device and test method of semiconductor device |
KR100886928B1 (en) * | 2001-03-19 | 2009-03-09 | 가부시키가이샤 히타치세이사쿠쇼 | Semiconductor device and its test method |
US7982217B2 (en) | 2001-03-19 | 2011-07-19 | Renesas Electronics Corporation | Semiconductor device and its test method |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS647635A (en) | Semiconductor integrated circuit device with gate array and memory | |
DE3681657D1 (en) | CIRCUIT ARRANGEMENT FOR TESTING INTEGRATED CIRCUIT UNITS. | |
EP0111053A3 (en) | On-chip monitor | |
GB2266381B (en) | Parallel test circuit for semiconductor memory device | |
EP0213037A3 (en) | Semiconductor memory device having test pattern generating circuit | |
HK95691A (en) | Monolithic integrated semiconductor device | |
EP0247809A3 (en) | Logic device | |
DE69028435D1 (en) | Integrated circuit with test circuit | |
EP0347905A3 (en) | Circuit for testing circuit blocks controlled by microinstructions | |
JPS6419599A (en) | Semiconductor integrated circuit | |
JPS6491074A (en) | Memory-contained logic lsi and testing thereof | |
DE3686989D1 (en) | REDUCING NOISE DURING CHECKING INTEGRATED CIRCUIT CHIPS. | |
EP0342592A3 (en) | Chip enable input circuit in semiconductor memory device | |
JPS561545A (en) | Input/output buffer cell for semiconductor integrated circuit | |
JPS5319760A (en) | Integrated circuit device | |
JPS5546578A (en) | Method of mounting integrated circuit | |
JPS56124240A (en) | Semiconductor integrated circuit device | |
JPS5515559A (en) | Test input circuit of microcomputer | |
JPS5745942A (en) | Semiconductor integrated circuit device | |
JPS56158442A (en) | Wafer test device | |
JPS56152060A (en) | Semiconductor device | |
JPS6413294A (en) | Semiconductor storage device | |
JPS5481077A (en) | Semiconductor wafer | |
JPS647636A (en) | Semiconductor integrated circuit device with gate array and memory | |
JPS5446476A (en) | Integrated-circuit package |