JPS6413294A - Semiconductor storage device - Google Patents

Semiconductor storage device

Info

Publication number
JPS6413294A
JPS6413294A JP62169248A JP16924887A JPS6413294A JP S6413294 A JPS6413294 A JP S6413294A JP 62169248 A JP62169248 A JP 62169248A JP 16924887 A JP16924887 A JP 16924887A JP S6413294 A JPS6413294 A JP S6413294A
Authority
JP
Japan
Prior art keywords
circuit part
pads
pad
input
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62169248A
Other languages
Japanese (ja)
Inventor
Masumi Nakao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62169248A priority Critical patent/JPS6413294A/en
Publication of JPS6413294A publication Critical patent/JPS6413294A/en
Pending legal-status Critical Current

Links

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

PURPOSE:To independently and safely measure only a memory circuit part by connecting the input/output terminal of the memory circuit part with a chip input/output pad with the aid of selecting signal from outside. CONSTITUTION:The input/output signal line LM of the memory circuit part 1 is connected with a logic circuit 2 and the chip input/output pads I1 and O1 through an N channel MOSFET. A signal line from a switching signal pad SP is connected with the gate of the MOSFET. When the pad SP is low potential, the pads I1 and O1 are connected with a circuit part 2 and the circuit part 2 is connected with the circuit part 2 and the circuit part 2 is connected with the circuit part 1. On the other hand, when the pad SP is high potential, the pads I1 and O1 are directly connected with the circuit part 1 and the circuit 2 is separated. Therefore the memory circuit part 1 can be independently inspected and measured through the pads I1 and O1.
JP62169248A 1987-07-06 1987-07-06 Semiconductor storage device Pending JPS6413294A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62169248A JPS6413294A (en) 1987-07-06 1987-07-06 Semiconductor storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62169248A JPS6413294A (en) 1987-07-06 1987-07-06 Semiconductor storage device

Publications (1)

Publication Number Publication Date
JPS6413294A true JPS6413294A (en) 1989-01-18

Family

ID=15882990

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62169248A Pending JPS6413294A (en) 1987-07-06 1987-07-06 Semiconductor storage device

Country Status (1)

Country Link
JP (1) JPS6413294A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5815426A (en) * 1981-07-21 1983-01-28 三菱電機株式会社 Protecting relay

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5815426A (en) * 1981-07-21 1983-01-28 三菱電機株式会社 Protecting relay

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