JPS5546578A - Method of mounting integrated circuit - Google Patents

Method of mounting integrated circuit

Info

Publication number
JPS5546578A
JPS5546578A JP12077478A JP12077478A JPS5546578A JP S5546578 A JPS5546578 A JP S5546578A JP 12077478 A JP12077478 A JP 12077478A JP 12077478 A JP12077478 A JP 12077478A JP S5546578 A JPS5546578 A JP S5546578A
Authority
JP
Japan
Prior art keywords
pad
inspecting
chip
board
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12077478A
Other languages
Japanese (ja)
Inventor
Tamio Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12077478A priority Critical patent/JPS5546578A/en
Publication of JPS5546578A publication Critical patent/JPS5546578A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Abstract

PURPOSE: To readily replace chips of an integrated circuit by providing inspecting pad integral with a bonding pad on a printed board, inspecting IC chips secured onto the board with inspecting pad, and connecting a signal pattern thereto only when the chip is passed.
CONSTITUTION: A bonding pad 13 and an inspecting pad 14 integral with the pad 13 are formed on a printed board 11, and patterns 16 are arranged in space therewith correspondingly. The board 11 is thus formed, and IC chips 12 are secured onto the central portion of the board 11. Then, pad 12a provided at the chip 12 is bonded to the pad 13 using a wire 17. Then, the inspecting probe is pushed in contact with the pad 14 to thus inspect the chip 12 to connect the pad 14 to the pad 16 connected with a signal pattern 15 only at passing time via a wire 18 and to replace the chip 12 before connecting the pad 14 to the pad 16 at eliminating time.
COPYRIGHT: (C)1980,JPO&Japio
JP12077478A 1978-09-30 1978-09-30 Method of mounting integrated circuit Pending JPS5546578A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12077478A JPS5546578A (en) 1978-09-30 1978-09-30 Method of mounting integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12077478A JPS5546578A (en) 1978-09-30 1978-09-30 Method of mounting integrated circuit

Publications (1)

Publication Number Publication Date
JPS5546578A true JPS5546578A (en) 1980-04-01

Family

ID=14794661

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12077478A Pending JPS5546578A (en) 1978-09-30 1978-09-30 Method of mounting integrated circuit

Country Status (1)

Country Link
JP (1) JPS5546578A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58189969U (en) * 1982-01-29 1983-12-16 株式会社三和電気製作所 Internal magnet type instrument
US5002895A (en) * 1987-04-17 1991-03-26 Thomson-Csf Wire bonding method with a frame, for connecting an electronic component for testing and mounting
US5561086A (en) * 1993-06-18 1996-10-01 Lsi Logic Corporation Techniques for mounting semiconductor dies in die-receiving areas having support structure having notches
KR100224657B1 (en) * 1996-04-06 1999-10-15 윤종용 Pin pad display method of semiconductor ic
EP0867932A3 (en) * 1997-01-31 2000-05-17 Robert Bosch Gmbh Method for making wire connections
WO2001020669A3 (en) * 1999-09-16 2001-10-04 Koninkl Philips Electronics Nv Use of additional bonding finger rows to improve wire bond density

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58189969U (en) * 1982-01-29 1983-12-16 株式会社三和電気製作所 Internal magnet type instrument
JPS6329257Y2 (en) * 1982-01-29 1988-08-05
US5002895A (en) * 1987-04-17 1991-03-26 Thomson-Csf Wire bonding method with a frame, for connecting an electronic component for testing and mounting
US5561086A (en) * 1993-06-18 1996-10-01 Lsi Logic Corporation Techniques for mounting semiconductor dies in die-receiving areas having support structure having notches
KR100224657B1 (en) * 1996-04-06 1999-10-15 윤종용 Pin pad display method of semiconductor ic
EP0867932A3 (en) * 1997-01-31 2000-05-17 Robert Bosch Gmbh Method for making wire connections
US6232561B1 (en) 1997-01-31 2001-05-15 Robert Bosch Gmbh Process for producing wire connections on an electronic component assembly carrier made by the process
WO2001020669A3 (en) * 1999-09-16 2001-10-04 Koninkl Philips Electronics Nv Use of additional bonding finger rows to improve wire bond density

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